nuvoTon NUC121AE_v1 2024.04.28 NUC121AE_v1 SVD file 8 32 ADC ADC Register Map ADC 0x0 0x0 0x30 registers n 0x100 0x4 registers n 0x74 0x8 registers n 0x80 0x20 registers n ADCHER ADC_ADCHER ADC Channel Enable Register 0x84 read-write n 0x0 0x0 CHEN Analog Input Channel Enable Control\nSet CHEN[11:0] to enable the corresponding analog input channel 11 ~ 0. If DIFFEN bit is set to 1, only the even number channel needs to be enabled.\nBesides, set CHEN[29] to CHEN[30] will enable internal channel for band-gap voltage and temperature sensor respectively. Other bits are reserved.\nNote 1 : If the internal channel for band-gap voltage (CHEN[29]) is active, the maximum sampling rate will be TBD SPS\nNote 2 : If the internal channel for temperature sensor (CHEN[30]) is active, the maximum sampling rate will be 300k SPS 0 32 read-write 0 Channel Disabled 0 1 Channel Enabled 1 ADCMPR0 ADC_ADCMPR0 ADC Compare Register 0 0x88 read-write n 0x0 0x0 CMPCH Compare Channel Selection\n 3 5 read-write 0 Channel 0 conversion result is selected to be compared #00000 1 Channel 1 conversion result is selected to be compared #00001 2 Channel 2 conversion result is selected to be compared #00010 3 Channel 3 conversion result is selected to be compared #00011 4 Channel 4 conversion result is selected to be compared #00100 5 Channel 5 conversion result is selected to be compared #00101 6 Channel 6 conversion result is selected to be compared #00110 7 Channel 7 conversion result is selected to be compared #00111 8 Channel 8 conversion result is selected to be compared #01000 9 Channel 9 conversion result is selected to be compared #01001 10 Channel 10 conversion result is selected to be compared #01010 11 Channel 11 conversion result is selected to be compared #01011 29 Band-gap voltage conversion result is selected to be compared #11101 30 Temperature sensor conversion result is selected to be compared #11110 CMPCOND Compare Condition\nNote: When the compare result meets the condition setting, the internal match counter will increase 1, otherwise, the internal match counter will be cleared to 0.\nNote: When the internal counter reaches to (CMPMATCNT +1), the CMPFx bit will be set. 2 1 read-write 0 Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one #0 1 Set the compare condition as that when a 12-bit A/D conversion result is greater than or equal to the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one #1 CMPD Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nNote: CMPD should be filled in unsigned format (straight binary format). 16 12 read-write CMPEN Compare Enable Control Bit\nSet this bit to 1 to enable ADC controller to compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADDR register.\n 0 1 read-write 0 Compare function Disabled #0 1 Compare function Enabled #1 CMPIE Compare Interrupt Enable Control Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPFx bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated.\n 1 1 read-write 0 Compare function interrupt Disabled #0 1 Compare function interrupt Enabled #1 CMPMATCNT Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND, the internal match counter will increase 1, otherwise, the internal match counter will be cleared to 0. When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set. 8 4 read-write CMPWEN Compare Window Mode Enable Bit\nNote: This bit is only presented in ADCMPR0 register. 15 1 read-write 0 Compare Window Mode Disabled #0 1 Compare Window Mode Enabled #1 ADCMPR1 ADC_ADCMPR1 ADC Compare Register 1 0x8C read-write n 0x0 0x0 ADCR ADC_ADCR ADC Control Register 0x80 read-write n 0x0 0x0 ADEN A/D Converter Enable Bit\nNote: Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption. 0 1 read-write 0 A/D converter Disabled #0 1 A/D converter Enabled #1 ADIE A/D Interrupt Enable Control\nA/D conversion end interrupt request is generated if ADIE bit is set to 1.\n 1 1 read-write 0 A/D interrupt function Disabled #0 1 A/D interrupt function Enabled #1 ADMD A/D Converter Operation Mode Control\nNote1: When changing the operation mode, software should clear ADST bit first.\nNote2: In Burst mode, the A/D result data always at Data Register 0. 2 2 read-write 0 Single conversion #00 1 Burst conversion #01 2 Single-cycle Scan #10 3 Continuous Scan #11 ADST A/D Conversion Start\nADST bit can be set to 1 from four sources: software, external pin STADC, PWM trigger and Timer trigger. ADST will be cleared to 0 by hardware automatically at the ends of Single mode and Single-cycle Scan mode. In Continuous Scan mode and Burst mode, A/D conversion is continuously performed until software writes 0 to this bit or chip is reset.\n 11 1 read-write 0 Conversion stops and A/D converter enters idle state #0 1 Conversion starts #1 DIFFEN Differential Input Mode Control\nNote: In Differential Input mode, only the even number of the two corresponding channels needs to be enabled in ADCHER register. The conversion result will be placed to the corresponding data register of the enabled channel. 10 1 read-write 0 Single-end analog input mode #0 1 Differential analog input mode #1 DMOF Differential Input Mode Output Format\nIf user enables differential input mode, the conversion result can be expressed with binary straight format (unsigned format) or 2's complement format (signed format).\n 31 1 read-write 0 A/D Conversion result will be filled in RSLT at ADDRx registers with unsigned format (straight binary format) #0 1 A/D Conversion result will be filled in RSLT at ADDRx registers with 2's complement format #1 PTEN PDMA Transfer Enable Bit\nWhen A/D conversion is completed, the converted data is loaded into ADDR0~11, ADDR29~ADDR30. Software can enable this bit to generate a PDMA data transfer request.\n 9 1 read-write 0 PDMA data transfer Disabled #0 1 PDMA data transfer in ADDR0~11, ADDR29~ADDR30 Enabled #1 SMPTSEL ADC Internal Sampling Time Selection\n 16 3 read-write 0 2 ADC clock for sampling ; 14 ADC clock for complete conversion #000 1 3 ADC clock for sampling ; 15 ADC clock for complete conversion #001 2 4 ADC clock for sampling ; 16 ADC clock for complete conversion #010 3 5 ADC clock for sampling ; 17 ADC clock for complete conversion #011 4 6 ADC clock for sampling ; 18 ADC clock for complete conversion #100 5 7 ADC clock for sampling ; 19 ADC clock for complete conversion #101 6 8 ADC clock for sampling ; 20 ADC clock for complete conversion #110 7 9 ADC clock for sampling ; 21 ADC clock for complete conversion #111 TRGCOND External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and at least 4 PCLKs for edge trigger.\n 6 2 read-write 0 Low level #00 1 High level #01 2 Falling edge #10 3 Rising edge #11 TRGEN External Trigger Enable Control\nEnable or disable triggering of A/D conversion by external STADC pin, PWM trigger and Timer trigger. If external trigger is enabled, the ADST bit can be set to 1 by the selected hardware trigger source.\nNote: The ADC external trigger function is only supported in Single-cycle Scan mode. 8 1 read-write 0 External trigger Disabled #0 1 External trigger Enabled #1 TRGS Hardware Trigger Source\nNote: Software should clear TRGEN bit and ADST bit to 0 before changing TRGS. 4 2 read-write 0 A/D conversion is started by external STADC pin #00 1 Timer0 ~ Timer3 overflow pulse trigger #01 2 Reserved #10 3 A/D conversion is started by PWM trigger #11 ADDR0 ADC_ADDR0 ADC Data Register 0 0x0 read-only n 0x0 0x0 OVERRUN Overrun Flag\nIf converted data in RSLT has not been read before new conversion result is loaded to this register, OVERRUN is set to 1. It is cleared by hardware after ADDR register is read\n 16 1 read-only 0 Data in RSLT is not overwrote #0 1 Data in RSLT is overwrote. #1 RSLT A/D Conversion Result\nThis field contains conversion result of ADC. 0 16 read-only VALID Valid Flag \nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read\n 17 1 read-only 0 Data in RSLT bits is not valid #0 1 Data in RSLT bits is valid #1 ADDR1 ADC_ADDR1 ADC Data Register 1 0x4 read-write n 0x0 0x0 ADDR10 ADC_ADDR10 ADC Data Register 10 0x28 read-write n 0x0 0x0 ADDR11 ADC_ADDR11 ADC Data Register 11 0x2C read-write n 0x0 0x0 ADDR2 ADC_ADDR2 ADC Data Register 2 0x8 read-write n 0x0 0x0 ADDR29 ADC_ADDR29 ADC Data Register 29 0x74 read-write n 0x0 0x0 ADDR3 ADC_ADDR3 ADC Data Register 3 0xC read-write n 0x0 0x0 ADDR30 ADC_ADDR30 ADC Data Register 30 0x78 read-write n 0x0 0x0 ADDR4 ADC_ADDR4 ADC Data Register 4 0x10 read-write n 0x0 0x0 ADDR5 ADC_ADDR5 ADC Data Register 5 0x14 read-write n 0x0 0x0 ADDR6 ADC_ADDR6 ADC Data Register 6 0x18 read-write n 0x0 0x0 ADDR7 ADC_ADDR7 ADC Data Register 7 0x1C read-write n 0x0 0x0 ADDR8 ADC_ADDR8 ADC Data Register 8 0x20 read-write n 0x0 0x0 ADDR9 ADC_ADDR9 ADC Data Register 9 0x24 read-write n 0x0 0x0 ADPDMA ADC_ADPDMA ADC PDMA Current Transfer Data Register 0x100 read-only n 0x0 0x0 CURDAT ADC PDMA Current Transfer Data Register\nWhen PDMA transferring, read this register can monitor current PDMA transfer data.\nCurrent PDMA transfer data could be the content of ADDR0 ~ ADDR11 and ADDR29 ~ ADDR30.\nThis is a read only register. 0 18 read-only ADSR0 ADC_ADSR0 ADC Status Register0 0x90 read-write n 0x0 0x0 ADF A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion. Software can write 1 to clear this bit.\nADF is set to 1 at the following three conditions:\nWhen A/D conversion ends in Single mode.\nWhen A/D conversion ends on all specified channels in Single-cycle Scan mode and Continuous Scan mode.\nWhen more than 8 samples in FIFO in Burst mode. 0 1 read-write BUSY BUSY/IDLE\nThis bit is a mirror of ADST bit in ADCR register. It is read only.\n 7 1 read-write 0 A/D converter is in idle state #0 1 A/D converter is busy at conversion #1 CHANNEL Current Conversion Channel\nIt is read only. 27 5 read-write CMPF0 Compare Flag 0\nWhen the A/D conversion result of the selected channel meets setting condition in ADCMPR0 then this bit is set to 1. This bit is cleared by writing 1 to it.\n 1 1 read-write 0 Conversion result in ADDR does not meet ADCMPR0 setting #0 1 Conversion result in ADDR meets ADCMPR0 setting #1 CMPF1 Compare Flag 1\nWhen the A/D conversion result of the selected channel meets setting condition in ADCMPR1 then this bit is set to 1; it is cleared by writing 1 to it\n 2 1 read-write 0 Conversion result in ADDR does not meet ADCMPR1 setting #0 1 Conversion result in ADDR meets ADCMPR1 setting #1 OVERRUNF Overrun Flag\nIf any one of OVERRUN (ADDRx[16]) is set, this flag will be set to 1. This is a read only bit.\nNote: When ADC is in burst mode and the FIFO is overrun, this flag will be set to 1. 16 1 read-write VALIDF Data Valid Flag\nIf any one of VALID (ADDRx[17]) is set, this flag will be set to 1. This is a read only bit.\nNote: When ADC is in burst mode and any conversion result is valid, this flag will be set to 1 8 1 read-write ADSR1 ADC_ADSR1 ADC Status Register1 0x94 read-only n 0x0 0x0 VALID Data Valid Flag\nVALID[30:29, 11:0] are the mirror of the VALID bits in ADDR30[17] ~ ADDR29[17], ADDR11[17]~ ADDR0[17]. The other bits are reserved. \nNote: When ADC is in burst mode and any conversion result is valid, VALID[30:29, 11:0] will be set to 1. 0 32 read-only ADSR2 ADC_ADSR2 ADC Status Register2 0x98 read-only n 0x0 0x0 OVERRUN Overrun Flag\nOVERRUN[30:29, 11:0] are the mirror of the OVERRUN bit in ADDR30[16] ~ADDR29[16], ADDR11[16] ~ ADDR0[16]. The other bits are reserved. \nNote: When ADC is in burst mode and the FIFO is overrun, OVERRUN[30:29, 11:0] will be set to 1. 0 32 read-only ADTDCR ADC_ADTDCR ADC Trigger Delay Control Register 0x9C read-write n 0x0 0x0 PTDT PWM Trigger Delay Time\nSet this field will delay ADC start conversion time after PWM trigger.\nPWM trigger delay time is (4 * PTDT) * system clock 0 8 read-write BPWM0 BPWM Register Map BPWM 0x0 0x0 0x8 registers n 0x10 0x8 registers n 0x110 0x8 registers n 0x120 0x4 registers n 0x20 0x8 registers n 0x200 0x3C registers n 0x250 0x8 registers n 0x30 0x4 registers n 0x304 0x4 registers n 0x31C 0x18 registers n 0x50 0x18 registers n 0x90 0x4 registers n 0xB0 0x10 registers n 0xD4 0x8 registers n 0xE0 0x4 registers n 0xE8 0x4 registers n 0xF8 0x8 registers n BPWM_ADCTS0 BPWM_ADCTS0 BPWM Trigger ADC Source Select Register 0 0xF8 read-write n 0x0 0x0 TRGEN0 BPWM_CH0 Trigger ADC Enable Bit 7 1 read-write TRGEN1 BPWM_CH1 Trigger ADC Enable Bit 15 1 read-write TRGEN2 BPWM_CH2 Trigger ADC Enable Bit 23 1 read-write TRGEN3 BPWM_CH3 Trigger ADC Enable Bit 31 1 read-write TRGSEL0 BPWM_CH0 Trigger ADC Source Select\n 0 4 read-write 0 BPWM_CH0 zero point #0000 1 BPWM_CH0 period point #0001 2 BPWM_CH0 zero or period point #0010 3 BPWM_CH0 up-count CMPDAT point #0011 4 BPWM_CH0 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 BPWM_CH1 up-count CMPDAT point #1000 9 BPWM_CH1 down-count CMPDAT point #1001 TRGSEL1 BPWM_CH1 Trigger ADC Source Select\n 8 4 read-write 0 BPWM_CH0 zero point #0000 1 BPWM_CH0 period point #0001 2 BPWM_CH0 zero or period point #0010 3 BPWM_CH0 up-count CMPDAT point #0011 4 BPWM_CH0 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 BPWM_CH1 up-count CMPDAT point #1000 9 BPWM_CH1 down-count CMPDAT point #1001 TRGSEL2 BPWM_CH2 Trigger ADC Source Select\nOthers reserved. 16 4 read-write 0 BPWM_CH2 zero point #0000 1 BPWM_CH2 period point #0001 2 BPWM_CH2 zero or period point #0010 3 BPWM_CH2 up-count CMPDAT point #0011 4 BPWM_CH2 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 BPWM_CH3 up-count CMPDAT point #1000 9 BPWM_CH3 down-count CMPDAT point #1001 TRGSEL3 BPWM_CH3 Trigger ADC Source Select\n 24 4 read-write 0 BPWM_CH2 zero point #0000 1 BPWM_CH2 period point #0001 2 BPWM_CH2 zero or period point #0010 3 BPWM_CH2 up-count CMPDAT point #0011 4 BPWM_CH2 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 BPWM_CH3 up-count CMPDAT point #1000 9 BPWM_CH3 down-count CMPDAT point #1001 BPWM_ADCTS1 BPWM_ADCTS1 BPWM Trigger ADC Source Select Register 1 0xFC read-write n 0x0 0x0 TRGEN4 BPWM_CH4 Trigger ADC Enable Bit 7 1 read-write TRGEN5 BPWM_CH5 Trigger ADC Enable Bit 15 1 read-write TRGSEL4 BPWM_CH4 Trigger ADC Source Select\n 0 4 read-write 0 BPWM_CH4 zero point #0000 1 BPWM_CH4 period point #0001 2 BPWM_CH4 zero or period point #0010 3 BPWM_CH4 up-count CMPDAT point #0011 4 BPWM_CH4 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 BPWM_CH5 up-count CMPDAT point #1000 9 BPWM_CH5 down-count CMPDAT point #1001 TRGSEL5 BPWM_CH5 Trigger ADC Source Select\n 8 4 read-write 0 BPWM_CH4 zero point #0000 1 BPWM_CH4 period point #0001 2 BPWM_CH4 zero or period point #0010 3 BPWM_CH4 up-count CMPDAT point #0011 4 BPWM_CH4 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 BPWM_CH5 up-count CMPDAT point #1000 9 BPWM_CH5 down-count CMPDAT point #1001 BPWM_CAPCTL BPWM_CAPCTL BPWM Capture Control Register 0x204 read-write n 0x0 0x0 CAPENn Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated 0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) 1 CAPINVn Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.\n 8 6 read-write 0 Capture source inverter Disabled 0 1 Capture source inverter Enabled. Reverse the input signal from GPIO 1 FCRLDENn Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.\n 24 6 read-write 0 Falling capture reload counter Disabled 0 1 Falling capture reload counter Enabled 1 RCRLDENn Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.\n 16 6 read-write 0 Rising capture reload counter Disabled 0 1 Rising capture reload counter Enabled 1 BPWM_CAPIEN BPWM_CAPIEN BPWM Capture Interrupt Enable Register 0x250 read-write n 0x0 0x0 CAPFIENn BPWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.\n 8 6 read-write 0 Capture falling edge latch interrupt Disabled 0 1 Capture falling edge latch interrupt Enabled 1 CAPRIENn BPWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 Capture rising edge latch interrupt Disabled 0 1 Capture rising edge latch interrupt Enabled 1 BPWM_CAPIF BPWM_CAPIF BPWM Capture Interrupt Flag Register 0x254 read-write n 0x0 0x0 CFLIFn BPWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.\n 8 6 read-write 0 No capture falling latch condition happened 0 1 Capture falling latch condition happened, this flag will be set to high 1 CRLIFn BPWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 No capture rising latch condition happened 0 1 Capture rising latch condition happened, this flag will be set to high 1 BPWM_CAPINEN BPWM_CAPINEN BPWM Capture Input Enable Register 0x200 read-write n 0x0 0x0 CAPINENn Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin 1 BPWM_CAPSTS BPWM_CAPSTS BPWM Capture Status Register 0x208 read-only n 0x0 0x0 CFLIFOVn Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF. 8 6 read-only CRLIFOVn Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF. 0 6 read-only BPWM_CLKPSC BPWM_CLKPSC BPWM Clock Pre-scale Register 0x14 read-write n 0x0 0x0 CLKPSC BPWM Counter Clock Pre-scale \nThe clock of BPWM counter is decided by clock prescaler. Each BPWM pair share one BPWM counter clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1). 0 12 read-write BPWM_CLKSRC BPWM_CLKSRC BPWM Clock Source Register 0x10 read-write n 0x0 0x0 ECLKSRC0 BPWM_CH0/1 External Clock Source Select\n 0 3 read-write 0 BPWMx_CLK, x denotes 0, 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 BPWM_CMPBUF0 BPWM_CMPBUF0 BPWM CMPDAT0 Buffer 0x31C read-only n 0x0 0x0 CMPBUF BPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register. 0 16 read-only BPWM_CMPBUF1 BPWM_CMPBUF1 BPWM CMPDAT1 Buffer 0x320 read-write n 0x0 0x0 BPWM_CMPBUF2 BPWM_CMPBUF2 BPWM CMPDAT2 Buffer 0x324 read-write n 0x0 0x0 BPWM_CMPBUF3 BPWM_CMPBUF3 BPWM CMPDAT3 Buffer 0x328 read-write n 0x0 0x0 BPWM_CMPBUF4 BPWM_CMPBUF4 BPWM CMPDAT4 Buffer 0x32C read-write n 0x0 0x0 BPWM_CMPBUF5 BPWM_CMPBUF5 BPWM CMPDAT5 Buffer 0x330 read-write n 0x0 0x0 BPWM_CMPDAT0 BPWM_CMPDAT0 BPWM Comparator Register 0 0x50 read-write n 0x0 0x0 CMP BPWM Comparator Register\nCMP use to compare with CNT to generate BPWM waveform, interrupt and trigger ADC.\nIn independent mode, BPWM_CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point. 0 16 read-write BPWM_CMPDAT1 BPWM_CMPDAT1 BPWM Comparator Register 1 0x54 read-write n 0x0 0x0 BPWM_CMPDAT2 BPWM_CMPDAT2 BPWM Comparator Register 2 0x58 read-write n 0x0 0x0 BPWM_CMPDAT3 BPWM_CMPDAT3 BPWM Comparator Register 3 0x5C read-write n 0x0 0x0 BPWM_CMPDAT4 BPWM_CMPDAT4 BPWM Comparator Register 4 0x60 read-write n 0x0 0x0 BPWM_CMPDAT5 BPWM_CMPDAT5 BPWM Comparator Register 5 0x64 read-write n 0x0 0x0 BPWM_CNT BPWM_CNT BPWM Counter Register 0 0x90 read-only n 0x0 0x0 CNT BPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter. 0 16 read-only DIRF BPWM Direction Indicator Flag (Read Only)\n 16 1 read-only 0 Counter is Down count #0 1 Counter is UP count #1 BPWM_CNTCLR BPWM_CNTCLR BPWM Clear Counter Register 0x24 read-write n 0x0 0x0 CNTCLR0 Clear BPWM Counter Control Bit 0\nIt is automatically cleared by hardware.\n 0 1 read-write 0 No effect #0 1 Clear 16-bit BPWM counter to 0000H #1 BPWM_CNTEN BPWM_CNTEN BPWM Counter Enable Register 0x20 read-write n 0x0 0x0 CNTEN0 BPWM Counter Enable 0\n 0 1 read-write 0 BPWM Counter and clock prescaler Stop Running #0 1 BPWM Counter and clock prescaler Start Running #1 BPWM_CTL0 BPWM_CTL0 BPWM Control Register 0 0x0 read-write n 0x0 0x0 CTRLDn Center Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 0 1 read-write 0 Center Lodaing mode is disable for corresponding BPWM channel n #0 1 Center Lodaing mode is enable for corresponding BPWM channel n #1 DBGHALT ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 30 1 read-write 0 ICE debug mode counter halt disable #0 1 ICE debug mode counter halt enable #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable (Write Protect)\nBPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects BPWM output #0 1 ICE debug mode acknowledgement disabled #1 IMMLDENn Immediately Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled, CTRLDn will be invalid. 16 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 BPWM_CTL1 BPWM_CTL1 BPWM Control Register 1 0x4 read-write n 0x0 0x0 CNTTYPE0 BPWM Counter Behavior Type 0\n 0 2 read-write 0 Up counter type (supports in capture mode) #00 1 Down count type (supports in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 BPWM_FCAPDAT0 BPWM_FCAPDAT0 BPWM Falling Capture Data Register 0 0x210 read-only n 0x0 0x0 FCAPDAT BPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened, the BPWM counter value will be saved in this register. 0 16 read-only BPWM_FCAPDAT1 BPWM_FCAPDAT1 BPWM Falling Capture Data Register 1 0x218 read-write n 0x0 0x0 BPWM_FCAPDAT2 BPWM_FCAPDAT2 BPWM Falling Capture Data Register 2 0x220 read-write n 0x0 0x0 BPWM_FCAPDAT3 BPWM_FCAPDAT3 BPWM Falling Capture Data Register 3 0x228 read-write n 0x0 0x0 BPWM_FCAPDAT4 BPWM_FCAPDAT4 BPWM Falling Capture Data Register 4 0x230 read-write n 0x0 0x0 BPWM_FCAPDAT5 BPWM_FCAPDAT5 BPWM Falling Capture Data Register 5 0x238 read-write n 0x0 0x0 BPWM_INTEN BPWM_INTEN BPWM Interrupt Enable Register 0xE0 read-write n 0x0 0x0 CMPDIENn BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.\n 24 6 read-write 0 Compare down count interrupt Disabled 0 1 Compare down count interrupt Enabled 1 CMPUIENn BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.\n. 16 6 read-write 0 Compare up count interrupt Disabled 0 1 Compare up count interrupt Enabled 1 PIEN0 BPWM Period Point Interrupt Enable 0\nNote: When up-down counter type period point means center point. 8 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 ZIEN0 BPWM Zero Point Interrupt Enable 0\n 0 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 BPWM_INTSTS0 BPWM_INTSTS0 BPWM Interrupt Flag Register 0 0xE8 read-write n 0x0 0x0 CMPDIFn BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 24 6 read-write CMPUIFn BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 16 6 read-write PIF0 BPWM Period Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to zero. 8 1 read-write ZIF0 BPWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches zero, software can write 1 to clear this bit to zero. 0 1 read-write BPWM_MSK BPWM_MSK BPWM Mask Data Register 0xBC read-write n 0x0 0x0 MSKDATn BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 Output logic low to BPWMn 0 1 Output logic high to BPWMn 1 BPWM_MSKEN BPWM_MSKEN BPWM Mask Enable Register 0xB8 read-write n 0x0 0x0 MSKENn BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. \n 0 6 read-write 0 BPWM output signal is non-masked 0 1 BPWM output signal is masked and output MSKDATn data 1 BPWM_PBUF BPWM_PBUF BPWM PERIOD Buffer 0x304 read-only n 0x0 0x0 PBUF BPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register. 0 16 read-only BPWM_PERIOD BPWM_PERIOD BPWM Period Register 0x30 read-write n 0x0 0x0 PERIOD BPWM Period Register\nUp-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0.\nDown-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD.\n 0 16 read-write BPWM_POEN BPWM_POEN BPWM Output Enable Register 0xD8 read-write n 0x0 0x0 POENn BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 BPWM pin at tri-state 0 1 BPWM pin in output mode 1 BPWM_POLCTL BPWM_POLCTL BPWM Pin Polar Inverse Register 0xD4 read-write n 0x0 0x0 PINVn BPWM PIN Polar Inverse Control Bits\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 BPWM output polar inverse Disabled 0 1 BPWM output polar inverse Enabled 1 BPWM_RCAPDAT0 BPWM_RCAPDAT0 BPWM Rising Capture Data Register 0 0x20C read-only n 0x0 0x0 RCAPDAT BPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened, the BPWM counter value will be saved in this register. 0 16 read-only BPWM_RCAPDAT1 BPWM_RCAPDAT1 BPWM Rising Capture Data Register 1 0x214 read-write n 0x0 0x0 BPWM_RCAPDAT2 BPWM_RCAPDAT2 BPWM Rising Capture Data Register 2 0x21C read-write n 0x0 0x0 BPWM_RCAPDAT3 BPWM_RCAPDAT3 BPWM Rising Capture Data Register 3 0x224 read-write n 0x0 0x0 BPWM_RCAPDAT4 BPWM_RCAPDAT4 BPWM Rising Capture Data Register 4 0x22C read-write n 0x0 0x0 BPWM_RCAPDAT5 BPWM_RCAPDAT5 BPWM Rising Capture Data Register 5 0x234 read-write n 0x0 0x0 BPWM_SSCTL BPWM_SSCTL BPWM Synchronous Start Control Register 0x110 read-write n 0x0 0x0 SSEN0 BPWM Synchronous Start Function Enable 0\nWhen synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN). \n 0 1 read-write 0 BPWM synchronous start function Disabled #0 1 BPWM synchronous start function Enabled #1 SSRC BPWM Synchronous Start Source Select\n 8 2 read-write 0 Synchronous start source come from BPWM0 #00 1 Synchronous start source come from BPWM1 #01 2 Synchronous start source come from PWM0 #10 3 Synchronous start source come from PWM1 #11 BPWM_SSTRG BPWM_SSTRG BPWM Synchronous Start Trigger Register 0x114 write-only n 0x0 0x0 CNTSEN BPWM Counter Synchronous Start Enable (Write Only)\nWriting this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated BPWM channel counter synchronous start function is enabled. 0 1 write-only BPWM_STATUS BPWM_STATUS BPWM Status Register 0x120 read-write n 0x0 0x0 ADCTRGn ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\n 16 6 read-write 0 Indicates no ADC start of conversion trigger event has occurred 0 1 Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit 1 CNTMAX0 Time-base Counter 0 Equal to 0xFFFF Latched Status\n 0 1 read-write 0 Indicates the time-base counter never reached its maximum value 0xFFFF #0 1 Indicates the time-base counter reached its maximum value, software can write 1 to clear this bit #1 BPWM_WGCTL0 BPWM_WGCTL0 BPWM Generation Register 0 0xB0 read-write n 0x0 0x0 PRDPCTLn BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIODn+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type. 16 12 read-write 0 Do nothing 00 1 BPWM period (center) point output Low 01 10 BPWM period (center) point output High 10 11 BPWM period (center) point output Toggle 11 ZPCTLn BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to zero. 0 12 read-write 0 Do nothing 00 1 BPWM zero point output Low 01 10 BPWM zero point output High 10 11 BPWM zero point output Toggle 11 BPWM_WGCTL1 BPWM_WGCTL1 BPWM Generation Register 1 0xB4 read-write n 0x0 0x0 CMPDCTLn BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT. 16 12 read-write 0 Do nothing 00 1 BPWM compare down point output Low 01 10 BPWM compare down point output High 10 11 BPWM compare down point output Toggle 11 CMPUCTLn BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT. 0 12 read-write 0 Do nothing 00 1 BPWM compare up point output Low 01 10 BPWM compare up point output High 10 11 BPWM compare up point output Toggle 11 BPWM1 BPWM Register Map BPWM 0x0 0x0 0x8 registers n 0x10 0x8 registers n 0x110 0x8 registers n 0x120 0x4 registers n 0x20 0x8 registers n 0x200 0x3C registers n 0x250 0x8 registers n 0x30 0x4 registers n 0x304 0x4 registers n 0x31C 0x18 registers n 0x50 0x18 registers n 0x90 0x4 registers n 0xB0 0x10 registers n 0xD4 0x8 registers n 0xE0 0x4 registers n 0xE8 0x4 registers n 0xF8 0x8 registers n BPWM_ADCTS0 BPWM_ADCTS0 BPWM Trigger ADC Source Select Register 0 0xF8 read-write n 0x0 0x0 TRGEN0 BPWM_CH0 Trigger ADC Enable Bit 7 1 read-write TRGEN1 BPWM_CH1 Trigger ADC Enable Bit 15 1 read-write TRGEN2 BPWM_CH2 Trigger ADC Enable Bit 23 1 read-write TRGEN3 BPWM_CH3 Trigger ADC Enable Bit 31 1 read-write TRGSEL0 BPWM_CH0 Trigger ADC Source Select\n 0 4 read-write 0 BPWM_CH0 zero point #0000 1 BPWM_CH0 period point #0001 2 BPWM_CH0 zero or period point #0010 3 BPWM_CH0 up-count CMPDAT point #0011 4 BPWM_CH0 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 BPWM_CH1 up-count CMPDAT point #1000 9 BPWM_CH1 down-count CMPDAT point #1001 TRGSEL1 BPWM_CH1 Trigger ADC Source Select\n 8 4 read-write 0 BPWM_CH0 zero point #0000 1 BPWM_CH0 period point #0001 2 BPWM_CH0 zero or period point #0010 3 BPWM_CH0 up-count CMPDAT point #0011 4 BPWM_CH0 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 BPWM_CH1 up-count CMPDAT point #1000 9 BPWM_CH1 down-count CMPDAT point #1001 TRGSEL2 BPWM_CH2 Trigger ADC Source Select\nOthers reserved. 16 4 read-write 0 BPWM_CH2 zero point #0000 1 BPWM_CH2 period point #0001 2 BPWM_CH2 zero or period point #0010 3 BPWM_CH2 up-count CMPDAT point #0011 4 BPWM_CH2 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 BPWM_CH3 up-count CMPDAT point #1000 9 BPWM_CH3 down-count CMPDAT point #1001 TRGSEL3 BPWM_CH3 Trigger ADC Source Select\n 24 4 read-write 0 BPWM_CH2 zero point #0000 1 BPWM_CH2 period point #0001 2 BPWM_CH2 zero or period point #0010 3 BPWM_CH2 up-count CMPDAT point #0011 4 BPWM_CH2 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 BPWM_CH3 up-count CMPDAT point #1000 9 BPWM_CH3 down-count CMPDAT point #1001 BPWM_ADCTS1 BPWM_ADCTS1 BPWM Trigger ADC Source Select Register 1 0xFC read-write n 0x0 0x0 TRGEN4 BPWM_CH4 Trigger ADC Enable Bit 7 1 read-write TRGEN5 BPWM_CH5 Trigger ADC Enable Bit 15 1 read-write TRGSEL4 BPWM_CH4 Trigger ADC Source Select\n 0 4 read-write 0 BPWM_CH4 zero point #0000 1 BPWM_CH4 period point #0001 2 BPWM_CH4 zero or period point #0010 3 BPWM_CH4 up-count CMPDAT point #0011 4 BPWM_CH4 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 BPWM_CH5 up-count CMPDAT point #1000 9 BPWM_CH5 down-count CMPDAT point #1001 TRGSEL5 BPWM_CH5 Trigger ADC Source Select\n 8 4 read-write 0 BPWM_CH4 zero point #0000 1 BPWM_CH4 period point #0001 2 BPWM_CH4 zero or period point #0010 3 BPWM_CH4 up-count CMPDAT point #0011 4 BPWM_CH4 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 BPWM_CH5 up-count CMPDAT point #1000 9 BPWM_CH5 down-count CMPDAT point #1001 BPWM_CAPCTL BPWM_CAPCTL BPWM Capture Control Register 0x204 read-write n 0x0 0x0 CAPENn Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated 0 1 Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) 1 CAPINVn Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.\n 8 6 read-write 0 Capture source inverter Disabled 0 1 Capture source inverter Enabled. Reverse the input signal from GPIO 1 FCRLDENn Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.\n 24 6 read-write 0 Falling capture reload counter Disabled 0 1 Falling capture reload counter Enabled 1 RCRLDENn Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.\n 16 6 read-write 0 Rising capture reload counter Disabled 0 1 Rising capture reload counter Enabled 1 BPWM_CAPIEN BPWM_CAPIEN BPWM Capture Interrupt Enable Register 0x250 read-write n 0x0 0x0 CAPFIENn BPWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.\n 8 6 read-write 0 Capture falling edge latch interrupt Disabled 0 1 Capture falling edge latch interrupt Enabled 1 CAPRIENn BPWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 Capture rising edge latch interrupt Disabled 0 1 Capture rising edge latch interrupt Enabled 1 BPWM_CAPIF BPWM_CAPIF BPWM Capture Interrupt Flag Register 0x254 read-write n 0x0 0x0 CFLIFn BPWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.\n 8 6 read-write 0 No capture falling latch condition happened 0 1 Capture falling latch condition happened, this flag will be set to high 1 CRLIFn BPWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 No capture rising latch condition happened 0 1 Capture rising latch condition happened, this flag will be set to high 1 BPWM_CAPINEN BPWM_CAPINEN BPWM Capture Input Enable Register 0x200 read-write n 0x0 0x0 CAPINENn Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0 0 1 BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin 1 BPWM_CAPSTS BPWM_CAPSTS BPWM Capture Status Register 0x208 read-only n 0x0 0x0 CFLIFOVn Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF. 8 6 read-only CRLIFOVn Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF. 0 6 read-only BPWM_CLKPSC BPWM_CLKPSC BPWM Clock Pre-scale Register 0x14 read-write n 0x0 0x0 CLKPSC BPWM Counter Clock Pre-scale \nThe clock of BPWM counter is decided by clock prescaler. Each BPWM pair share one BPWM counter clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1). 0 12 read-write BPWM_CLKSRC BPWM_CLKSRC BPWM Clock Source Register 0x10 read-write n 0x0 0x0 ECLKSRC0 BPWM_CH0/1 External Clock Source Select\n 0 3 read-write 0 BPWMx_CLK, x denotes 0, 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 BPWM_CMPBUF0 BPWM_CMPBUF0 BPWM CMPDAT0 Buffer 0x31C read-only n 0x0 0x0 CMPBUF BPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register. 0 16 read-only BPWM_CMPBUF1 BPWM_CMPBUF1 BPWM CMPDAT1 Buffer 0x320 read-write n 0x0 0x0 BPWM_CMPBUF2 BPWM_CMPBUF2 BPWM CMPDAT2 Buffer 0x324 read-write n 0x0 0x0 BPWM_CMPBUF3 BPWM_CMPBUF3 BPWM CMPDAT3 Buffer 0x328 read-write n 0x0 0x0 BPWM_CMPBUF4 BPWM_CMPBUF4 BPWM CMPDAT4 Buffer 0x32C read-write n 0x0 0x0 BPWM_CMPBUF5 BPWM_CMPBUF5 BPWM CMPDAT5 Buffer 0x330 read-write n 0x0 0x0 BPWM_CMPDAT0 BPWM_CMPDAT0 BPWM Comparator Register 0 0x50 read-write n 0x0 0x0 CMP BPWM Comparator Register\nCMP use to compare with CNT to generate BPWM waveform, interrupt and trigger ADC.\nIn independent mode, BPWM_CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point. 0 16 read-write BPWM_CMPDAT1 BPWM_CMPDAT1 BPWM Comparator Register 1 0x54 read-write n 0x0 0x0 BPWM_CMPDAT2 BPWM_CMPDAT2 BPWM Comparator Register 2 0x58 read-write n 0x0 0x0 BPWM_CMPDAT3 BPWM_CMPDAT3 BPWM Comparator Register 3 0x5C read-write n 0x0 0x0 BPWM_CMPDAT4 BPWM_CMPDAT4 BPWM Comparator Register 4 0x60 read-write n 0x0 0x0 BPWM_CMPDAT5 BPWM_CMPDAT5 BPWM Comparator Register 5 0x64 read-write n 0x0 0x0 BPWM_CNT BPWM_CNT BPWM Counter Register 0 0x90 read-only n 0x0 0x0 CNT BPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter. 0 16 read-only DIRF BPWM Direction Indicator Flag (Read Only)\n 16 1 read-only 0 Counter is Down count #0 1 Counter is UP count #1 BPWM_CNTCLR BPWM_CNTCLR BPWM Clear Counter Register 0x24 read-write n 0x0 0x0 CNTCLR0 Clear BPWM Counter Control Bit 0\nIt is automatically cleared by hardware.\n 0 1 read-write 0 No effect #0 1 Clear 16-bit BPWM counter to 0000H #1 BPWM_CNTEN BPWM_CNTEN BPWM Counter Enable Register 0x20 read-write n 0x0 0x0 CNTEN0 BPWM Counter Enable 0\n 0 1 read-write 0 BPWM Counter and clock prescaler Stop Running #0 1 BPWM Counter and clock prescaler Start Running #1 BPWM_CTL0 BPWM_CTL0 BPWM Control Register 0 0x0 read-write n 0x0 0x0 CTRLDn Center Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 0 1 read-write 0 Center Lodaing mode is disable for corresponding BPWM channel n #0 1 Center Lodaing mode is enable for corresponding BPWM channel n #1 DBGHALT ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 30 1 read-write 0 ICE debug mode counter halt disable #0 1 ICE debug mode counter halt enable #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable (Write Protect)\nBPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects BPWM output #0 1 ICE debug mode acknowledgement disabled #1 IMMLDENn Immediately Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled, CTRLDn will be invalid. 16 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 BPWM_CTL1 BPWM_CTL1 BPWM Control Register 1 0x4 read-write n 0x0 0x0 CNTTYPE0 BPWM Counter Behavior Type 0\n 0 2 read-write 0 Up counter type (supports in capture mode) #00 1 Down count type (supports in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 BPWM_FCAPDAT0 BPWM_FCAPDAT0 BPWM Falling Capture Data Register 0 0x210 read-only n 0x0 0x0 FCAPDAT BPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened, the BPWM counter value will be saved in this register. 0 16 read-only BPWM_FCAPDAT1 BPWM_FCAPDAT1 BPWM Falling Capture Data Register 1 0x218 read-write n 0x0 0x0 BPWM_FCAPDAT2 BPWM_FCAPDAT2 BPWM Falling Capture Data Register 2 0x220 read-write n 0x0 0x0 BPWM_FCAPDAT3 BPWM_FCAPDAT3 BPWM Falling Capture Data Register 3 0x228 read-write n 0x0 0x0 BPWM_FCAPDAT4 BPWM_FCAPDAT4 BPWM Falling Capture Data Register 4 0x230 read-write n 0x0 0x0 BPWM_FCAPDAT5 BPWM_FCAPDAT5 BPWM Falling Capture Data Register 5 0x238 read-write n 0x0 0x0 BPWM_INTEN BPWM_INTEN BPWM Interrupt Enable Register 0xE0 read-write n 0x0 0x0 CMPDIENn BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.\n 24 6 read-write 0 Compare down count interrupt Disabled 0 1 Compare down count interrupt Enabled 1 CMPUIENn BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.\n. 16 6 read-write 0 Compare up count interrupt Disabled 0 1 Compare up count interrupt Enabled 1 PIEN0 BPWM Period Point Interrupt Enable 0\nNote: When up-down counter type period point means center point. 8 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 ZIEN0 BPWM Zero Point Interrupt Enable 0\n 0 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 BPWM_INTSTS0 BPWM_INTSTS0 BPWM Interrupt Flag Register 0 0xE8 read-write n 0x0 0x0 CMPDIFn BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 24 6 read-write CMPUIFn BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 16 6 read-write PIF0 BPWM Period Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to zero. 8 1 read-write ZIF0 BPWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches zero, software can write 1 to clear this bit to zero. 0 1 read-write BPWM_MSK BPWM_MSK BPWM Mask Data Register 0xBC read-write n 0x0 0x0 MSKDATn BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 Output logic low to BPWMn 0 1 Output logic high to BPWMn 1 BPWM_MSKEN BPWM_MSKEN BPWM Mask Enable Register 0xB8 read-write n 0x0 0x0 MSKENn BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. \n 0 6 read-write 0 BPWM output signal is non-masked 0 1 BPWM output signal is masked and output MSKDATn data 1 BPWM_PBUF BPWM_PBUF BPWM PERIOD Buffer 0x304 read-only n 0x0 0x0 PBUF BPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register. 0 16 read-only BPWM_PERIOD BPWM_PERIOD BPWM Period Register 0x30 read-write n 0x0 0x0 PERIOD BPWM Period Register\nUp-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0.\nDown-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD.\n 0 16 read-write BPWM_POEN BPWM_POEN BPWM Output Enable Register 0xD8 read-write n 0x0 0x0 POENn BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 BPWM pin at tri-state 0 1 BPWM pin in output mode 1 BPWM_POLCTL BPWM_POLCTL BPWM Pin Polar Inverse Register 0xD4 read-write n 0x0 0x0 PINVn BPWM PIN Polar Inverse Control Bits\nThe register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n.\n 0 6 read-write 0 BPWM output polar inverse Disabled 0 1 BPWM output polar inverse Enabled 1 BPWM_RCAPDAT0 BPWM_RCAPDAT0 BPWM Rising Capture Data Register 0 0x20C read-only n 0x0 0x0 RCAPDAT BPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened, the BPWM counter value will be saved in this register. 0 16 read-only BPWM_RCAPDAT1 BPWM_RCAPDAT1 BPWM Rising Capture Data Register 1 0x214 read-write n 0x0 0x0 BPWM_RCAPDAT2 BPWM_RCAPDAT2 BPWM Rising Capture Data Register 2 0x21C read-write n 0x0 0x0 BPWM_RCAPDAT3 BPWM_RCAPDAT3 BPWM Rising Capture Data Register 3 0x224 read-write n 0x0 0x0 BPWM_RCAPDAT4 BPWM_RCAPDAT4 BPWM Rising Capture Data Register 4 0x22C read-write n 0x0 0x0 BPWM_RCAPDAT5 BPWM_RCAPDAT5 BPWM Rising Capture Data Register 5 0x234 read-write n 0x0 0x0 BPWM_SSCTL BPWM_SSCTL BPWM Synchronous Start Control Register 0x110 read-write n 0x0 0x0 SSEN0 BPWM Synchronous Start Function Enable 0\nWhen synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN). \n 0 1 read-write 0 BPWM synchronous start function Disabled #0 1 BPWM synchronous start function Enabled #1 SSRC BPWM Synchronous Start Source Select\n 8 2 read-write 0 Synchronous start source come from BPWM0 #00 1 Synchronous start source come from BPWM1 #01 2 Synchronous start source come from PWM0 #10 3 Synchronous start source come from PWM1 #11 BPWM_SSTRG BPWM_SSTRG BPWM Synchronous Start Trigger Register 0x114 write-only n 0x0 0x0 CNTSEN BPWM Counter Synchronous Start Enable (Write Only)\nWriting this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated BPWM channel counter synchronous start function is enabled. 0 1 write-only BPWM_STATUS BPWM_STATUS BPWM Status Register 0x120 read-write n 0x0 0x0 ADCTRGn ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\n 16 6 read-write 0 Indicates no ADC start of conversion trigger event has occurred 0 1 Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit 1 CNTMAX0 Time-base Counter 0 Equal to 0xFFFF Latched Status\n 0 1 read-write 0 Indicates the time-base counter never reached its maximum value 0xFFFF #0 1 Indicates the time-base counter reached its maximum value, software can write 1 to clear this bit #1 BPWM_WGCTL0 BPWM_WGCTL0 BPWM Generation Register 0 0xB0 read-write n 0x0 0x0 PRDPCTLn BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIODn+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type. 16 12 read-write 0 Do nothing 00 1 BPWM period (center) point output Low 01 10 BPWM period (center) point output High 10 11 BPWM period (center) point output Toggle 11 ZPCTLn BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to zero. 0 12 read-write 0 Do nothing 00 1 BPWM zero point output Low 01 10 BPWM zero point output High 10 11 BPWM zero point output Toggle 11 BPWM_WGCTL1 BPWM_WGCTL1 BPWM Generation Register 1 0xB4 read-write n 0x0 0x0 CMPDCTLn BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT. 16 12 read-write 0 Do nothing 00 1 BPWM compare down point output Low 01 10 BPWM compare down point output High 10 11 BPWM compare down point output Toggle 11 CMPUCTLn BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT. 0 12 read-write 0 Do nothing 00 1 BPWM compare up point output Low 01 10 BPWM compare up point output High 10 11 BPWM compare up point output Toggle 11 CLK CLK Register Map CLK 0x0 0x0 0x28 registers n 0x30 0x8 registers n 0x70 0x10 registers n AHBCLK CLK_AHBCLK AHB Devices Clock Enable Control Register 0x4 read-write n 0x0 0x0 GPIOACKEN General Purpose I/O PA Group Clock Enable Bit\n 16 1 read-write 0 GPIO PA group clock Disabled #0 1 GPIO PA group clock Enabled #1 GPIOBCKEN General Purpose I/O PB Group Clock Enable Bit\n 17 1 read-write 0 GPIO PB group clock Disabled #0 1 GPIO PB group clock Enabled #1 GPIOCCKEN General Purpose I/O PC Group Clock Enable Bit\n 18 1 read-write 0 GPIO PC group clock Disabled #0 1 GPIO PC group clock Enabled #1 GPIODCKEN General Purpose I/O PD Group Clock Enable Bit\n 19 1 read-write 0 GPIO PD group clock Disabled #0 1 GPIO PD group clock Enabled #1 GPIOECKEN General Purpose I/O PE Group Clock Enable Bit\n 20 1 read-write 0 GPIO PE group clock Disabled #0 1 GPIO PE group clock Enabled #1 GPIOFCKEN General Purpose I/O PF Group Clock Enable Bit\n 21 1 read-write 0 GPIO PF group clock Disabled #0 1 GPIO PF group clock Enabled #1 ISPCKEN Flash ISP Controller Clock Enable Bit\n 2 1 read-write 0 Flash ISP peripheral clock Disabled #0 1 Flash ISP peripheral clock Enabled #1 PDMACKEN PDMA Controller Clock Enable Bit\n 1 1 read-write 0 PDMA peripheral clock Disabled #0 1 PDMA peripheral clock Enabled #1 APBCLK0 CLK_APBCLK0 APB Devices Clock Enable Control Register 0 0x8 read-write n 0x0 0x0 ADCCKEN Analog-digital-converter (ADC) Clock Enable Bit\n 28 1 read-write 0 ADC clock Disabled #0 1 ADC clock Enabled #1 BPWM0CKEN BPWM0 Clock Enable Bit\n 20 1 read-write 0 BPWM0 clock Disabled #0 1 BPWM0 clock Enabled #1 BPWM1CKEN BPWM1 Clock Enable Bit\n 21 1 read-write 0 BPWM1 clock Disabled #0 1 BPWM1 clock Enabled #1 CLKOCKEN CLKO Clock Enable Bit\n 6 1 read-write 0 CLKO Clock Disabled #0 1 CLKO Clock Enabled #1 I2C0CKEN I2C0 Clock Enable Bit\n 8 1 read-write 0 I2C0 Clock Disabled #0 1 I2C0 Clock Enabled #1 I2C1CKEN I2C1 Clock Enable Bit\n 9 1 read-write 0 I2C1 Clock Disabled #0 1 I2C1 Clock Enabled #1 PWM0CKEN PWM0 Clock Enable Bit\n 22 1 read-write 0 PWM0 clock Disabled #0 1 PWM0 clock Enabled #1 PWM1CKEN PWM1 Clock Enable Bit\n 23 1 read-write 0 PWM1 clock Disabled #0 1 PWM1 clock Enabled #1 SPI0CKEN SPI0 Clock Enable Bit\n 12 1 read-write 0 SPI0 Clock Disabled #0 1 SPI0 Clock Enabled #1 TMR0CKEN Timer0 Clock Enable Bit\n 2 1 read-write 0 Timer0 Clock Disabled #0 1 Timer0 Clock Enabled #1 TMR1CKEN Timer1 Clock Enable Bit\n 3 1 read-write 0 Timer1 Clock Disabled #0 1 Timer1 Clock Enabled #1 TMR2CKEN Timer2 Clock Enable Bit\n 4 1 read-write 0 Timer2 Clock Disabled #0 1 Timer2 Clock Enabled #1 TMR3CKEN Timer3 Clock Enable Bit\n 5 1 read-write 0 Timer3 Clock Disabled #0 1 Timer3 Clock Enabled #1 UART0CKEN UART0 Clock Enable Bit\n 16 1 read-write 0 UART0 clock Disabled #0 1 UART0 clock Enabled #1 USBDCKEN USB Device Clock Enable Bit\n 27 1 read-write 0 USB Device clock Disabled #0 1 USB Device clock Enabled #1 WDTCKEN Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 Watchdog Timer Clock Disabled #0 1 Watchdog Timer Clock Enabled #1 APBCLK1 CLK_APBCLK1 APB Devices Clock Enable Control Register 1 0x30 read-write n 0x0 0x0 USCI0CKEN USCI0 Clock Enable Bit\n 8 1 read-write 0 USCI0 clock Disabled #0 1 USCI0 clock Enabled #1 CDLOWB CLK_CDLOWB Clock Frequency Detector Low Boundary Register 0x7C read-write n 0x0 0x0 LOWERBD HXT Clock Frequency Detector Low Boundary\nThe bits define the low value of frequency monitor window.\nWhen HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will set to 1. 0 10 read-write CDUPB CLK_CDUPB Clock Frequency Detector Upper Boundary Register 0x78 read-write n 0x0 0x0 UPERBD HXT Clock Frequency Detector Upper Boundary\nThe bits define the high value of frequency monitor window.\nWhen HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1. 0 10 read-write CLKDCTL CLK_CLKDCTL Clock Fail Detector Control Register 0x70 read-write n 0x0 0x0 HXTFDEN HXT Clock Fail Detector Enable Bit\n 4 1 read-write 0 4~24 MHz external high speed crystal oscillator (HXT) clock Fail detector Disabled #0 1 4~24 MHz external high speed crystal oscillator (HXT) clock Fail detector Enabled #1 HXTFIEN HXT Clock Fail Interrupt Enable Bit\n 5 1 read-write 0 4~24 MHz external high speed crystal oscillator (HXT)clock Fail interrupt Disabled #0 1 4~24 MHz external high speed crystal oscillator (HXT)clock Fail interrupt Enabled #1 HXTFQDEN HXT Clock Frequency Monitor Enable Bit\n 16 1 read-write 0 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Disabled #0 1 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Enabled #1 HXTFQIEN HXT Clock Frequency Monitor Interrupt Enable Bit\n 17 1 read-write 0 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Disabled #0 1 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Enabled #1 LXTFDEN LXT Clock Fail Detector Enable Bit\n 12 1 read-write 0 32.768 kHz external low speed crystal oscillator (LXT) clock Fail detector Disabled #0 1 32.768 kHz external low speed crystal oscillator (LXT) clock Fail detector Enabled #1 LXTFIEN LXT Clock Fail Interrupt Enable Bit\n 13 1 read-write 0 32.768 kHz external low speed crystal oscillator (LXT) clock Fail interrupt Disabled #0 1 32.768 kHz external low speed crystal oscillator (LXT) clock Fail interrupt Enabled #1 CLKDIV0 CLK_CLKDIV0 Clock Divider Number Register 0 0x18 read-write n 0x0 0x0 ADCDIV ADC Clock Divide Number From EADC Clock Source\n 16 8 read-write HCLKDIV HCLK Clock Divide Number From HCLK Clock Source\n 0 4 read-write UARTDIV UART Clock Divide Number From UART Clock Source\n 8 4 read-write USBDIV USB Clock Divide Number From PLL Clock\n 4 4 read-write CLKDSTS CLK_CLKDSTS Clock Fail Detector Status Register 0x74 read-write n 0x0 0x0 HXTFIF HXT Clock Fail Interrupt Flag\nNote: Write 1 to clear the bit to 0. 0 1 read-write 0 4~24 MHz external high speed crystal oscillator (HXT) clock normal #0 1 4~24 MHz external high speed crystal oscillator (HXT) clock stop #1 HXTFQIF HXT Clock Frequency Monitor Interrupt Flag\nNote: Write 1 to clear the bit to 0. 8 1 read-write 0 4~24 MHz external high speed crystal oscillator (HXT) clock normal #0 1 4~24 MHz external high speed crystal oscillator (HXT) clock frequency abnormal #1 LXTFIF LXT Clock Fail Interrupt Flag\nNote: Write 1 to clear the bit to 0. 1 1 read-write 0 32.768 kHz external low speed crystal oscillator (LXT) clock normal #0 1 32.768 kHz external low speed crystal oscillator (LXT) stop #1 CLKOCTL CLK_CLKOCTL Clock Output Control Register 0x24 read-write n 0x0 0x0 CLKOEN Clock Output Enable Bit\n 4 1 read-write 0 Clock Output function Disabled #0 1 Clock Output function Enabled #1 DIV1EN Clock Output Divide One Enable Bit\n 5 1 read-write 0 Clock Output will output clock with source frequency divided by FREQSEL #0 1 Clock Output will output clock with source frequency #1 FREQSEL Clock Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL[3:0]. 0 4 read-write CLKSEL0 CLK_CLKSEL0 Clock Source Select Control Register 0 0x10 read-write n 0x0 0x0 HCLKSEL HCLK Clock Source Selection (Write Protect)\nBefore clock switching, the related clock sources (both pre-select and new-select) must be turned on.\nThe default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 0 3 read-write 0 Clock source from HXT clock #000 1 Clock source from LXT clock #001 2 Clock source from PLL clock #010 3 Clock source from LIRC clock #011 4 Clock source from HIRC clock #100 5 Clock source from PLL/2 #101 7 Clock source from HIRC/2(24 MHz) #111 PCLK0SEL PCLK0 Clock Source Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write 0 APB0 BUS clock source from HCLK clock #0 1 APB0 BUS clock source from HCLK/2 #1 PCLK1SEL PCLK1 Clock Source Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 7 1 read-write 0 APB1 BUS clock source from HCLK clock #0 1 APB1 BUS clock source from HCLK/2 #1 STCLKSEL Cortex-M0 SysTick Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 3 3 read-write 0 Clock source from HXT clock #000 1 Clock source from LXT clock #001 2 Clock source from HXT/2 #010 3 Clock source from HCLK/2 #011 7 Clock source from HIRC/4 (12 MHz) #111 CLKSEL1 CLK_CLKSEL1 Clock Source Select Control Register 1 0x14 read-write n 0x0 0x0 ADCSEL ADC Peripheral Clock Source Selection\n 2 2 read-write 0 Clock source is from HXT clock #00 1 Clock source is from PLL clock #01 2 Clock source is from PCLK0 clock #10 3 Clock source is from HIRC/2 (24 MHz) #11 BPWM0SEL BPWM0 Clock Source Selection\nThe peripheral clock source of BPWM0 is defined by BPWM0SEL. \n 28 1 read-write 0 Clock source from PLL clock #0 1 Clock source from PCLK0 clock #1 BPWM1SEL BPWM1 Clock Source Selection\nThe peripheral clock source of BPWM1 is defined by BPWM1SEL. \n 29 1 read-write 0 Clock source from PLL clock #0 1 Clock source from PCLK1 clock #1 PWM0SEL PWM0 Clock Source Selection\nThe peripheral clock source of PWM1 is defined by PWM0SEL. \n 30 1 read-write 0 Clock source from PLL clock #0 1 Clock source from PCLK0 clock #1 PWM1SEL PWM1 Clock Source Selection\nThe peripheral clock source of PWM1 is defined by PWM1SEL. \n 31 1 read-write 0 Clock source from PLL clock #0 1 Clock source from PCLK1 clock #1 TMR0SEL TIMER0 Clock Source Selection\n 8 3 read-write 0 Clock source from HXT clock #000 1 Clock source from LXT clock #001 2 Clock source from PCLK0 clock #010 3 Clock source from external clock T0 pin #011 5 Clock source from LIRC clock #101 7 Clock source from HIRC/2 (24 MHz) #111 TMR1SEL TIMER1 Clock Source Selection\n 12 3 read-write 0 Clock source from HXT #000 1 Clock source from LXT #001 2 Clock source from PCLK0 #010 3 Clock source from external clock T1 pin #011 5 Clock source from LIRC #101 7 Clock source from HIRC/2 (24 MHz) #111 TMR2SEL TIMER2 Clock Source Selection\n 16 3 read-write 0 Clock source from HXT clock #000 1 Clock source from LXT clock #001 2 Clock source from PCLK1 clock #010 3 Clock source from external clock T2 pin #011 5 Clock source from LIRC clock #101 7 Clock source from HIRC/2 (24 MHz) #111 TMR3SEL TIMER3 Clock Source Selection\n 20 3 read-write 0 Clock source from HXT clock #000 1 Clock source from LXT clock #001 2 Clock source from PCLK1 clock #010 3 Clock source from external clock T3 pin #011 5 Clock source from LIRC clock #101 7 Clock source from HIRC/2 (24 MHz) #111 UARTSEL UART Clock Source Selection\n 24 2 read-write 0 Clock source from HXT clock #00 1 Clock source from PLL clock #01 2 Clock source from LXT clock #10 3 Clock source from HIRC/2 clock #11 WDTSEL Watchdog Timer Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 0 2 read-write 0 Reserved #00 1 Clock source from LXT clock #01 2 Clock source from HCLK/2048 #10 3 Clock source from LIRC clock #11 CLKSEL2 CLK_CLKSEL2 Clock Source Select Control Register 2 0x1C read-write n 0x0 0x0 CLKOSEL Clock Divider Clock Source Selection\n 2 3 read-write 0 Clock source from HXT clock #000 1 Clock source from LXT clock #001 2 Clock source from HCLK clock #010 3 Clock source from HIRC/2 clock #011 5 Clock source from HIRC clock #101 7 Clock source from SOF (USB Start Of Frame) event. (not 50% duty cycle) #111 SPI0SEL SPI0 Clock Source Selection\n 24 2 read-write 0 Clock source from HXT clock #00 1 Clock source from PLL clock #01 2 Clock source from PCLK0 clock #10 3 Clock source from HIRC clock #11 WWDTSEL Window Watchdog Timer Clock Source Selection\n 16 2 read-write 2 Clock source from HCLK/2048 clock #10 3 Clock source from LIRC clock #11 CLKSEL3 CLK_CLKSEL3 Clock Source Select Control Register 3 0x34 read-write n 0x0 0x0 USBDSEL USBD Clock Source Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 8 1 read-write 0 Clock source from HIRC #0 1 Clock source from PLL clock #1 PLLCTL CLK_PLLCTL PLL Control Register 0x20 read-write n 0x0 0x0 BP PLL Bypass Control\n 17 1 read-write 0 PLL is in normal mode (default) #0 1 PLL clock output is same as PLL input clock FIN #1 FBDIV PLL Feedback Divider Control\nRefer to the formulas below the table. 0 9 read-write INDIV PLL Input Divider Control\nRefer to the formulas below the table. 9 5 read-write OE PLL OE (FOUT Enable) Pin Control\n 18 1 read-write 0 PLL FOUT Enabled #0 1 PLL FOUT is fixed low #1 OUTDIV PLL Output Divider Control\nRefer to the formulas below the table. 14 2 read-write PD Power-down Mode\nIf set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.\n 16 1 read-write 0 PLL is in normal mode #0 1 PLL is in Power-down mode (default) #1 PLLSRC PLL Source Clock Selection\n 19 1 read-write 0 PLL source clock from external 4~24 MHz high-speed crystal (HXT) #0 1 PLL source clock from internal 24 MHz high-speed oscillator (HIRC/2) #1 STBSEL PLL Stable Counter Selection\n 23 1 read-write 0 PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12MHz) #0 1 PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12MHz) #1 PWRCTL CLK_PWRCTL System Power-down Control Register 0x0 read-write n 0x0 0x0 HIRCEN HIRC Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 2 1 read-write 0 48 MHz internal high speed RC oscillator (HIRC) Disabled #0 1 48 MHz internal high speed RC oscillator (HIRC) Enabled #1 HXTGAIN HXT Gain Control Bit (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nGain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled, crystal will consume more power than gain control off. \nNote 1: These bits are write protected. Refer to the SYS_REGLCTL register.\nNote 2: These bits are over-written by CFGXT1 (CONFIG0[18:17]) after reset. 10 2 read-write 0 HXT frequency is lower than from 8 MHz #00 1 HXT frequency is from 8 MHz to 12 MHz #01 2 HXT frequency is from 12 MHz to 16 MHz #10 3 HXT frequency is higher than 16 MHz #11 LIRCEN LIRC Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 3 1 read-write 0 10 kHz internal low speed RC oscillator (LIRC) Disabled #0 1 10 kHz internal low speed RC oscillator (LIRC) Enabled #1 PDEN System Power-down Enable (Write Protect)\nWhen this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.\nWhen chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down.\nIn Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode.\nIn Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 7 1 read-write 0 Chip operating normally or chip in idle mode because of WFI command #0 1 Chip enters Power-down mode instant or wait CPU sleep command WFI #1 PDWKDLY Enable the Wake-up Delay Counter (Write Protect)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at 4~24 MHz external high speed crystal oscillator (HXT), and 512 clock cycles(selected by HIRCSTBS) when chip work at 48 MHz internal high speed RC oscillator (HIRC).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 Clock cycles delay Disabled #0 1 Clock cycles delay Enabled #1 PDWKIEN Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\nNote1: The interrupt will occur when both PDWKIF and PDWKIEN are high.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register. 5 1 read-write 0 Power-down mode wake-up interrupt Disabled #0 1 Power-down mode wake-up interrupt Enabled #1 PDWKIF Power-down Mode Wake-up Interrupt Status\nSet by "Power-down wake-up event", it indicates that resume from Power-down mode" \nThe flag is set if the EINT0~5, GPIO, USBD, UART0, WDT, BOD, TMR0~3 or I2C0~1 wake-up occurred.\nNote1: Write 1 to clear the bit to 0.\nNote2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. 6 1 read-write XTLEN External HXT or LXT Crystal Oscillator Enable Bit (Write Protect)\nThe default clock source is from HIRC. These two bits are default set to "00" and the PF.0 and PF.1 pins are GPIO.\nNote 1: These bits are write protected. Refer to the SYS_REGLCTL register.\nNote 2: These bits are over-written by CFOSC (CONFIG0[26]) after reset. 0 2 read-write 0 HXT LXT Disabled (default) #00 1 HXT Enabled #01 2 LXT Enabled #10 3 Reserved #11 STATUS CLK_STATUS Clock Status Monitor Register 0xC read-only n 0x0 0x0 CLKSFAIL Clock Switching Fail Flag (Read Only) \nThis bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nNote 1: Clock switch will finish automatically when target clcok is stable even if this bit already set to 1. 7 1 read-only 0 Clock switching success #0 1 Clock switching failure #1 HIRCSTB HIRC Clock Source Stable Flag (Read Only)\n 4 1 read-only 0 48 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled #0 1 48 MHz internal high speed RC oscillator (HIRC) clock is stabe and enabled #1 HXTSTB HXT Clock Source Stable Flag (Read Only)\n 0 1 read-only 0 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled #0 1 4~24 MHz external high speed crystal oscillator (HXT)clock is stable and enabled #1 LIRCSTB LIRC Clock Source Stable Flag (Read Only)\n 3 1 read-only 0 10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled #0 1 10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled #1 LXTSTB LXT Clock Source Stable Flag (Read Only)\n 1 1 read-only 0 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled #0 1 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled #1 PLLSTB Internal PLL Clock Source Stable Flag (Read Only)\n 2 1 read-only 0 Internal PLL clock is not stable or disabled #0 1 Internal PLL clock is stable and enabled #1 FMC FMC Register Map FMC 0x0 0x0 0x1C registers n 0x40 0x4 registers n DFBA FMC_DFBA Data Flash Base Address 0x14 read-only n 0x0 0x0 DFBA Data Flash Base Address\nThis register indicates Data Flash start address. It is a read only register.\nThe Data Flash is shared with APROM. the content of this register is loaded from CONFIG1\n 0 32 read-only FTCTL FMC_FTCTL Flash Access Time Control Register 0x18 read-write n 0x0 0x0 FOM Frequency Optimization Mode (Write Protect)\nThe NuMicro N121/125 series supports adjustable flash access timing to optimize the flash access cycles in different working frequency.\nNote 1: x denotes the bit is don't care.\nNote 2: These bits are write protected. Refer to the SYS_REGLCTL register. 4 3 read-write 1 Frequency 24MHz #001 ISPADDR FMC_ISPADDR ISP Address Register 0x4 read-write n 0x0 0x0 ISPADDR ISP Address\nThe NUC121/125 series is equipped with embedded flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. and ISPADDR[8:0] must be kept all 0 for Vector Page Re-map Command\nFor CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 512 bytes alignment is necessary for checksum calculation. 0 32 read-write ISPCMD FMC_ISPCMD ISP Command Register 0xC read-write n 0x0 0x0 CMD ISP CMD\nISP command table is shown below:\nThe other commands are invalid. 0 7 read-write 0 FLASH Read 0x00 4 Read Unique ID 0x04 11 Read Company ID 0x0b 12 Read Device ID 0x0c 13 Read CRC32 Checksum 0x0d 33 FLASH 32-bit Program 0x21 34 FLASH Page Erase 0x22 45 Run CRC32 Checksum Calculation 0x2d 46 Vector Remap 0x2e ISPCTL FMC_ISPCTL ISP Control Register 0x0 read-write n 0x0 0x0 APUEN APROM Update Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 3 1 read-write 0 APROM cannot be updated when the chip runs in APROM #0 1 APROM can be updated when the chip runs in APROM #1 BS Boot Select (Write Protect)\nSet/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 Booting from APROM #0 1 Booting from LDROM #1 CFGUEN CONFIG Update Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 CONFIG cannot be updated #0 1 CONFIG can be updated #1 ISPEN ISP Enable (Write Protect)\nISP function enable bit. Set this bit to enable ISP function.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 ISP function Disabled #0 1 ISP function Enabled #1 ISPFF ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\nThis bit needs to be cleared by writing 1 to it.\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) SPROM is erased/programmed if SPUEN is set to 0\n(5) SPROM is programmed at SPROM secured mode.\n(6) Page Erase command at LOCK mode with ICE connection\n(7) Erase or Program command at brown-out detected\n(8) Destination address is illegal, such as over an available range.\n(9) Invalid ISP commands\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write LDUEN LDROM Update Enable (Write Protect)\nLDROM update enable bit.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 5 1 read-write 0 LDROM cannot be updated #0 1 LDROM can be updated #1 SPUEN SPROM Update Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 2 1 read-write 0 SPROM cannot be updated #0 1 SPROM can be updated #1 ISPDAT FMC_ISPDAT ISP Data Register 0x8 read-write n 0x0 0x0 ISPDAT ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation.\n 0 32 read-write ISPSTS FMC_ISPSTS ISP Status Register 0x40 read-write n 0x0 0x0 CBS Boot Selection of CONFIG (Read Only)\nThis bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened.\n 1 2 read-only 0 LDROM with IAP mode #00 1 LDROM without IAP mode #01 2 APROM with IAP mode #10 3 APROM without IAP mode #11 ISPBUSY ISP BUSY (Read Only)\n 0 1 read-only 0 ISP operation is finished #0 1 ISP operation is busy #1 ISPFF ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) SPROM is erased/programmed if SPUEN is set to 0\n(5) SPROM is programmed at SPROM secured mode.\n(6) Page Erase command at LOCK mode with ICE connection\n(7) Erase or Program command at brown-out detected\n(8) Destination address is illegal, such as over an available range.\n(9) Invalid ISP commands\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write SCODE Security Code Active Flag\nThis bit is set to 1 by hardware when detecting SPROM secured code is active at flash initialization, or software writes 1 to this bit to make secured code active; this bit is only cleared by SPROM page erase operation.\n 31 1 read-write 0 SPROM secured code is inactive #0 1 SPROM secured code is active #1 VECMAP Vector Page Mapping Address (Read Only)\nAll access to 0x0000_0000~0x0000_01FF is remapped to the flash memory or SRAM address {VECMAP[20:0], 9'b0} ~ {VECMAP[20:0], 9'h1FF}, except SPROM.\nVECMAP [18:12] should be 0.\nNote: Vector mapping is page alignment (512 byte), and thus VECMAP starts from bit10. 9 21 read-only ISPTRG FMC_ISPTRG ISP Trigger Control Register 0x10 read-write n 0x0 0x0 ISPGO ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 ISP operation is finished #0 1 ISP is progressed #1 GPIO GPIO Register Map GPIO 0x0 0x0 0x2C registers n 0x100 0x2C registers n 0x140 0x2C registers n 0x180 0x4 registers n 0x200 0x10C registers n 0x340 0x20 registers n 0x40 0x2C registers n 0x80 0x30 registers n 0xC0 0x2C registers n DBCTL GPIO_DBCTL Interrupt De-bounce Control 0x180 read-write n 0x0 0x0 DBCLKSEL De-bounce Sampling Cycle Selection\n 0 4 read-write 0 Sample interrupt input once per 1 clocks #0000 1 Sample interrupt input once per 2 clocks #0001 2 Sample interrupt input once per 4 clocks #0010 3 Sample interrupt input once per 8 clocks #0011 4 Sample interrupt input once per 16 clocks #0100 5 Sample interrupt input once per 32 clocks #0101 6 Sample interrupt input once per 64 clocks #0110 7 Sample interrupt input once per 128 clocks #0111 8 Sample interrupt input once per 256 clocks #1000 9 Sample interrupt input once per 2*256 clocks #1001 10 Sample interrupt input once per 4*256 clocks #1010 11 Sample interrupt input once per 8*256 clocks #1011 12 Sample interrupt input once per 16*256 clocks #1100 13 Sample interrupt input once per 32*256 clocks #1101 14 Sample interrupt input once per 64*256 clocks #1110 15 Sample interrupt input once per 128*256 clocks #1111 DBCLKSRC De-bounce Counter Clock Source Selection\n 4 1 read-write 0 De-bounce counter clock source is the HCLK #0 1 De-bounce counter clock source is the internal 10 kHz internal low speed oscillator #1 ICLKON Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern. 5 1 read-write 0 Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1 #0 1 All I/O pins edge detection circuit is always active after reset #1 PA0_PDIO PA0_PDIO GPIO PA.n Pin Data Input/Output 0x200 read-write n 0x0 0x0 PDIO GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 0 1 read-write 0 Corresponding GPIO pin set to low #0 1 Corresponding GPIO pin set to high #1 PA10_PDIO PA10_PDIO GPIO PA.n Pin Data Input/Output 0x228 read-write n 0x0 0x0 PA11_PDIO PA11_PDIO GPIO PA.n Pin Data Input/Output 0x22C read-write n 0x0 0x0 PA12_PDIO PA12_PDIO GPIO PA.n Pin Data Input/Output 0x230 read-write n 0x0 0x0 PA13_PDIO PA13_PDIO GPIO PA.n Pin Data Input/Output 0x234 read-write n 0x0 0x0 PA14_PDIO PA14_PDIO GPIO PA.n Pin Data Input/Output 0x238 read-write n 0x0 0x0 PA15_PDIO PA15_PDIO GPIO PA.n Pin Data Input/Output 0x23C read-write n 0x0 0x0 PA1_PDIO PA1_PDIO GPIO PA.n Pin Data Input/Output 0x204 read-write n 0x0 0x0 PA2_PDIO PA2_PDIO GPIO PA.n Pin Data Input/Output 0x208 read-write n 0x0 0x0 PA3_PDIO PA3_PDIO GPIO PA.n Pin Data Input/Output 0x20C read-write n 0x0 0x0 PA4_PDIO PA4_PDIO GPIO PA.n Pin Data Input/Output 0x210 read-write n 0x0 0x0 PA5_PDIO PA5_PDIO GPIO PA.n Pin Data Input/Output 0x214 read-write n 0x0 0x0 PA6_PDIO PA6_PDIO GPIO PA.n Pin Data Input/Output 0x218 read-write n 0x0 0x0 PA7_PDIO PA7_PDIO GPIO PA.n Pin Data Input/Output 0x21C read-write n 0x0 0x0 PA8_PDIO PA8_PDIO GPIO PA.n Pin Data Input/Output 0x220 read-write n 0x0 0x0 PA9_PDIO PA9_PDIO GPIO PA.n Pin Data Input/Output 0x224 read-write n 0x0 0x0 PA_DATMSK PA_DATMSK PA Data Output Write Mask 0xC read-write n 0x0 0x0 DATMSK0 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 0 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK1 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 1 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK10 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 10 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK11 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 11 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK12 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 12 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK13 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 13 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK14 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 14 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK15 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 15 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK2 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 2 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK3 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 3 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK4 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 4 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK5 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 5 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK6 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 6 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK7 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 7 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK8 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 8 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK9 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 9 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 PA_DBEN PA_DBEN PA De-bounce Enable Control 0x14 read-write n 0x0 0x0 DBEN0 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 0 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN1 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 1 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN10 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 10 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN11 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 11 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN12 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 12 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN13 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 13 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN14 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 14 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN15 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 15 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN2 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 2 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN3 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 3 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN4 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 4 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN5 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 5 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN6 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 6 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN7 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 7 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN8 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 8 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN9 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 9 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 PA_DINOFF PA_DINOFF PA Digital Input Path Disable Control 0x4 read-write n 0x0 0x0 DINOFF0 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. \nUser can disable GPIO digital input path by setting DINOFF (Px_DINOFF[n]) to avoid input current leakage. When GPIO digital input path is disabled, the digital input pin value PIN (PxPIN[n]) is tied to low. By the way, the GPIO digital input path is force disabled by hardware and DINOFF control is useless when I/O function configure as ADC/ACMP/ext. XTL..\n\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 16 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF1 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. \nUser can disable GPIO digital input path by setting DINOFF (Px_DINOFF[n]) to avoid input current leakage. When GPIO digital input path is disabled, the digital input pin value PIN (PxPIN[n]) is tied to low. By the way, the GPIO digital input path is force disabled by hardware and DINOFF control is useless when I/O function configure as ADC/ACMP/ext. XTL..\n\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 17 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF10 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. \nUser can disable GPIO digital input path by setting DINOFF (Px_DINOFF[n]) to avoid input current leakage. When GPIO digital input path is disabled, the digital input pin value PIN (PxPIN[n]) is tied to low. By the way, the GPIO digital input path is force disabled by hardware and DINOFF control is useless when I/O function configure as ADC/ACMP/ext. XTL..\n\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 26 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF11 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. \nUser can disable GPIO digital input path by setting DINOFF (Px_DINOFF[n]) to avoid input current leakage. When GPIO digital input path is disabled, the digital input pin value PIN (PxPIN[n]) is tied to low. By the way, the GPIO digital input path is force disabled by hardware and DINOFF control is useless when I/O function configure as ADC/ACMP/ext. XTL..\n\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 27 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF12 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. \nUser can disable GPIO digital input path by setting DINOFF (Px_DINOFF[n]) to avoid input current leakage. When GPIO digital input path is disabled, the digital input pin value PIN (PxPIN[n]) is tied to low. By the way, the GPIO digital input path is force disabled by hardware and DINOFF control is useless when I/O function configure as ADC/ACMP/ext. XTL..\n\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 28 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF13 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. \nUser can disable GPIO digital input path by setting DINOFF (Px_DINOFF[n]) to avoid input current leakage. When GPIO digital input path is disabled, the digital input pin value PIN (PxPIN[n]) is tied to low. By the way, the GPIO digital input path is force disabled by hardware and DINOFF control is useless when I/O function configure as ADC/ACMP/ext. XTL..\n\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 29 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF14 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. \nUser can disable GPIO digital input path by setting DINOFF (Px_DINOFF[n]) to avoid input current leakage. When GPIO digital input path is disabled, the digital input pin value PIN (PxPIN[n]) is tied to low. By the way, the GPIO digital input path is force disabled by hardware and DINOFF control is useless when I/O function configure as ADC/ACMP/ext. XTL..\n\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 30 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF15 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. \nUser can disable GPIO digital input path by setting DINOFF (Px_DINOFF[n]) to avoid input current leakage. When GPIO digital input path is disabled, the digital input pin value PIN (PxPIN[n]) is tied to low. By the way, the GPIO digital input path is force disabled by hardware and DINOFF control is useless when I/O function configure as ADC/ACMP/ext. XTL..\n\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 31 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF2 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. \nUser can disable GPIO digital input path by setting DINOFF (Px_DINOFF[n]) to avoid input current leakage. When GPIO digital input path is disabled, the digital input pin value PIN (PxPIN[n]) is tied to low. By the way, the GPIO digital input path is force disabled by hardware and DINOFF control is useless when I/O function configure as ADC/ACMP/ext. XTL..\n\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 18 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF3 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. \nUser can disable GPIO digital input path by setting DINOFF (Px_DINOFF[n]) to avoid input current leakage. When GPIO digital input path is disabled, the digital input pin value PIN (PxPIN[n]) is tied to low. By the way, the GPIO digital input path is force disabled by hardware and DINOFF control is useless when I/O function configure as ADC/ACMP/ext. XTL..\n\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 19 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF4 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. \nUser can disable GPIO digital input path by setting DINOFF (Px_DINOFF[n]) to avoid input current leakage. When GPIO digital input path is disabled, the digital input pin value PIN (PxPIN[n]) is tied to low. By the way, the GPIO digital input path is force disabled by hardware and DINOFF control is useless when I/O function configure as ADC/ACMP/ext. XTL..\n\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 20 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF5 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. \nUser can disable GPIO digital input path by setting DINOFF (Px_DINOFF[n]) to avoid input current leakage. When GPIO digital input path is disabled, the digital input pin value PIN (PxPIN[n]) is tied to low. By the way, the GPIO digital input path is force disabled by hardware and DINOFF control is useless when I/O function configure as ADC/ACMP/ext. XTL..\n\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 21 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF6 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. \nUser can disable GPIO digital input path by setting DINOFF (Px_DINOFF[n]) to avoid input current leakage. When GPIO digital input path is disabled, the digital input pin value PIN (PxPIN[n]) is tied to low. By the way, the GPIO digital input path is force disabled by hardware and DINOFF control is useless when I/O function configure as ADC/ACMP/ext. XTL..\n\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 22 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF7 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. \nUser can disable GPIO digital input path by setting DINOFF (Px_DINOFF[n]) to avoid input current leakage. When GPIO digital input path is disabled, the digital input pin value PIN (PxPIN[n]) is tied to low. By the way, the GPIO digital input path is force disabled by hardware and DINOFF control is useless when I/O function configure as ADC/ACMP/ext. XTL..\n\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 23 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF8 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. \nUser can disable GPIO digital input path by setting DINOFF (Px_DINOFF[n]) to avoid input current leakage. When GPIO digital input path is disabled, the digital input pin value PIN (PxPIN[n]) is tied to low. By the way, the GPIO digital input path is force disabled by hardware and DINOFF control is useless when I/O function configure as ADC/ACMP/ext. XTL..\n\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 24 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF9 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. \nUser can disable GPIO digital input path by setting DINOFF (Px_DINOFF[n]) to avoid input current leakage. When GPIO digital input path is disabled, the digital input pin value PIN (PxPIN[n]) is tied to low. By the way, the GPIO digital input path is force disabled by hardware and DINOFF control is useless when I/O function configure as ADC/ACMP/ext. XTL..\n\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 25 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 PA_DOUT PA_DOUT PA Data Output Value 0x8 read-write n 0x0 0x0 DOUT0 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 0 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT1 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 1 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT10 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 10 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT11 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 11 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT12 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 12 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT13 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 13 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT14 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 14 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT15 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 15 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT2 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 2 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT3 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 3 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT4 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 4 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT5 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 5 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT6 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 6 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT7 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 7 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT8 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 8 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT9 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 9 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 PA_INTEN PA_INTEN PA Interrupt Enable Control 0x1C read-write n 0x0 0x0 FLIEN0 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 0 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN1 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 1 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN10 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 10 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN11 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 11 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN12 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 12 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN13 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 13 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN14 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 14 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN15 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 15 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN2 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 2 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN3 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 3 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN4 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 4 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN5 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 5 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN6 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 6 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN7 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 7 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN8 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 8 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN9 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 9 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 RHIEN0 Port A-f Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 16 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN1 Port A-f Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 17 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN10 Port A-f Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 26 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN11 Port A-f Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 27 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN12 Port A-f Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 28 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN13 Port A-f Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 29 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN14 Port A-f Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 30 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN15 Port A-f Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 31 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN2 Port A-f Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 18 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN3 Port A-f Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 19 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN4 Port A-f Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 20 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN5 Port A-f Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 21 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN6 Port A-f Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 22 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN7 Port A-f Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 23 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN8 Port A-f Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 24 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN9 Port A-f Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 25 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 PA_INTSRC PA_INTSRC PA Interrupt Source Flag 0x20 read-write n 0x0 0x0 INTSRC0 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation :\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 0 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC1 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation :\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 1 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC10 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation :\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 10 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC11 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation :\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 11 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC12 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation :\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 12 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC13 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation :\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 13 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC14 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation :\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 14 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC15 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation :\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 15 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC2 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation :\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 2 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC3 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation :\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 3 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC4 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation :\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 4 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC5 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation :\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 5 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC6 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation :\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 6 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC7 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation :\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 7 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC8 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation :\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 8 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC9 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation :\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 9 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 PA_INTTYPE PA_INTTYPE PA Interrupt Mode Trigger Type Control 0x18 read-write n 0x0 0x0 TYPE0 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 0 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE1 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 1 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE10 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 10 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE11 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 11 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE12 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 12 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE13 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 13 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE14 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 14 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE15 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 15 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE2 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 2 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE3 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 3 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE4 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 4 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE5 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 5 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE6 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 6 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE7 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 7 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE8 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 8 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE9 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 9 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 PA_MODE PA_MODE PA I/O Mode Control 0x0 read-write n 0x0 0x0 MODE0 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 0 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE1 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 2 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE10 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 20 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE11 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 22 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE12 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 24 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE13 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 26 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE14 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 28 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE15 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 30 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE2 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 4 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE3 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 6 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE4 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 8 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE5 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 10 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE6 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 12 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE7 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 14 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE8 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 16 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE9 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 18 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 PA_PIN PA_PIN PA Pin Value 0x10 read-only n 0x0 0x0 PIN0 Port A-fPin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.\nNote1: \nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 0 1 read-only PIN1 Port A-fPin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.\nNote1: \nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 1 1 read-only PIN10 Port A-fPin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.\nNote1: \nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 10 1 read-only PIN11 Port A-fPin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.\nNote1: \nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 11 1 read-only PIN12 Port A-fPin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.\nNote1: \nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 12 1 read-only PIN13 Port A-fPin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.\nNote1: \nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 13 1 read-only PIN14 Port A-fPin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.\nNote1: \nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 14 1 read-only PIN15 Port A-fPin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.\nNote1: \nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 15 1 read-only PIN2 Port A-fPin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.\nNote1: \nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 2 1 read-only PIN3 Port A-fPin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.\nNote1: \nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 3 1 read-only PIN4 Port A-fPin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.\nNote1: \nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 4 1 read-only PIN5 Port A-fPin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.\nNote1: \nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 5 1 read-only PIN6 Port A-fPin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.\nNote1: \nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 6 1 read-only PIN7 Port A-fPin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.\nNote1: \nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 7 1 read-only PIN8 Port A-fPin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.\nNote1: \nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 8 1 read-only PIN9 Port A-fPin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.\nNote1: \nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 9 1 read-only PA_SLEWCTL PA_SLEWCTL PA High Slew Rate Control 0x28 read-write n 0x0 0x0 HSREN0 Port A-f Pin[n] High Slew Rate Control\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 0 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN1 Port A-f Pin[n] High Slew Rate Control\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 1 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN10 Port A-f Pin[n] High Slew Rate Control\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 10 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN11 Port A-f Pin[n] High Slew Rate Control\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 11 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN12 Port A-f Pin[n] High Slew Rate Control\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 12 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN13 Port A-f Pin[n] High Slew Rate Control\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 13 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN14 Port A-f Pin[n] High Slew Rate Control\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 14 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN15 Port A-f Pin[n] High Slew Rate Control\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 15 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN2 Port A-f Pin[n] High Slew Rate Control\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 2 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN3 Port A-f Pin[n] High Slew Rate Control\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 3 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN4 Port A-f Pin[n] High Slew Rate Control\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 4 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN5 Port A-f Pin[n] High Slew Rate Control\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 5 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN6 Port A-f Pin[n] High Slew Rate Control\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 6 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN7 Port A-f Pin[n] High Slew Rate Control\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 7 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN8 Port A-f Pin[n] High Slew Rate Control\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 8 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN9 Port A-f Pin[n] High Slew Rate Control\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 9 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 PA_SMTEN PA_SMTEN PA Input Schmitt Trigger Enable 0x24 read-write n 0x0 0x0 SMTEN0 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 0 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN1 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 1 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN10 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 10 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN11 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 11 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN12 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 12 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN13 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 13 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN14 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 14 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN15 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 15 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN2 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 2 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN3 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 3 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN4 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 4 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN5 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 5 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN6 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 6 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN7 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 7 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN8 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 8 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN9 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PB.11, PC.6/PC.7, PD.6/D.7 pin is ignored. 9 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 PB0_PDIO PB0_PDIO GPIO PB.n Pin Data Input/Output 0x240 read-write n 0x0 0x0 PB10_PDIO PB10_PDIO GPIO PB.n Pin Data Input/Output 0x268 read-write n 0x0 0x0 PB11_PDIO PB11_PDIO GPIO PB.n Pin Data Input/Output 0x26C read-write n 0x0 0x0 PB12_PDIO PB12_PDIO GPIO PB.n Pin Data Input/Output 0x270 read-write n 0x0 0x0 PB13_PDIO PB13_PDIO GPIO PB.n Pin Data Input/Output 0x274 read-write n 0x0 0x0 PB14_PDIO PB14_PDIO GPIO PB.n Pin Data Input/Output 0x278 read-write n 0x0 0x0 PB15_PDIO PB15_PDIO GPIO PB.n Pin Data Input/Output 0x27C read-write n 0x0 0x0 PB1_PDIO PB1_PDIO GPIO PB.n Pin Data Input/Output 0x244 read-write n 0x0 0x0 PB2_PDIO PB2_PDIO GPIO PB.n Pin Data Input/Output 0x248 read-write n 0x0 0x0 PB3_PDIO PB3_PDIO GPIO PB.n Pin Data Input/Output 0x24C read-write n 0x0 0x0 PB4_PDIO PB4_PDIO GPIO PB.n Pin Data Input/Output 0x250 read-write n 0x0 0x0 PB5_PDIO PB5_PDIO GPIO PB.n Pin Data Input/Output 0x254 read-write n 0x0 0x0 PB6_PDIO PB6_PDIO GPIO PB.n Pin Data Input/Output 0x258 read-write n 0x0 0x0 PB7_PDIO PB7_PDIO GPIO PB.n Pin Data Input/Output 0x25C read-write n 0x0 0x0 PB8_PDIO PB8_PDIO GPIO PB.n Pin Data Input/Output 0x260 read-write n 0x0 0x0 PB9_PDIO PB9_PDIO GPIO PB.n Pin Data Input/Output 0x264 read-write n 0x0 0x0 PB_DATMSK PB_DATMSK PB Data Output Write Mask 0x4C read-write n 0x0 0x0 PB_DBEN PB_DBEN PB De-bounce Enable Control 0x54 read-write n 0x0 0x0 PB_DINOFF PB_DINOFF PB Digital Input Path Disable Control 0x44 read-write n 0x0 0x0 PB_DOUT PB_DOUT PB Data Output Value 0x48 read-write n 0x0 0x0 PB_INTEN PB_INTEN PB Interrupt Enable Control 0x5C read-write n 0x0 0x0 PB_INTSRC PB_INTSRC PB Interrupt Source Flag 0x60 read-write n 0x0 0x0 PB_INTTYPE PB_INTTYPE PB Interrupt Mode Trigger Type Control 0x58 read-write n 0x0 0x0 PB_MODE PB_MODE PB I/O Mode Control 0x40 read-write n 0x0 0x0 PB_PIN PB_PIN PB Pin Value 0x50 read-write n 0x0 0x0 PB_SLEWCTL PB_SLEWCTL PB High Slew Rate Control 0x68 read-write n 0x0 0x0 PB_SMTEN PB_SMTEN PB Input Schmitt Trigger Enable 0x64 read-write n 0x0 0x0 PC0_PDIO PC0_PDIO GPIO PC.n Pin Data Input/Output 0x280 read-write n 0x0 0x0 PC10_PDIO PC10_PDIO GPIO PC.n Pin Data Input/Output 0x2A8 read-write n 0x0 0x0 PC11_PDIO PC11_PDIO GPIO PC.n Pin Data Input/Output 0x2AC read-write n 0x0 0x0 PC12_PDIO PC12_PDIO GPIO PC.n Pin Data Input/Output 0x2B0 read-write n 0x0 0x0 PC13_PDIO PC13_PDIO GPIO PC.n Pin Data Input/Output 0x2B4 read-write n 0x0 0x0 PC14_PDIO PC14_PDIO GPIO PC.n Pin Data Input/Output 0x2B8 read-write n 0x0 0x0 PC15_PDIO PC15_PDIO GPIO PC.n Pin Data Input/Output 0x2BC read-write n 0x0 0x0 PC1_PDIO PC1_PDIO GPIO PC.n Pin Data Input/Output 0x284 read-write n 0x0 0x0 PC2_PDIO PC2_PDIO GPIO PC.n Pin Data Input/Output 0x288 read-write n 0x0 0x0 PC3_PDIO PC3_PDIO GPIO PC.n Pin Data Input/Output 0x28C read-write n 0x0 0x0 PC4_PDIO PC4_PDIO GPIO PC.n Pin Data Input/Output 0x290 read-write n 0x0 0x0 PC5_PDIO PC5_PDIO GPIO PC.n Pin Data Input/Output 0x294 read-write n 0x0 0x0 PC6_PDIO PC6_PDIO GPIO PC.n Pin Data Input/Output 0x298 read-write n 0x0 0x0 PC7_PDIO PC7_PDIO GPIO PC.n Pin Data Input/Output 0x29C read-write n 0x0 0x0 PC8_PDIO PC8_PDIO GPIO PC.n Pin Data Input/Output 0x2A0 read-write n 0x0 0x0 PC9_PDIO PC9_PDIO GPIO PC.n Pin Data Input/Output 0x2A4 read-write n 0x0 0x0 PC_DATMSK PC_DATMSK PC Data Output Write Mask 0x8C read-write n 0x0 0x0 PC_DBEN PC_DBEN PC De-bounce Enable Control 0x94 read-write n 0x0 0x0 PC_DINOFF PC_DINOFF PC Digital Input Path Disable Control 0x84 read-write n 0x0 0x0 PC_DOUT PC_DOUT PC Data Output Value 0x88 read-write n 0x0 0x0 PC_DRVCTL PC_DRVCTL PC High Drive Strength Control 0xAC read-write n 0x0 0x0 HDRVEN0 Port C Pin[n] Driving Strength Control\n 0 1 read-write 0 Px.n output with basic driving strength #0 1 Px.n output with high driving strength #1 HDRVEN1 Port C Pin[n] Driving Strength Control\n 1 1 read-write 0 Px.n output with basic driving strength #0 1 Px.n output with high driving strength #1 HDRVEN2 Port C Pin[n] Driving Strength Control\n 2 1 read-write 0 Px.n output with basic driving strength #0 1 Px.n output with high driving strength #1 HDRVEN3 Port C Pin[n] Driving Strength Control\n 3 1 read-write 0 Px.n output with basic driving strength #0 1 Px.n output with high driving strength #1 HDRVEN4 Port C Pin[n] Driving Strength Control\n 4 1 read-write 0 Px.n output with basic driving strength #0 1 Px.n output with high driving strength #1 HDRVEN5 Port C Pin[n] Driving Strength Control\n 5 1 read-write 0 Px.n output with basic driving strength #0 1 Px.n output with high driving strength #1 PC_INTEN PC_INTEN PC Interrupt Enable Control 0x9C read-write n 0x0 0x0 PC_INTSRC PC_INTSRC PC Interrupt Source Flag 0xA0 read-write n 0x0 0x0 PC_INTTYPE PC_INTTYPE PC Interrupt Mode Trigger Type Control 0x98 read-write n 0x0 0x0 PC_MODE PC_MODE PC I/O Mode Control 0x80 read-write n 0x0 0x0 PC_PIN PC_PIN PC Pin Value 0x90 read-write n 0x0 0x0 PC_SLEWCTL PC_SLEWCTL PC High Slew Rate Control 0xA8 read-write n 0x0 0x0 PC_SMTEN PC_SMTEN PC Input Schmitt Trigger Enable 0xA4 read-write n 0x0 0x0 PD0_PDIO PD0_PDIO GPIO PD.n Pin Data Input/Output 0x2C0 read-write n 0x0 0x0 PD10_PDIO PD10_PDIO GPIO PD.n Pin Data Input/Output 0x2E8 read-write n 0x0 0x0 PD11_PDIO PD11_PDIO GPIO PD.n Pin Data Input/Output 0x2EC read-write n 0x0 0x0 PD12_PDIO PD12_PDIO GPIO PD.n Pin Data Input/Output 0x2F0 read-write n 0x0 0x0 PD13_PDIO PD13_PDIO GPIO PD.n Pin Data Input/Output 0x2F4 read-write n 0x0 0x0 PD14_PDIO PD14_PDIO GPIO PD.n Pin Data Input/Output 0x2F8 read-write n 0x0 0x0 PD15_PDIO PD15_PDIO GPIO PD.n Pin Data Input/Output 0x2FC read-write n 0x0 0x0 PD1_PDIO PD1_PDIO GPIO PD.n Pin Data Input/Output 0x2C4 read-write n 0x0 0x0 PD2_PDIO PD2_PDIO GPIO PD.n Pin Data Input/Output 0x2C8 read-write n 0x0 0x0 PD3_PDIO PD3_PDIO GPIO PD.n Pin Data Input/Output 0x2CC read-write n 0x0 0x0 PD4_PDIO PD4_PDIO GPIO PD.n Pin Data Input/Output 0x2D0 read-write n 0x0 0x0 PD5_PDIO PD5_PDIO GPIO PD.n Pin Data Input/Output 0x2D4 read-write n 0x0 0x0 PD6_PDIO PD6_PDIO GPIO PD.n Pin Data Input/Output 0x2D8 read-write n 0x0 0x0 PD7_PDIO PD7_PDIO GPIO PD.n Pin Data Input/Output 0x2DC read-write n 0x0 0x0 PD8_PDIO PD8_PDIO GPIO PD.n Pin Data Input/Output 0x2E0 read-write n 0x0 0x0 PD9_PDIO PD9_PDIO GPIO PD.n Pin Data Input/Output 0x2E4 read-write n 0x0 0x0 PD_DATMSK PD_DATMSK PD Data Output Write Mask 0xCC read-write n 0x0 0x0 PD_DBEN PD_DBEN PD De-bounce Enable Control 0xD4 read-write n 0x0 0x0 PD_DINOFF PD_DINOFF PD Digital Input Path Disable Control 0xC4 read-write n 0x0 0x0 PD_DOUT PD_DOUT PD Data Output Value 0xC8 read-write n 0x0 0x0 PD_INTEN PD_INTEN PD Interrupt Enable Control 0xDC read-write n 0x0 0x0 PD_INTSRC PD_INTSRC PD Interrupt Source Flag 0xE0 read-write n 0x0 0x0 PD_INTTYPE PD_INTTYPE PD Interrupt Mode Trigger Type Control 0xD8 read-write n 0x0 0x0 PD_MODE PD_MODE PD I/O Mode Control 0xC0 read-write n 0x0 0x0 PD_PIN PD_PIN PD Pin Value 0xD0 read-write n 0x0 0x0 PD_SLEWCTL PD_SLEWCTL PD High Slew Rate Control 0xE8 read-write n 0x0 0x0 PD_SMTEN PD_SMTEN PD Input Schmitt Trigger Enable 0xE4 read-write n 0x0 0x0 PE0_PDIO PE0_PDIO GPIO PE.n Pin Data Input/Output 0x300 read-write n 0x0 0x0 PE1_PDIO PE1_PDIO GPIO PE.n Pin Data Input/Output 0x304 read-write n 0x0 0x0 PE2_PDIO PE2_PDIO GPIO PE.n Pin Data Input/Output 0x308 read-write n 0x0 0x0 PE_DATMSK PE_DATMSK PE Data Output Write Mask 0x10C read-write n 0x0 0x0 PE_DBEN PE_DBEN PE De-bounce Enable Control 0x114 read-write n 0x0 0x0 PE_DINOFF PE_DINOFF PE Digital Input Path Disable Control 0x104 read-write n 0x0 0x0 PE_DOUT PE_DOUT PE Data Output Value 0x108 read-write n 0x0 0x0 PE_INTEN PE_INTEN PE Interrupt Enable Control 0x11C read-write n 0x0 0x0 PE_INTSRC PE_INTSRC PE Interrupt Source Flag 0x120 read-write n 0x0 0x0 PE_INTTYPE PE_INTTYPE PE Interrupt Mode Trigger Type Control 0x118 read-write n 0x0 0x0 PE_MODE PE_MODE PE I/O Mode Control 0x100 read-write n 0x0 0x0 PE_PIN PE_PIN PE Pin Value 0x110 read-write n 0x0 0x0 PE_SLEWCTL PE_SLEWCTL PE High Slew Rate Control 0x128 read-write n 0x0 0x0 PE_SMTEN PE_SMTEN PE Input Schmitt Trigger Enable 0x124 read-write n 0x0 0x0 PF0_PDIO PF0_PDIO GPIO PF.n Pin Data Input/Output 0x340 read-write n 0x0 0x0 PF1_PDIO PF1_PDIO GPIO PF.n Pin Data Input/Output 0x344 read-write n 0x0 0x0 PF2_PDIO PF2_PDIO GPIO PF.n Pin Data Input/Output 0x348 read-write n 0x0 0x0 PF3_PDIO PF3_PDIO GPIO PF.n Pin Data Input/Output 0x34C read-write n 0x0 0x0 PF4_PDIO PF4_PDIO GPIO PF.n Pin Data Input/Output 0x350 read-write n 0x0 0x0 PF5_PDIO PF5_PDIO GPIO PF.n Pin Data Input/Output 0x354 read-write n 0x0 0x0 PF6_PDIO PF6_PDIO GPIO PF.n Pin Data Input/Output 0x358 read-write n 0x0 0x0 PF7_PDIO PF7_PDIO GPIO PF.n Pin Data Input/Output 0x35C read-write n 0x0 0x0 PF_DATMSK PF_DATMSK PF Data Output Write Mask 0x14C read-write n 0x0 0x0 PF_DBEN PF_DBEN PF De-bounce Enable Control 0x154 read-write n 0x0 0x0 PF_DINOFF PF_DINOFF PF Digital Input Path Disable Control 0x144 read-write n 0x0 0x0 PF_DOUT PF_DOUT PF Data Output Value 0x148 read-write n 0x0 0x0 PF_INTEN PF_INTEN PF Interrupt Enable Control 0x15C read-write n 0x0 0x0 PF_INTSRC PF_INTSRC PF Interrupt Source Flag 0x160 read-write n 0x0 0x0 PF_INTTYPE PF_INTTYPE PF Interrupt Mode Trigger Type Control 0x158 read-write n 0x0 0x0 PF_MODE PF_MODE PF I/O Mode Control 0x140 read-write n 0x0 0x0 PF_PIN PF_PIN PF Pin Value 0x150 read-write n 0x0 0x0 PF_SLEWCTL PF_SLEWCTL PF High Slew Rate Control 0x168 read-write n 0x0 0x0 PF_SMTEN PF_SMTEN PF Input Schmitt Trigger Enable 0x164 read-write n 0x0 0x0 I2C0 I2C Register Map I2C 0x0 0x0 0x30 registers n 0x3C 0x14 registers n I2C_ADDR0 I2C_ADDR0 I2C Slave Address Register0 0x4 read-write n 0x0 0x0 ADDR I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched. 1 7 read-write GC General Call Function\n 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 I2C_ADDR1 I2C_ADDR1 I2C Slave Address Register1 0x18 read-write n 0x0 0x0 I2C_ADDR2 I2C_ADDR2 I2C Slave Address Register2 0x1C read-write n 0x0 0x0 I2C_ADDR3 I2C_ADDR3 I2C Slave Address Register3 0x20 read-write n 0x0 0x0 I2C_ADDRMSK0 I2C_ADDRMSK0 I2C Slave Address Mask Register0 0x24 read-write n 0x0 0x0 ADDRMSK I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 1 7 read-write 0 Mask Disabled (the received corresponding register bit should be exact the same as address register.) 0 1 Mask Enabled (the received corresponding address bit is don't care.) 1 I2C_ADDRMSK1 I2C_ADDRMSK1 I2C Slave Address Mask Register1 0x28 read-write n 0x0 0x0 I2C_ADDRMSK2 I2C_ADDRMSK2 I2C Slave Address Mask Register2 0x2C read-write n 0x0 0x0 I2C_ADDRMSK3 I2C_ADDRMSK3 I2C Slave Address Mask Register3 0x30 read-write n 0x0 0x0 I2C_CLKDIV I2C_CLKDIV I2C Clock Divided Register 0x10 read-write n 0x0 0x0 DIVIDER I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4. 0 8 read-write I2C_CTL I2C_CTL I2C Control Register 0 0x0 read-write n 0x0 0x0 AA Assert Acknowledge Control\n 2 1 read-write I2CEN I2C Controller Enable Bit\n 6 1 read-write 0 I2C controller Disabled #0 1 I2C controller Enabled #1 INTEN Enable Interrupt\n 7 1 read-write 0 I2C interrupt Disabled #0 1 I2C interrupt Enabled #1 SI I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware. If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit. 3 1 read-write STA I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 5 1 read-write STO I2C STOP Control\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically. 4 1 read-write I2C_CTL1 I2C_CTL1 I2C Control Register 1 0x44 read-write n 0x0 0x0 NSTRETCH No Stretch on the I2C Bus\n 7 1 read-write 0 The I2C SCL bus is stretched by hardware if the SI is not cleared in master mode #0 1 The I2C SCL bus is not stretched by hardware if the SI is not cleared in master mode #1 OVRIEN I2C over Run Interrupt Control Bit\nSetting OVRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is over run event in received buffer. 3 1 read-write PDMARST PDMA Reset \n 2 1 read-write 0 No effect #0 1 Reset the PDMA control logic. This bit will be cleared to 0 automatically #1 PDMASTR PDMA Stretch Bit\n 8 1 read-write 0 I2C sends STOP automatically after PDMA transfer done. (only master TX) #0 1 I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared. (only master TX) #1 RXPDMAEN PDMA Receive Channel Available \n 1 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TWOBUFEN Two-level Buffer Enable Bit\n 5 1 read-write 0 Two-level buffer Disabled #0 1 Two-level buffer Enabled #1 TWOBUFRST Two-level Buffer Reset\n 6 1 read-write 0 No effect #0 1 Reset the related counters, two-level buffer state machine, and the content of data buffer #1 TXPDMAEN PDMA Transmit Channel Available\n 0 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 UDRIEN I2C Under Run Interrupt Control Bit\nSetting UDRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is under run event happened in transmitted buffer. 4 1 read-write I2C_DAT I2C_DAT I2C Data Register 0x8 read-write n 0x0 0x0 DAT I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port. 0 8 read-write I2C_STATUS I2C_STATUS I2C Status Register 0 0xC read-only n 0x0 0x0 STATUS I2C Status\n 0 8 read-only I2C_STATUS1 I2C_STATUS1 I2C Status Register 1 0x48 read-only n 0x0 0x0 EMPTY Two-level Buffer Empty\nThis bit is set when buffer empty. 5 1 read-only FULL Two-level Buffer Full\nThis bit is set when buffer full. 4 1 read-only ONBUSY Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected.\n 8 1 read-only 0 The bus is IDLE (both SCLK and SDA High) #0 1 The bus is busy #1 OVR I2C over Run Status Bit\n 6 1 read-only UDR I2C Under Run Status Bit\n 7 1 read-only I2C_TMCTL I2C_TMCTL I2C Timing Configure Control Register 0x4C read-write n 0x0 0x0 HTCTL Hold Time Configure Control Register\nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.\n 6 6 read-write STCTL Setup Time Configure Control Register \nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs. 0 6 read-write I2C_TOCTL I2C_TOCTL I2C Time-out Control Register 0x14 read-write n 0x0 0x0 TOCDIV4 Time-out Counter Input Clock Divided by 4\nWhen it Enabled, The time-out period is extend 4 times.\n 1 1 read-write 0 Time-out period is extend 4 times Disabled #0 1 Time-out period is extend 4 times Enabled #1 TOCEN Time-out Counter Enable Bit\nWhen Enabled, the 14-bit time-out counter will start counting when SI is clear. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.\n 2 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 TOIF Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit. 0 1 read-write I2C_WKCTL I2C_WKCTL I2C Wake-up Control Register 0x3C read-write n 0x0 0x0 NHDBUSEN I2C No Hold BUS Enable Bit\nNote: I2C controller could response when WKIF event is not clear, it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again. 7 1 read-write 0 I2C don't hold bus after wake-up disable #0 1 I2C don't hold bus after wake-up enable #1 WKEN I2C Wake-up Enable Bit\n 0 1 read-write 0 I2C wake-up function Disabled #0 1 I2C wake-up function Enabled #1 I2C_WKSTS I2C_WKSTS I2C Wake-up Status Register 0x40 read-write n 0x0 0x0 WKAKDONE Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF. Software can write 1 to clear this bit. 1 1 read-write 0 The ACK bit cycle of address match frame isn't done #0 1 The ACK bit cycle of address match frame is done in power-down #1 WKIF I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write WRSTSWK Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit. 2 1 read-write 0 Write command be record on the address match wakeup frame #0 1 Read command be record on the address match wakeup frame #1 I2C1 I2C Register Map I2C 0x0 0x0 0x30 registers n 0x3C 0x14 registers n I2C_ADDR0 I2C_ADDR0 I2C Slave Address Register0 0x4 read-write n 0x0 0x0 ADDR I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched. 1 7 read-write GC General Call Function\n 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 I2C_ADDR1 I2C_ADDR1 I2C Slave Address Register1 0x18 read-write n 0x0 0x0 I2C_ADDR2 I2C_ADDR2 I2C Slave Address Register2 0x1C read-write n 0x0 0x0 I2C_ADDR3 I2C_ADDR3 I2C Slave Address Register3 0x20 read-write n 0x0 0x0 I2C_ADDRMSK0 I2C_ADDRMSK0 I2C Slave Address Mask Register0 0x24 read-write n 0x0 0x0 ADDRMSK I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 1 7 read-write 0 Mask Disabled (the received corresponding register bit should be exact the same as address register.) 0 1 Mask Enabled (the received corresponding address bit is don't care.) 1 I2C_ADDRMSK1 I2C_ADDRMSK1 I2C Slave Address Mask Register1 0x28 read-write n 0x0 0x0 I2C_ADDRMSK2 I2C_ADDRMSK2 I2C Slave Address Mask Register2 0x2C read-write n 0x0 0x0 I2C_ADDRMSK3 I2C_ADDRMSK3 I2C Slave Address Mask Register3 0x30 read-write n 0x0 0x0 I2C_CLKDIV I2C_CLKDIV I2C Clock Divided Register 0x10 read-write n 0x0 0x0 DIVIDER I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4. 0 8 read-write I2C_CTL I2C_CTL I2C Control Register 0 0x0 read-write n 0x0 0x0 AA Assert Acknowledge Control\n 2 1 read-write I2CEN I2C Controller Enable Bit\n 6 1 read-write 0 I2C controller Disabled #0 1 I2C controller Enabled #1 INTEN Enable Interrupt\n 7 1 read-write 0 I2C interrupt Disabled #0 1 I2C interrupt Enabled #1 SI I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware. If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit. 3 1 read-write STA I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 5 1 read-write STO I2C STOP Control\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically. 4 1 read-write I2C_CTL1 I2C_CTL1 I2C Control Register 1 0x44 read-write n 0x0 0x0 NSTRETCH No Stretch on the I2C Bus\n 7 1 read-write 0 The I2C SCL bus is stretched by hardware if the SI is not cleared in master mode #0 1 The I2C SCL bus is not stretched by hardware if the SI is not cleared in master mode #1 OVRIEN I2C over Run Interrupt Control Bit\nSetting OVRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is over run event in received buffer. 3 1 read-write PDMARST PDMA Reset \n 2 1 read-write 0 No effect #0 1 Reset the PDMA control logic. This bit will be cleared to 0 automatically #1 PDMASTR PDMA Stretch Bit\n 8 1 read-write 0 I2C sends STOP automatically after PDMA transfer done. (only master TX) #0 1 I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared. (only master TX) #1 RXPDMAEN PDMA Receive Channel Available \n 1 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TWOBUFEN Two-level Buffer Enable Bit\n 5 1 read-write 0 Two-level buffer Disabled #0 1 Two-level buffer Enabled #1 TWOBUFRST Two-level Buffer Reset\n 6 1 read-write 0 No effect #0 1 Reset the related counters, two-level buffer state machine, and the content of data buffer #1 TXPDMAEN PDMA Transmit Channel Available\n 0 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 UDRIEN I2C Under Run Interrupt Control Bit\nSetting UDRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is under run event happened in transmitted buffer. 4 1 read-write I2C_DAT I2C_DAT I2C Data Register 0x8 read-write n 0x0 0x0 DAT I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port. 0 8 read-write I2C_STATUS I2C_STATUS I2C Status Register 0 0xC read-only n 0x0 0x0 STATUS I2C Status\n 0 8 read-only I2C_STATUS1 I2C_STATUS1 I2C Status Register 1 0x48 read-only n 0x0 0x0 EMPTY Two-level Buffer Empty\nThis bit is set when buffer empty. 5 1 read-only FULL Two-level Buffer Full\nThis bit is set when buffer full. 4 1 read-only ONBUSY Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected.\n 8 1 read-only 0 The bus is IDLE (both SCLK and SDA High) #0 1 The bus is busy #1 OVR I2C over Run Status Bit\n 6 1 read-only UDR I2C Under Run Status Bit\n 7 1 read-only I2C_TMCTL I2C_TMCTL I2C Timing Configure Control Register 0x4C read-write n 0x0 0x0 HTCTL Hold Time Configure Control Register\nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.\n 6 6 read-write STCTL Setup Time Configure Control Register \nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs. 0 6 read-write I2C_TOCTL I2C_TOCTL I2C Time-out Control Register 0x14 read-write n 0x0 0x0 TOCDIV4 Time-out Counter Input Clock Divided by 4\nWhen it Enabled, The time-out period is extend 4 times.\n 1 1 read-write 0 Time-out period is extend 4 times Disabled #0 1 Time-out period is extend 4 times Enabled #1 TOCEN Time-out Counter Enable Bit\nWhen Enabled, the 14-bit time-out counter will start counting when SI is clear. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.\n 2 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 TOIF Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit. 0 1 read-write I2C_WKCTL I2C_WKCTL I2C Wake-up Control Register 0x3C read-write n 0x0 0x0 NHDBUSEN I2C No Hold BUS Enable Bit\nNote: I2C controller could response when WKIF event is not clear, it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again. 7 1 read-write 0 I2C don't hold bus after wake-up disable #0 1 I2C don't hold bus after wake-up enable #1 WKEN I2C Wake-up Enable Bit\n 0 1 read-write 0 I2C wake-up function Disabled #0 1 I2C wake-up function Enabled #1 I2C_WKSTS I2C_WKSTS I2C Wake-up Status Register 0x40 read-write n 0x0 0x0 WKAKDONE Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF. Software can write 1 to clear this bit. 1 1 read-write 0 The ACK bit cycle of address match frame isn't done #0 1 The ACK bit cycle of address match frame is done in power-down #1 WKIF I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write WRSTSWK Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit. 2 1 read-write 0 Write command be record on the address match wakeup frame #0 1 Read command be record on the address match wakeup frame #1 INT INT Register Map INT 0x0 0x0 0x8C registers n IRQ0_SRC IRQ0_SRC IRQ0 (BOD) Interrupt Source Identity 0x0 read-only n 0x0 0x0 INT_SRC Interrupt Source\nDefine the interrupt sources for interrupt event. 0 4 read-only IRQ10_SRC IRQ10_SRC IRQ10 (TMR2) Interrupt Source Identity 0x28 read-write n 0x0 0x0 IRQ11_SRC IRQ11_SRC IRQ11 (TMR3) Interrupt Source Identity 0x2C read-write n 0x0 0x0 IRQ12_SRC IRQ12_SRC IRQ12 (UART0) Interrupt Source Identity 0x30 read-write n 0x0 0x0 IRQ13_SRC IRQ13_SRC Reserved 0x34 read-write n 0x0 0x0 IRQ14_SRC IRQ14_SRC IRQ14 (SPI0) Interrupt Source Identity 0x38 read-write n 0x0 0x0 IRQ15_SRC IRQ15_SRC Reserved 0x3C read-write n 0x0 0x0 IRQ16_SRC IRQ16_SRC Reserved 0x40 read-write n 0x0 0x0 IRQ17_SRC IRQ17_SRC Reserved 0x44 read-write n 0x0 0x0 IRQ18_SRC IRQ18_SRC IRQ18 (I2C0) Interrupt Source Identity 0x48 read-write n 0x0 0x0 IRQ19_SRC IRQ19_SRC IRQ19 (I2C1) Interrupt Source Identity 0x4C read-write n 0x0 0x0 IRQ1_SRC IRQ1_SRC IRQ1 (WDT) Interrupt Source Identity 0x4 read-write n 0x0 0x0 IRQ20_SRC IRQ20_SRC IRQ20 (BPWM0) Interrupt Source Identity 0x50 read-write n 0x0 0x0 IRQ21_SRC IRQ21_SRC IRQ21 (BPWM1) Interrupt Source Identity 0x54 read-write n 0x0 0x0 IRQ22_SRC IRQ22_SRC IRQ22 (USCI0) Interrupt Source Identity 0x58 read-write n 0x0 0x0 IRQ23_SRC IRQ23_SRC IRQ23 (USBD) Interrupt Source Identity 0x5C read-write n 0x0 0x0 IRQ24_SRC IRQ24_SRC Reserved 0x60 read-write n 0x0 0x0 IRQ25_SRC IRQ25_SRC IRQ25 (PWM_BRAKE) Interrupt Source Identity 0x64 read-write n 0x0 0x0 IRQ26_SRC IRQ26_SRC IRQ26 (PDMA) Interrupt Source Identity 0x68 read-write n 0x0 0x0 IRQ27_SRC IRQ27_SRC Reserved 0x6C read-write n 0x0 0x0 IRQ28_SRC IRQ28_SRC IRQ28 (PWRWU) Interrupt Source Identity 0x70 read-write n 0x0 0x0 IRQ29_SRC IRQ29_SRC IRQ29 (ADC) Interrupt Source Identity 0x74 read-write n 0x0 0x0 IRQ2_SRC IRQ2_SRC IRQ2 (EINT0/2/4) Interrupt Source Identity 0x8 read-write n 0x0 0x0 IRQ30_SRC IRQ30_SRC IRQ30 (IRC/CLKD) Interrupt Source Identity 0x78 read-write n 0x0 0x0 IRQ31_SRC IRQ31_SRC Reserved 0x7C read-write n 0x0 0x0 IRQ3_SRC IRQ3_SRC IRQ3 (EINT1/3/5) Interrupt Source Identity 0xC read-write n 0x0 0x0 IRQ4_SRC IRQ4_SRC IRQ4 (GPA/GPB) Interrupt Source Identity 0x10 read-write n 0x0 0x0 IRQ5_SRC IRQ5_SRC IRQ5 (GPC/GPD/GPE/GPF) Interrupt Source Identity 0x14 read-write n 0x0 0x0 IRQ6_SRC IRQ6_SRC IRQ6 (PWM0) Interrupt Source Identity 0x18 read-write n 0x0 0x0 IRQ7_SRC IRQ7_SRC IRQ7 (PWM1) Interrupt Source Identity 0x1C read-write n 0x0 0x0 IRQ8_SRC IRQ8_SRC IRQ8 (TMR0) Interrupt Source Identity 0x20 read-write n 0x0 0x0 IRQ9_SRC IRQ9_SRC IRQ9 (TMR1) Interrupt Source Identity 0x24 read-write n 0x0 0x0 MCU_IRQ MCU_IRQ MCU Interrupt Request Source Register 0x84 read-write n 0x0 0x0 MCU_IRQ MCU IRQ Source Register\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0. There are two modes to generate interrupt to Cortex-M0, the normal mode and test mode.\nThe MCU_IRQ collects all interrupts from each peripheral and synchronizes them and interrupts the Cortex-M0.\nWhen the MCU_IRQ[n] is 0: Set MCU_IRQ[n] 1 will generate an interrupt to Cortex-M0 NVIC[n].\nWhen the MCU_IRQ[n] is 1 (mean an interrupt is assert), setting 1 to the MCU_IRQ[n] 1 will clear the interrupt and setting MCU_IRQ[n] 0: has no effect 0 32 read-write MCU_IRQCR MCU_IRQCR MCU Interrupt Request Control Register 0x88 read-write n 0x0 0x0 NMI_SEL NMI_SEL NMI Source Interrupt Select Control Register 0x80 read-write n 0x0 0x0 NMI_EN NMI Interrupt Enable Bit (Write Protect)\nNote: This bit is the protected bit, and programming it needs to write "59h", "16h", and "88h" to address 0x5000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100. 8 1 read-write 0 NMI interrupt Disabled #0 1 NMI interrupt Enabled #1 NMI_SEL NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL. 0 5 read-write PDMA PDMA Register Map PDMA 0x0 0x0 0x64 registers n 0x400 0x44 registers n 0x460 0x4 registers n 0x480 0x8 registers n ABTSTS PDMA_ABTSTS PDMA Channel Read/Write Target Abort Flag Register 0x420 read-write n 0x0 0x0 ABTIF0 PDMA Channel N Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error or transfer source and destination address not alignment; User can write 1 to clear these bits. \n 0 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF1 PDMA Channel N Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error or transfer source and destination address not alignment; User can write 1 to clear these bits. \n 1 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF2 PDMA Channel N Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error or transfer source and destination address not alignment; User can write 1 to clear these bits. \n 2 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF3 PDMA Channel N Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error or transfer source and destination address not alignment; User can write 1 to clear these bits. \n 3 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF4 PDMA Channel N Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error or transfer source and destination address not alignment; User can write 1 to clear these bits. \n 4 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 CHCTL PDMA_CHCTL PDMA Channel Control Register 0x400 read-write n 0x0 0x0 CHEN0 PDMA Channel N Enable Bit\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit. 0 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN1 PDMA Channel N Enable Bit\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit. 1 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN2 PDMA Channel N Enable Bit\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit. 2 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN3 PDMA Channel N Enable Bit\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit. 3 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN4 PDMA Channel N Enable Bit\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit. 4 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CURSCAT0 PDMA_CURSCAT0 Current Scatter-gather Descriptor Table Address of PDMA Channel 0 0x50 read-only n 0x0 0x0 CURADDR PDMA Current Description Address Register (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and only used for Scatter-Gather mode to indicate the current external description address. 0 32 read-only CURSCAT1 PDMA_CURSCAT1 Current Scatter-gather Descriptor Table Address of PDMA Channel 1 0x54 read-write n 0x0 0x0 CURSCAT2 PDMA_CURSCAT2 Current Scatter-gather Descriptor Table Address of PDMA Channel 2 0x58 read-write n 0x0 0x0 CURSCAT3 PDMA_CURSCAT3 Current Scatter-gather Descriptor Table Address of PDMA Channel 3 0x5C read-write n 0x0 0x0 CURSCAT4 PDMA_CURSCAT4 Current Scatter-gather Descriptor Table Address of PDMA Channel 4 0x60 read-write n 0x0 0x0 DSCT0_CTL PDMA_DSCT0_CTL Descriptor Table Control Register of PDMA Channel 0 0x0 read-write n 0x0 0x0 BURSIZE Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type. 4 3 read-write 0 128 Transfers #000 1 64 Transfers #001 2 32 Transfers #010 3 16 Transfers #011 4 8 Transfers #100 5 4 Transfers #101 6 2 Transfers #110 7 1 Transfers #111 DAINC Destination Address Increment\nThis field is used to set the destination address increment size.\n 10 2 read-write 3 No increment (fixed address) #11 OPMODE PDMA Operation Mode Selection\nNote: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete. 0 2 read-write 0 Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically #00 1 Basic mode: The descriptor table only has one task. When this task is finished, the PDMA_INTSTS[n] will be asserted #01 2 Scatter-Gather mode: When operating in this mode, user must give the first descriptor table address in PDMA_DSCT_FIRST register; PDMA controller will ignore this task, then load the next task to execute #10 3 Reserved #11 SAINC Source Address Increment\nThis field is used to set the source address increment size.\n 8 2 read-write 3 No increment (fixed address) #11 TBINTDIS Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is set when PDMA controller finishes transfer task, it will not generates interrupt. \nNote: If this bit set to '1', the TEMPTYF will not be set. 7 1 read-write 0 Table interrupt Enabled #0 1 Table interrupt Disabled #1 TXCNT Transfer Count\nThe TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384, every transfer may be byte, half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA finish each transfer data, this field will be decrease immediately. 16 14 read-write TXTYPE Transfer Type\n 2 1 read-write 0 Burst transfer type #0 1 Single transfer type #1 TXWIDTH Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection 12 2 read-write 0 One byte (8 bit) is transferred for every operation #00 1 One half-word (16 bit) is transferred for every operation #01 2 One word (32-bit) is transferred for every operation #10 3 Reserved #11 DSCT0_DA PDMA_DSCT0_DA Destination Address Register of PDMA Channel 0 0x8 read-write n 0x0 0x0 DA PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA controller. 0 32 read-write DSCT0_FIRST PDMA_DSCT0_FIRST First Scatter-gather Descriptor Table Offset of PDMA Channel 0 0xC read-write n 0x0 0x0 FIRST PDMA First Descriptor Table Offset\nThis field indicates the offset of the first descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the first descriptor table is start from 0x2000_0100, then this field must fill in 0x0100.\nRead Operation:\nWhen operating in scatter-gather mode, the last two bits FIRST[1:0] will become reserved.\nNote1: The first descriptor table address must be word boundary.\nNote2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete. 0 16 read-write DSCT0_SA PDMA_DSCT0_SA Source Address Register of PDMA Channel 0 0x4 read-write n 0x0 0x0 SA PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA controller. 0 32 read-write DSCT1_CTL PDMA_DSCT1_CTL Descriptor Table Control Register of PDMA Channel 1 0x10 read-write n 0x0 0x0 DSCT1_DA PDMA_DSCT1_DA Destination Address Register of PDMA Channel 1 0x18 read-write n 0x0 0x0 DSCT1_FIRST PDMA_DSCT1_FIRST First Scatter-gather Descriptor Table Offset of PDMA Channel 1 0x1C read-write n 0x0 0x0 DSCT1_SA PDMA_DSCT1_SA Source Address Register of PDMA Channel 1 0x14 read-write n 0x0 0x0 DSCT2_CTL PDMA_DSCT2_CTL Descriptor Table Control Register of PDMA Channel 2 0x20 read-write n 0x0 0x0 DSCT2_DA PDMA_DSCT2_DA Destination Address Register of PDMA Channel 2 0x28 read-write n 0x0 0x0 DSCT2_FIRST PDMA_DSCT2_FIRST First Scatter-gather Descriptor Table Offset of PDMA Channel 2 0x2C read-write n 0x0 0x0 DSCT2_SA PDMA_DSCT2_SA Source Address Register of PDMA Channel 2 0x24 read-write n 0x0 0x0 DSCT3_CTL PDMA_DSCT3_CTL Descriptor Table Control Register of PDMA Channel 3 0x30 read-write n 0x0 0x0 DSCT3_DA PDMA_DSCT3_DA Destination Address Register of PDMA Channel 3 0x38 read-write n 0x0 0x0 DSCT3_FIRST PDMA_DSCT3_FIRST First Scatter-gather Descriptor Table Offset of PDMA Channel 3 0x3C read-write n 0x0 0x0 DSCT3_SA PDMA_DSCT3_SA Source Address Register of PDMA Channel 3 0x34 read-write n 0x0 0x0 DSCT4_CTL PDMA_DSCT4_CTL Descriptor Table Control Register of PDMA Channel 4 0x40 read-write n 0x0 0x0 DSCT4_DA PDMA_DSCT4_DA Destination Address Register of PDMA Channel 4 0x48 read-write n 0x0 0x0 DSCT4_FIRST PDMA_DSCT4_FIRST First Scatter-gather Descriptor Table Offset of PDMA Channel 4 0x4C read-write n 0x0 0x0 DSCT4_SA PDMA_DSCT4_SA Source Address Register of PDMA Channel 4 0x44 read-write n 0x0 0x0 INTEN PDMA_INTEN PDMA Interrupt Enable Register 0x418 read-write n 0x0 0x0 INTEN0 PDMA Channel N Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt.\n 0 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTEN1 PDMA Channel N Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt.\n 1 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTEN2 PDMA Channel N Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt.\n 2 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTEN3 PDMA Channel N Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt.\n 3 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTEN4 PDMA Channel N Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt.\n 4 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTSTS PDMA_INTSTS PDMA Interrupt Status Register 0x41C read-write n 0x0 0x0 ABTIF PDMA Read/Write Target Abort Interrupt Flag (Read-only)\nThis bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error.\n 0 1 read-write 0 No AHB bus ERROR response received #0 1 AHB bus ERROR response received #1 REQTOF0 PDMA Channel N Request Time-out Flag\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn, user can write 1 to clear these bits.\n 8 1 read-write 0 No request time-out #0 1 Peripheral request time-out #1 REQTOF1 PDMA Channel N Request Time-out Flag\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn, user can write 1 to clear these bits.\n 9 1 read-write 0 No request time-out #0 1 Peripheral request time-out #1 TDIF Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer.\n 1 1 read-only 0 Not finished yet #0 1 PDMA channel has finished transmission #1 TEIF Table Empty Interrupt Flag (Read Only)\nThis bit indicates PDMA channel scatter-gather table is empty. User can read PDMA_SCATSTS register to indicate which channel scatter-gather table is empty.\n 2 1 read-only 0 PDMA channel scatter-gather table is not empty #0 1 PDMA channel scatter-gather table is empty #1 PAUSE PDMA_PAUSE PDMA Transfer Pause Control Register 0x404 write-only n 0x0 0x0 PAUSE0 PDMA Channel N Transfer Pause Control Register (Write Only)\nUser can set PAUSEn bit field to pause the PDMA transfer.\n 0 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer. When user sets PDMA_PAUSE bit, the operation will pause the on-going transfer, but not finish the rest of transfers, and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and clear request active flag. If re-enable the paused channel agian, the remaining transfers will be processed #1 PAUSE1 PDMA Channel N Transfer Pause Control Register (Write Only)\nUser can set PAUSEn bit field to pause the PDMA transfer.\n 1 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer. When user sets PDMA_PAUSE bit, the operation will pause the on-going transfer, but not finish the rest of transfers, and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and clear request active flag. If re-enable the paused channel agian, the remaining transfers will be processed #1 PAUSE2 PDMA Channel N Transfer Pause Control Register (Write Only)\nUser can set PAUSEn bit field to pause the PDMA transfer.\n 2 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer. When user sets PDMA_PAUSE bit, the operation will pause the on-going transfer, but not finish the rest of transfers, and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and clear request active flag. If re-enable the paused channel agian, the remaining transfers will be processed #1 PAUSE3 PDMA Channel N Transfer Pause Control Register (Write Only)\nUser can set PAUSEn bit field to pause the PDMA transfer.\n 3 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer. When user sets PDMA_PAUSE bit, the operation will pause the on-going transfer, but not finish the rest of transfers, and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and clear request active flag. If re-enable the paused channel agian, the remaining transfers will be processed #1 PAUSE4 PDMA Channel N Transfer Pause Control Register (Write Only)\nUser can set PAUSEn bit field to pause the PDMA transfer.\n 4 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer. When user sets PDMA_PAUSE bit, the operation will pause the on-going transfer, but not finish the rest of transfers, and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and clear request active flag. If re-enable the paused channel agian, the remaining transfers will be processed #1 PRICLR PDMA_PRICLR PDMA Fixed Priority Clear Register 0x414 write-only n 0x0 0x0 FPRICLR0 PDMA Channel N Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority. 0 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR1 PDMA Channel N Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority. 1 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR2 PDMA Channel N Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority. 2 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR3 PDMA Channel N Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority. 3 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR4 PDMA Channel N Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority. 4 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 PRISET PDMA_PRISET PDMA Fixed Priority Setting Register 0x410 read-write n 0x0 0x0 FPRISET0 PDMA Channel N Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, user should use PDMA_PRICLR register to clear fixed priority. 0 1 read-write 0 No effect.\nCorresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority #1 FPRISET1 PDMA Channel N Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, user should use PDMA_PRICLR register to clear fixed priority. 1 1 read-write 0 No effect.\nCorresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority #1 FPRISET2 PDMA Channel N Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, user should use PDMA_PRICLR register to clear fixed priority. 2 1 read-write 0 No effect.\nCorresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority #1 FPRISET3 PDMA Channel N Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, user should use PDMA_PRICLR register to clear fixed priority. 3 1 read-write 0 No effect.\nCorresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority #1 FPRISET4 PDMA Channel N Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, user should use PDMA_PRICLR register to clear fixed priority. 4 1 read-write 0 No effect.\nCorresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority #1 REQSEL0_3 PDMA_REQSEL0_3 PDMA Channel 0 to Channel 3 Request Source Select Register 0x480 read-write n 0x0 0x0 REQSRC0 Channel 0 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 0. User can configure the peripheral by setting REQSRC0.\nNote 1: A peripheral can't assign to two channels at the same time.\nNote 2: This field is useless when transfer between memory and memory. 0 6 read-write 0 Disable PDMA peripheral request 0 1 reserved 1 10 Channel connects to USCI_TX 10 11 Channel connects to USCI_RX 11 12 Reserved 12 13 Reserved 13 14 Reserved 14 15 Reserved 15 16 Channel connects to SPI_TX 16 17 Channel connects to SPI_RX 17 18 Reserved 18 19 Reserved 19 20 Channel connects to ADC_RX 20 21 Channel connects to PWM0_P0_RX 21 22 Channel connects to PWM0_P1_RX 22 23 Channel connects to PWM0_P2_RX 23 24 Channel connects to PWM1_P0_RX 24 25 Channel connects to PWM1_P1_RX 25 26 Channel connects to PWM1_P2_RX 26 27 Reserved 27 28 Channel connects to I2C0_TX 28 29 Channel connects to I2C0_RX 29 30 Channel connects to I2C1_TX 30 31 Channel connects to I2C1_RX 31 32 Channel connects to TMR0 32 33 Channel connects to TMR1 33 34 Channel connects to TMR2 34 35 Channel connects to TMR3 35 4 Channel connects to UART_TX 4 5 Channel connects to UART_RX 5 6 Reserved 6 7 Reserved 7 8 Reserved 8 9 Reserved 9 REQSRC1 Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 8 6 read-write REQSRC2 Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 16 6 read-write REQSRC3 Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 24 6 read-write REQSEL4 PDMA_REQSEL4 PDMA Channel 4 Request Source Select Register 0x484 read-write n 0x0 0x0 REQSRC4 Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 0 6 read-write RESET PDMA_RESET PDMA Channel Reset Control Register 0x460 read-write n 0x0 0x0 RESET0 PDMA Channel N Reset Control Register \nUser can set this bit field to reset the PDMA channel.\nNote: This bit will be cleared automatically after finishing reset process. 0 1 read-write 0 No effect #0 1 Reset PDMA channel n. When user sets PDMA_RESET bit, the operation will finish the on-going transfer and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and clear request active flag. If re-enable channel after channel reset, PDMA will re-load the channel description table to execute PDMA task #1 RESET1 PDMA Channel N Reset Control Register \nUser can set this bit field to reset the PDMA channel.\nNote: This bit will be cleared automatically after finishing reset process. 1 1 read-write 0 No effect #0 1 Reset PDMA channel n. When user sets PDMA_RESET bit, the operation will finish the on-going transfer and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and clear request active flag. If re-enable channel after channel reset, PDMA will re-load the channel description table to execute PDMA task #1 RESET2 PDMA Channel N Reset Control Register \nUser can set this bit field to reset the PDMA channel.\nNote: This bit will be cleared automatically after finishing reset process. 2 1 read-write 0 No effect #0 1 Reset PDMA channel n. When user sets PDMA_RESET bit, the operation will finish the on-going transfer and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and clear request active flag. If re-enable channel after channel reset, PDMA will re-load the channel description table to execute PDMA task #1 RESET3 PDMA Channel N Reset Control Register \nUser can set this bit field to reset the PDMA channel.\nNote: This bit will be cleared automatically after finishing reset process. 3 1 read-write 0 No effect #0 1 Reset PDMA channel n. When user sets PDMA_RESET bit, the operation will finish the on-going transfer and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and clear request active flag. If re-enable channel after channel reset, PDMA will re-load the channel description table to execute PDMA task #1 RESET4 PDMA Channel N Reset Control Register \nUser can set this bit field to reset the PDMA channel.\nNote: This bit will be cleared automatically after finishing reset process. 4 1 read-write 0 No effect #0 1 Reset PDMA channel n. When user sets PDMA_RESET bit, the operation will finish the on-going transfer and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and clear request active flag. If re-enable channel after channel reset, PDMA will re-load the channel description table to execute PDMA task #1 SCATBA PDMA_SCATBA PDMA Scatter-gather Descriptor Table Base Address Register 0x43C read-write n 0x0 0x0 SCATBA PDMA Scatter-gather Descriptor Table Address Register\nIn Scatter-Gather mode, this is the base address for calculating the next link - list address. The next link address equation is \nNote: Only useful in Scatter-Gather mode. 16 16 read-write SCATSTS PDMA_SCATSTS PDMA Scatter-gather Table Empty Status Register 0x428 read-write n 0x0 0x0 TEMPTYFn Table Empty Flag Register\nThis bit indicates which PDMA channel table is empty when channel has a request, no matter request from software or peripheral, but operation mode of channel descriptor table is idle mode, or channel has finished current transfer and next table operation mode is idle mode for PDMA Scatter-Gather mode. User can write 1 to clear these bits.\n 0 5 read-write 0 PDMA channel scatter-gather table is not empty 0 1 PDMA channel scatter-gather table is empty 1 SWREQ PDMA_SWREQ PDMA Software Request Register 0x408 write-only n 0x0 0x0 SWREQ0 PDMA Channel N Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA channel n.\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored. 0 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ1 PDMA Channel N Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA channel n.\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored. 1 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ2 PDMA Channel N Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA channel n.\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored. 2 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ3 PDMA Channel N Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA channel n.\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored. 3 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ4 PDMA Channel N Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA channel n.\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored. 4 1 write-only 0 No effect #0 1 Generate a software request #1 TACTSTS PDMA_TACTSTS PDMA Transfer Active Flag Register 0x42C read-only n 0x0 0x0 TXACTF0 PDMA Channel N Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active.\n 0 1 read-only 0 PDMA channel is not finished #0 1 PDMA channel is active #1 TXACTF1 PDMA Channel N Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active.\n 1 1 read-only 0 PDMA channel is not finished #0 1 PDMA channel is active #1 TXACTF2 PDMA Channel N Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active.\n 2 1 read-only 0 PDMA channel is not finished #0 1 PDMA channel is active #1 TXACTF3 PDMA Channel N Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active.\n 3 1 read-only 0 PDMA channel is not finished #0 1 PDMA channel is active #1 TXACTF4 PDMA Channel N Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active.\n 4 1 read-only 0 PDMA channel is not finished #0 1 PDMA channel is active #1 TDSTS PDMA_TDSTS PDMA Channel Transfer Done Flag Register 0x424 read-write n 0x0 0x0 TDIF0 PDMA Channel N Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.\n 0 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF1 PDMA Channel N Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.\n 1 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF2 PDMA Channel N Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.\n 2 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF3 PDMA Channel N Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.\n 3 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF4 PDMA Channel N Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.\n 4 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TOC0_1 PDMA_TOC0_1 PDMA Channel 0 and Channel 1 Time-out Counter Register 0x440 read-write n 0x0 0x0 TOC0 Time-out Counter for Channel 0\nThis controls the period of time-out function for channel 0. The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC[2:0]) clock.\n 0 16 read-write TOC1 Time-out Counter for Channel 1\nThis controls the period of time-out function for channel 1. The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC[6:4]) clock. The example of time-out period can refer TOC0 bit description. 16 16 read-write TOUTEN PDMA_TOUTEN PDMA Time-out Enable Register 0x434 read-write n 0x0 0x0 TOUTEN0 PDMA Channel 0 Time-out Enable Bit\n 0 1 read-write 0 PDMA Channel 0 time-out function Disable #0 1 PDMA Channel 0 time-out function Enable #1 TOUTEN1 PDMA Channel 1 Time-out Enable Bit\n 1 1 read-write 0 PDMA Channel 1 time-out function Disable #0 1 PDMA Channel 1 time-out function Enable #1 TOUTIEN PDMA_TOUTIEN PDMA Time-out Interrupt Enable Register 0x438 read-write n 0x0 0x0 TOUTIEN0 PDMA Channel 0 Time-out Interrupt Enable Bit\n 0 1 read-write 0 PDMA Channel 0 time-out interrupt Disable #0 1 PDMA Channel 0 time-out interrupt Enable #1 TOUTIEN1 PDMA Channel 1 Time-out Interrupt Enable Bit\n 1 1 read-write 0 PDMA Channel 1 time-out interrupt Disable #0 1 PDMA Channel 1 time-out interrupt Enable #1 TOUTPSC PDMA_TOUTPSC PDMA Time-out Prescaler Register 0x430 read-write n 0x0 0x0 TOUTPSC0 PDMA Channel 0 Time-out Clock Source Prescaler Bits\n 0 3 read-write 0 PDMA channel 0 time-out clock source is HCLK/28 #000 1 PDMA channel 0 time-out clock source is HCLK/29 #001 2 PDMA channel 0 time-out clock source is HCLK/210 #010 3 PDMA channel 0 time-out clock source is HCLK/211 #011 4 PDMA channel 0 time-out clock source is HCLK/212 #100 5 PDMA channel 0 time-out clock source is HCLK/213 #101 6 PDMA channel 0 time-out clock source is HCLK/214 #110 7 PDMA channel 0 time-out clock source is HCLK/215 #111 TOUTPSC1 PDMA Channel 1 Time-out Clock Source Prescaler Bits\n 4 3 read-write 0 PDMA channel 1 time-out clock source is HCLK/28 #000 1 PDMA channel 1 time-out clock source is HCLK/29 #001 2 PDMA channel 1 time-out clock source is HCLK/210 #010 3 PDMA channel 1 time-out clock source is HCLK/211 #011 4 PDMA channel 1 time-out clock source is HCLK/212 #100 5 PDMA channel 1 time-out clock source is HCLK/213 #101 6 PDMA channel 1 time-out clock source is HCLK/214 #110 7 PDMA channel 1 time-out clock source is HCLK/215 #111 TRGSTS PDMA_TRGSTS PDMA Channel Request Status Register 0x40C read-only n 0x0 0x0 REQSTS0 PDMA Channel N Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer. 0 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS1 PDMA Channel N Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer. 1 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS2 PDMA Channel N Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer. 2 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS3 PDMA Channel N Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer. 3 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS4 PDMA Channel N Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer. 4 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 PWM0 PWM Register Map PWM 0x0 0x0 0x8 registers n 0x10 0x18 registers n 0x110 0x8 registers n 0x120 0x4 registers n 0x200 0x4C registers n 0x250 0x8 registers n 0x30 0x4 registers n 0x304 0x4 registers n 0x30C 0x4 registers n 0x314 0x4 registers n 0x31C 0x18 registers n 0x38 0x4 registers n 0x40 0x4 registers n 0x50 0x18 registers n 0x70 0xC registers n 0x90 0x4 registers n 0x98 0x4 registers n 0xA0 0x4 registers n 0xB0 0x40 registers n 0xF8 0x8 registers n PWM_ADCTS0 PWM_ADCTS0 PWM Trigger ADC Source Select Register 0 0xF8 read-write n 0x0 0x0 TRGEN0 PWM_CH0 Trigger ADC Enable Bit 7 1 read-write TRGEN1 PWM_CH1 Trigger ADC Enable Bit 15 1 read-write TRGEN2 PWM_CH2 Trigger ADC Enable Bit 23 1 read-write TRGEN3 PWM_CH3 Trigger ADC Enable Bit 31 1 read-write TRGSEL0 PWM_CH0 Trigger ADC Source Select\n 0 4 read-write 0 PWM_CH0 zero point #0000 1 PWM_CH0 period point #0001 2 PWM_CH0 zero or period point #0010 3 PWM_CH0 up-count CMPDAT point #0011 4 PWM_CH0 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM_CH1 up-count CMPDAT point #1000 9 PWM_CH1 down-count CMPDAT point #1001 TRGSEL1 PWM_CH1 Trigger ADC Source Select\n 8 4 read-write 0 PWM_CH0 zero point #0000 1 PWM_CH0 period point #0001 2 PWM_CH0 zero or period point #0010 3 PWM_CH0 up-count CMPDAT point #0011 4 PWM_CH0 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM_CH1 up-count CMPDAT point #1000 9 PWM_CH1 down-count CMPDAT point #1001 TRGSEL2 PWM_CH2 Trigger ADC Source Select\n 16 4 read-write 0 PWM_CH2 zero point #0000 1 PWM_CH2 period point #0001 2 PWM_CH2 zero or period point #0010 3 PWM_CH2 up-count CMPDAT point #0011 4 PWM_CH2 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM_CH3 up-count CMPDAT point #1000 9 PWM_CH3 down-count CMPDAT point #1001 TRGSEL3 PWM_CH3 Trigger ADC Source Select\n 24 4 read-write 0 PWM_CH2 zero point #0000 1 PWM_CH2 period point #0001 2 PWM_CH2 zero or period point #0010 3 PWM_CH2 up-count CMPDAT point #0011 4 PWM_CH2 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM_CH3 up-count CMPDAT point #1000 9 PWM_CH3 down-count CMPDAT point #1001 PWM_ADCTS1 PWM_ADCTS1 PWM Trigger ADC Source Select Register 1 0xFC read-write n 0x0 0x0 TRGEN4 PWM_CH4 Trigger ADC Enable Bit 7 1 read-write TRGEN5 PWM_CH5 Trigger ADC Enable Bit 15 1 read-write TRGSEL4 PWM_CH4 Trigger ADC Source Select\n 0 4 read-write 0 PWM_CH4 zero point #0000 1 PWM_CH4 period point #0001 2 PWM_CH4 zero or period point #0010 3 PWM_CH4 up-count CMPDAT point #0011 4 PWM_CH4 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM_CH5 up-count CMPDAT point #1000 9 PWM_CH5 down-count CMPDAT point #1001 TRGSEL5 PWM_CH5 Trigger ADC Source Select\n 8 4 read-write 0 PWM_CH4 zero point #0000 1 PWM_CH4 period point #0001 2 PWM_CH4 zero or period point #0010 3 PWM_CH4 up-count CMPDAT point #0011 4 PWM_CH4 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM_CH5 up-count CMPDAT point #1000 9 PWM_CH5 down-count CMPDAT point #1001 PWM_BNF PWM_BNF PWM Brake Noise Filter Register 0xC0 read-write n 0x0 0x0 BK0SRC Brake 0 Pin Source Select\nFor PWM0 setting:\n 16 1 read-write 0 Brake 0 pin source come from PWM0_BRAKE0.\nBrake 0 pin source come from PWM1_BRAKE0 #0 1 Brake 0 pin source come from PWM1_BRAKE0.\nBrake 0 pin source come from PWM0_BRAKE0 #1 BK1SRC Brake 1 Pin Source Select\nFor PWM0 setting:\n 24 1 read-write 0 Brake 1 pin source come from PWM0_BRAKE1.\nBrake 1 pin source come from PWM1_BRAKE1 #0 1 Brake 1 pin source come from PWM1_BRAKE1.\nBrake 1 pin source come from PWM0_BRAKE1 #1 BRK0FCNT Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT. 4 3 read-write BRK0FCS Brake 0 Edge Detector Filter Clock Selection\n 1 3 read-write 0 Filter clock is HCLK #000 1 Filter clock is HCLK/2 #001 2 Filter clock is HCLK/4 #010 3 Filter clock is HCLK/8 #011 4 Filter clock is HCLK/16 #100 5 Filter clock is HCLK/32 #101 6 Filter clock is HCLK/64 #110 7 Filter clock is HCLK/128 #111 BRK0FEN PWM Brake 0 Noise Filter Enable Bit\n 0 1 read-write 0 Noise filter of PWM Brake 0 Disabled #0 1 Noise filter of PWM Brake 0 Enabled #1 BRK0PINV Brake 0 Pin Inverse\n 7 1 read-write 0 The state of pin PWMx_BRAKE0 is passed to the negative edge detector #0 1 The inversed state of pin PWMx_BRAKE10 is passed to the negative edge detector #1 BRK1FCNT Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. 12 3 read-write BRK1FCS Brake 1 Edge Detector Filter Clock Selection\n 9 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 BRK1FEN PWM Brake 1 Noise Filter Enable Bit\n 8 1 read-write 0 Noise filter of PWM Brake 1 Disabled #0 1 Noise filter of PWM Brake 1 Enabled #1 BRK1PINV Brake 1 Pin Inverse\n 15 1 read-write 0 The state of pin PWMx_BRAKE1 is passed to the negative edge detector #0 1 The inversed state of pin PWMx_BRAKE1 is passed to the negative edge detector #1 PWM_BRKCTL0_1 PWM_BRKCTL0_1 PWM Brake Edge Detect Control Register 0_1 0xC8 read-write n 0x0 0x0 BRKAEVEN PWM Brake Action Select for Even Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register. 16 2 read-write 0 PWM even channel level-detect brake function not affect channel output #00 1 PWM even channel output tri-state when level-detect brake happened #01 2 PWM even channel output low level when level-detect brake happened #10 3 PWM even channel output high level when level-detect brake happened #11 BRKAODD PWM Brake Action Select for Odd Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register. 18 2 read-write 0 PWM odd channel level-detect brake function not affect channel output #00 1 PWM odd channel output tri-state when level-detect brake happened #01 2 PWM odd channel output low level when level-detect brake happened #10 3 PWM odd channel output high level when level-detect brake happened #11 BRKP0EEN Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 4 1 read-write 0 BKP0 pin as edge-detect brake source Disabled #0 1 BKP0 pin as edge-detect brake source Enabled #1 BRKP0LEN Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 12 1 read-write 0 PWMx_BRAKE0 pin as level-detect brake source Disabled #0 1 PWMx_BRAKE0 pin as level-detect brake source Enabled #1 BRKP1EEN Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 5 1 read-write 0 BKP1 pin as edge-detect brake source Disabled #0 1 BKP1 pin as edge-detect brake source Enabled #1 BRKP1LEN Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 13 1 read-write 0 PWMx_BRAKE1 pin as level-detect brake source Disabled #0 1 PWMx_BRAKE1 pin as level-detect brake source Enabled #1 SYSEEN Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 7 1 read-write 0 System Fail condition as edge-detect brake source Disabled #0 1 System Fail condition as edge-detect brake source Enabled #1 SYSLEN Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 15 1 read-write 0 System Fail condition as level-detect brake source Disabled #0 1 System Fail condition as level-detect brake source Enabled #1 PWM_BRKCTL2_3 PWM_BRKCTL2_3 PWM Brake Edge Detect Control Register 2_3 0xCC read-write n 0x0 0x0 PWM_BRKCTL4_5 PWM_BRKCTL4_5 PWM Brake Edge Detect Control Register 4_5 0xD0 read-write n 0x0 0x0 PWM_CAPCTL PWM_CAPCTL PWM Capture Control Register 0x204 read-write n 0x0 0x0 CAPENn Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated 0 1 Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) 1 CAPINVn Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n.\n 8 6 read-write 0 Capture source inverter Disabled 0 1 Capture source inverter Enabled. Reverse the input signal from GPIO 1 FCRLDENn Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n.\n 24 6 read-write 0 Falling capture reload counter Disabled 0 1 Falling capture reload counter Enabled 1 RCRLDENn Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n.\n 16 6 read-write 0 Rising capture reload counter Disabled 0 1 Rising capture reload counter Enabled 1 PWM_CAPIEN PWM_CAPIEN PWM Capture Interrupt Enable Register 0x250 read-write n 0x0 0x0 CAPFIENn PWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\n 8 6 read-write 0 Capture falling edge latch interrupt Disabled 0 1 Capture falling edge latch interrupt Enabled 1 CAPRIENn PWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 Capture rising edge latch interrupt Disabled 0 1 Capture rising edge latch interrupt Enabled 1 PWM_CAPIF PWM_CAPIF PWM Capture Interrupt Flag Register 0x254 read-write n 0x0 0x0 CFLIFn PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\n 8 6 read-write 0 No capture falling latch condition happened 0 1 Capture falling latch condition happened, this flag will be set to high 1 CRLIFn PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 No capture rising latch condition happened 0 1 Capture rising latch condition happened, this flag will be set to high 1 PWM_CAPINEN PWM_CAPINEN PWM Capture Input Enable Register 0x200 read-write n 0x0 0x0 CAPINENn Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0 0 1 PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin 1 PWM_CAPSTS PWM_CAPSTS PWM Capture Status Register 0x208 read-only n 0x0 0x0 CFLIFOVn Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF. 8 6 read-only CRLIFOVn Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF. 0 6 read-only PWM_CLKPSC0_1 PWM_CLKPSC0_1 PWM Clock Pre-scale Register 0_1 0x14 read-write n 0x0 0x0 CLKPSC PWM Counter Clock Pre-scale \nThe clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1). 0 12 read-write PWM_CLKPSC2_3 PWM_CLKPSC2_3 PWM Clock Pre-scale Register 2_3 0x18 read-write n 0x0 0x0 PWM_CLKPSC4_5 PWM_CLKPSC4_5 PWM Clock Pre-scale Register 4_5 0x1C read-write n 0x0 0x0 PWM_CLKSRC PWM_CLKSRC PWM Clock Source Register 0x10 read-write n 0x0 0x0 ECLKSRC0 PWM_CH01 External Clock Source Select\n 0 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 ECLKSRC2 PWM_CH23 External Clock Source Select\n 8 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 ECLKSRC4 PWM_CH45 External Clock Source Select\n 16 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 PWM_CMPBUF0 PWM_CMPBUF0 PWM CMPDAT0 Buffer 0x31C read-only n 0x0 0x0 CMPBUF PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register. 0 16 read-only PWM_CMPBUF1 PWM_CMPBUF1 PWM CMPDAT1 Buffer 0x320 read-write n 0x0 0x0 PWM_CMPBUF2 PWM_CMPBUF2 PWM CMPDAT2 Buffer 0x324 read-write n 0x0 0x0 PWM_CMPBUF3 PWM_CMPBUF3 PWM CMPDAT3 Buffer 0x328 read-write n 0x0 0x0 PWM_CMPBUF4 PWM_CMPBUF4 PWM CMPDAT4 Buffer 0x32C read-write n 0x0 0x0 PWM_CMPBUF5 PWM_CMPBUF5 PWM CMPDAT5 Buffer 0x330 read-write n 0x0 0x0 PWM_CMPDAT0 PWM_CMPDAT0 PWM Comparator Register 0 0x50 read-write n 0x0 0x0 CMP PWM Comparator Register\nCMP use to compare with CNT to generate PWM waveform, interrupt and trigger ADC.\nIn independent mode, PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode, PWM_CMPDAT0, 2, 4 denote as first compared point, and PWM_CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM_CH0 and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5. 0 16 read-write PWM_CMPDAT1 PWM_CMPDAT1 PWM Comparator Register 1 0x54 read-write n 0x0 0x0 PWM_CMPDAT2 PWM_CMPDAT2 PWM Comparator Register 2 0x58 read-write n 0x0 0x0 PWM_CMPDAT3 PWM_CMPDAT3 PWM Comparator Register 3 0x5C read-write n 0x0 0x0 PWM_CMPDAT4 PWM_CMPDAT4 PWM Comparator Register 4 0x60 read-write n 0x0 0x0 PWM_CMPDAT5 PWM_CMPDAT5 PWM Comparator Register 5 0x64 read-write n 0x0 0x0 PWM_CNT0 PWM_CNT0 PWM Counter Register 0 0x90 read-only n 0x0 0x0 CNT PWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter. 0 16 read-only DIRF PWM Direction Indicator Flag (Read Only)\n 16 1 read-only 0 Counter is Down count #0 1 Counter is UP count #1 PWM_CNT2 PWM_CNT2 PWM Counter Register 2 0x98 read-write n 0x0 0x0 PWM_CNT4 PWM_CNT4 PWM Counter Register 4 0xA0 read-write n 0x0 0x0 PWM_CNTCLR PWM_CNTCLR PWM Clear Counter Register 0x24 read-write n 0x0 0x0 CNTCLR0 Clear PWM Counter Control Bit 0\nIt is automatically cleared by hardware.\n 0 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0000H #1 CNTCLR2 Clear PWM Counter Control Bit 2\nIt is automatically cleared by hardware.\n 2 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0000H #1 CNTCLR4 Clear PWM Counter Control Bit 4\nIt is automatically cleared by hardware.\n 4 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0000H #1 PWM_CNTEN PWM_CNTEN PWM Counter Enable Register 0x20 read-write n 0x0 0x0 CNTEN0 PWM Counter Enable 0\n 0 1 read-write 0 PWM Counter and clock prescaler Stop Running #0 1 PWM Counter and clock prescaler Start Running #1 CNTEN2 PWM Counter Enable 2\n 2 1 read-write 0 PWM Counter and clock prescaler Stop Running #0 1 PWM Counter and clock prescaler Start Running #1 CNTEN4 PWM Counter Enable 4\n 4 1 read-write 0 PWM Counter and clock prescaler Stop Running #0 1 PWM Counter and clock prescaler Start Running #1 PWM_CTL0 PWM_CTL0 PWM Control Register 0 0x0 read-write n 0x0 0x0 CTRLDn Center Load Enable Bits\n \nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 0 1 read-write 0 Center Lodaing mode is disable for corresponding PWM channel n #0 1 Center Lodaing mode is enable for corresponding PWM channel n #1 DBGHALT ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 30 1 read-write 0 ICE debug mode counter halt disable #0 1 ICE debug mode counter halt enable #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable (Write Protect)\nPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement affects PWM output #0 1 ICE debug mode acknowledgement disabled #1 IMMLDENn Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 16 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 PWM_CTL1 PWM_CTL1 PWM Control Register 1 0x4 read-write n 0x0 0x0 CNTTYPE0 PWM Counter Behavior Type 0\nThe two bits control channel1 and channel0\n 0 2 read-write 0 Up counter type (supports in capture mode) #00 1 Down count type (supports in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 CNTTYPE2 PWM Counter Behavior Type 2\nThe two bits control channel3 and channel2\n 4 2 read-write 0 Up counter type (supports in capture mode) #00 1 Down count type (supports in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 CNTTYPE4 PWM Counter Behavior Type 4\nThe two bits control channel5 and channel4\n 8 2 read-write 0 Up counter type (supports in capture mode) #00 1 Down count type (supports in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 PWMMODEn PWM Mode\nEach bit n controls the corresponding PWM channel n.\nNote: When operating in group function, these bits must all set to the same mode. 24 3 read-write 0 PWM independent mode 0 1 PWM complementary mode 1 PWM_DTCTL0_1 PWM_DTCTL0_1 PWM Dead-time Control Register 0_1 0x70 read-write n 0x0 0x0 DTCKSEL Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 24 1 read-write 0 Dead-time clock source from PWM_CLK #0 1 Dead-time clock source from prescaler output #1 DTCNT Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: These bits are write protected. Refer to SYS_REGLCTL register. 0 12 read-write DTEN Enable Dead-time Insertion for PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 16 1 read-write 0 Dead-time insertion Disabled on the pin pair #0 1 Dead-time insertion Enabled on the pin pair #1 PWM_DTCTL2_3 PWM_DTCTL2_3 PWM Dead-time Control Register 2_3 0x74 read-write n 0x0 0x0 PWM_DTCTL4_5 PWM_DTCTL4_5 PWM Dead-time Control Register 4_5 0x78 read-write n 0x0 0x0 PWM_FAILBRK PWM_FAILBRK PWM System Fail Brake Control Register 0xC4 read-write n 0x0 0x0 BODBRKEN Brown-out Detection Trigger PWM Brake Function 0 Enable Bit\n 1 1 read-write 0 Brake Function triggered by BOD Disabled #0 1 Brake Function triggered by BOD Enabled #1 CORBRKEN Core Lockup Detection Trigger PWM Brake Function 0 Enable Bit\n 3 1 read-write 0 Brake Function triggered by Core lockup detection Disabled #0 1 Brake Function triggered by Core lockup detection Enabled #1 CSSBRKEN Clock Security System Detection Trigger PWM Brake Function 0 Enable Bit\n 0 1 read-write 0 Brake Function triggered by CSS detection Disabled #0 1 Brake Function triggered by CSS detection Enabled #1 PWM_FCAPDAT0 PWM_FCAPDAT0 PWM Falling Capture Data Register 0 0x210 read-only n 0x0 0x0 FCAPDAT PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened, the PWM counter value will be saved in this register. 0 16 read-only PWM_FCAPDAT1 PWM_FCAPDAT1 PWM Falling Capture Data Register 1 0x218 read-write n 0x0 0x0 PWM_FCAPDAT2 PWM_FCAPDAT2 PWM Falling Capture Data Register 2 0x220 read-write n 0x0 0x0 PWM_FCAPDAT3 PWM_FCAPDAT3 PWM Falling Capture Data Register 3 0x228 read-write n 0x0 0x0 PWM_FCAPDAT4 PWM_FCAPDAT4 PWM Falling Capture Data Register 4 0x230 read-write n 0x0 0x0 PWM_FCAPDAT5 PWM_FCAPDAT5 PWM Falling Capture Data Register 5 0x238 read-write n 0x0 0x0 PWM_INTEN0 PWM_INTEN0 PWM Interrupt Enable Register 0 0xE0 read-write n 0x0 0x0 CMPDIENn PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. 24 6 read-write 0 Compare down count interrupt Disabled 0 1 Compare down count interrupt Enabled 1 CMPUIENn PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. 16 6 read-write 0 Compare up count interrupt Disabled 0 1 Compare up count interrupt Enabled 1 PIEN0 PWM Period Point Interrupt Enable 0\nNote: When counter type is up-down, period point means center point. 8 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN2 PWM Period Point Interrupt Enable 2\nNote: When counter type is up-down, period point means center point. 10 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN4 PWM Period Point Interrupt Enable 4\nNote: When counter type is up-down, period point means center point. 12 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 ZIEN0 PWM Zero Point Interrupt Enable 0\nNote: Odd channels will read always 0 at complementary mode. 0 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN2 PWM Zero Point Interrupt Enable 2\nNote: Odd channels will read always 0 at complementary mode. 2 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN4 PWM Zero Point Interrupt Enable 4\nNote: Odd channels will read always 0 at complementary mode. 4 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 PWM_INTEN1 PWM_INTEN1 PWM Interrupt Enable Register 1 0xE4 read-write n 0x0 0x0 BRKEIEN0_1 PWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 Edge-detect Brake interrupt for channel0/1 Disabled #0 1 Edge-detect Brake interrupt for channel0/1 Enabled #1 BRKEIEN2_3 PWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 Edge-detect Brake interrupt for channel2/3 Disabled #0 1 Edge-detect Brake interrupt for channel2/3 Enabled #1 BRKEIEN4_5 PWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bitr is write protected. Refer to SYS_REGLCTL register. 2 1 read-write 0 Edge-detect Brake interrupt for channel4/5 Disabled #0 1 Edge-detect Brake interrupt for channel4/5 Enabled #1 BRKLIEN0_1 PWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 Level-detect Brake interrupt for channel0/1 Disabled #0 1 Level-detect Brake interrupt for channel0/1 Enabled #1 BRKLIEN2_3 PWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 Level-detect Brake interrupt for channel2/3 Disabled #0 1 Level-detect Brake interrupt for channel2/3 Enabled #1 BRKLIEN4_5 PWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 10 1 read-write 0 Level-detect Brake interrupt for channel4/5 Disabled #0 1 Level-detect Brake interrupt for channel4/5 Enabled #1 PWM_INTSTS0 PWM_INTSTS0 PWM Interrupt Flag Register 0 0xE8 read-write n 0x0 0x0 CMPDIFn PWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. 24 6 read-write CMPUIFn PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. 16 6 read-write PIF0 PWM Period Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches PWM_PERIOD0, software can write 1 to clear this bit to zero. 8 1 read-write PIF2 PWM Period Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches PWM_PERIOD2, software can write 1 to clear this bit to zero. 10 1 read-write PIF4 PWM Period Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches PWM_PERIOD4, software can write 1 to clear this bit to zero. 12 1 read-write ZIF0 PWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches zero, software can write 1 to clear this bit to zero. 0 1 read-write ZIF2 PWM Zero Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches zero, software can write 1 to clear this bit to zero. 2 1 read-write ZIF4 PWM Zero Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches zero, software can write 1 to clear this bit to zero. 4 1 read-write PWM_INTSTS1 PWM_INTSTS1 PWM Interrupt Flag Register 1 0xEC read-write n 0x0 0x0 BRKEIF0 PWM Channel0 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 PWM channel0 edge-detect brake event do not happened #0 1 When PWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF1 PWM Channel1 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 PWM channel1 edge-detect brake event do not happened #0 1 When PWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF2 PWM Channel2 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 2 1 read-write 0 PWM channel2 edge-detect brake event do not happened #0 1 When PWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF3 PWM Channel3 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 3 1 read-write 0 PWM channel3 edge-detect brake event do not happened #0 1 When PWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF4 PWM Channel4 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 4 1 read-write 0 PWM channel4 edge-detect brake event do not happened #0 1 When PWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF5 PWM Channel5 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 5 1 read-write 0 PWM channel5 edge-detect brake event do not happened #0 1 When PWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKESTS0 PWM Channel0 Edge-detect Brake Status\n 16 1 read-write 0 PWM channel0 edge-detect brake state is released #0 1 When PWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state, writing 1 to clear #1 BRKESTS1 PWM Channel1 Edge-detect Brake Status\n 17 1 read-write 0 PWM channel1 edge-detect brake state is released #0 1 When PWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state, writing 1 to clear #1 BRKESTS2 PWM Channel2 Edge-detect Brake Status\n 18 1 read-write 0 PWM channel2 edge-detect brake state is released #0 1 When PWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state, writing 1 to clear #1 BRKESTS3 PWM Channel3 Edge-detect Brake Status\n 19 1 read-write 0 PWM channel3 edge-detect brake state is released #0 1 When PWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state, writing 1 to clear #1 BRKESTS4 PWM Channel4 Edge-detect Brake Status\n 20 1 read-write 0 PWM channel4 edge-detect brake state is released #0 1 When PWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state, writing 1 to clear #1 BRKESTS5 PWM Channel5 Edge-detect Brake Status\n 21 1 read-write 0 PWM channel5 edge-detect brake state is released #0 1 When PWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state, writing 1 to clear #1 BRKLIF0 PWM Channel0 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 PWM channel0 level-detect brake event do not happened #0 1 When PWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF1 PWM Channel1 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 PWM channel1 level-detect brake event do not happened #0 1 When PWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF2 PWM Channel2 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 10 1 read-write 0 PWM channel2 level-detect brake event do not happened #0 1 When PWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF3 PWM Channel3 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 11 1 read-write 0 PWM channel3 level-detect brake event do not happened #0 1 When PWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF4 PWM Channel4 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 12 1 read-write 0 PWM channel4 level-detect brake event do not happened #0 1 When PWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF5 PWM Channel5 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 13 1 read-write 0 PWM channel5 level-detect brake event do not happened #0 1 When PWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLSTS0 PWM Channel0 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 24 1 read-only 0 PWM channel0 level-detect brake state is released #0 1 When PWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state #1 BRKLSTS1 PWM Channel1 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 25 1 read-only 0 PWM channel1 level-detect brake state is released #0 1 When PWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state #1 BRKLSTS2 PWM Channel2 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 26 1 read-only 0 PWM channel2 level-detect brake state is released #0 1 When PWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state #1 BRKLSTS3 PWM Channel3 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 27 1 read-only 0 PWM channel3 level-detect brake state is released #0 1 When PWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state #1 BRKLSTS4 PWM Channel4 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 28 1 read-only 0 PWM channel4 level-detect brake state is released #0 1 When PWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state #1 BRKLSTS5 PWM Channel5 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 29 1 read-only 0 PWM channel5 level-detect brake state is released #0 1 When PWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state #1 PWM_MSK PWM_MSK PWM Mask Data Register 0xBC read-write n 0x0 0x0 MSKDATn PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 Output logic low to PWMn 0 1 Output logic high to PWMn 1 PWM_MSKEN PWM_MSKEN PWM Mask Enable Register 0xB8 read-write n 0x0 0x0 MSKENn PWM Mask Enable Bits\nEach bit n controls the corresponding PWM channel n.\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. \n 0 6 read-write 0 PWM output signal is non-masked 0 1 PWM output signal is masked and output MSKDATn data 1 PWM_PBUF0 PWM_PBUF0 PWM PERIOD0 Buffer 0x304 read-only n 0x0 0x0 PBUF PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register. 0 16 read-only PWM_PBUF2 PWM_PBUF2 PWM PERIOD2 Buffer 0x30C read-write n 0x0 0x0 PWM_PBUF4 PWM_PBUF4 PWM PERIOD4 Buffer 0x314 read-write n 0x0 0x0 PWM_PDMACAP0_1 PWM_PDMACAP0_1 PWM Capture Channel 01 PDMA Register 0x240 read-only n 0x0 0x0 CAPBUF PWM Capture PDMA Register (Read Only)\nThis register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA. 0 16 read-only PWM_PDMACAP2_3 PWM_PDMACAP2_3 PWM Capture Channel 23 PDMA Register 0x244 read-write n 0x0 0x0 PWM_PDMACAP4_5 PWM_PDMACAP4_5 PWM Capture Channel 45 PDMA Register 0x248 read-write n 0x0 0x0 PWM_PDMACTL PWM_PDMACTL PWM PDMA Control Register 0x23C read-write n 0x0 0x0 CAPMOD0_1 Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer \n 1 2 read-write 0 Reserved #00 1 PWM_RCAPDAT0/1 #01 2 PWM_FCAPDAT0/1 #10 3 Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1 #11 CAPMOD2_3 Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer \n 9 2 read-write 0 Reserved #00 1 PWM_RCAPDAT2/3 #01 2 PWM_FCAPDAT2/3 #10 3 Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3 #11 CAPMOD4_5 Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer \n 17 2 read-write 0 Reserved #00 1 PWM_RCAPDAT4/5 #01 2 PWM_FCAPDAT4/5 #10 3 Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5 #11 CAPORD0_1 Capture Channel 0/1 Rising/Falling Order \n 3 1 read-write 0 PWM_FCAPDAT0/1 is the first captured data to memory #0 1 PWM_RCAPDAT0/1 is the first captured data to memory #1 CAPORD2_3 Capture Channel 2/3 Rising/Falling Order \n 11 1 read-write 0 PWM_FCAPDAT2/3 is the first captured data to memory #0 1 PWM_RCAPDAT2/3 is the first captured data to memory #1 CAPORD4_5 Capture Channel 4/5 Rising/Falling Order \n 19 1 read-write 0 PWM_FCAPDAT4/5 is the first captured data to memory #0 1 PWM_RCAPDAT4/5 is the first captured data to memory #1 CHEN0_1 Channel 0/1 PDMA Enable Bit\n 0 1 read-write 0 Channel 0/1 PDMA function Disabled #0 1 Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory #1 CHEN2_3 Channel 2/3 PDMA Enable Bit\n 8 1 read-write 0 Channel 2/3 PDMA function Disabled #0 1 Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory #1 CHEN4_5 Channel 4/5 PDMA Enable Bit\n 16 1 read-write 0 Channel 4/5 PDMA function Disabled #0 1 Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory #1 CHSEL0_1 Select Channel 0/1 to Do PDMA Transfer \n 4 1 read-write 0 Channel0 #0 1 Channel1 #1 CHSEL2_3 Select Channel 2/3 to Do PDMA Transfer \n 12 1 read-write 0 Channel2 #0 1 Channel3 #1 CHSEL4_5 Select Channel 4/5 to Do PDMA Transfer \n 20 1 read-write 0 Channel4 #0 1 Channel5 #1 PWM_PERIOD0 PWM_PERIOD0 PWM Period Register 0 0x30 read-write n 0x0 0x0 PERIOD PWM Period Register\nUp-Count mode: In this mode, PWM counter counts from 0 to PERIOD, and restarts from 0.\nDown-Count mode: In this mode, PWM counter counts from PERIOD to 0, and restarts from PERIOD.\n 0 16 read-write PWM_PERIOD2 PWM_PERIOD2 PWM Period Register 2 0x38 read-write n 0x0 0x0 PWM_PERIOD4 PWM_PERIOD4 PWM Period Register 4 0x40 read-write n 0x0 0x0 PWM_POEN PWM_POEN PWM Output Enable Register 0xD8 read-write n 0x0 0x0 POENn PWM Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 PWM pin at tri-state 0 1 PWM pin in output mode 1 PWM_POLCTL PWM_POLCTL PWM Pin Polar Inverse Register 0xD4 read-write n 0x0 0x0 PINVn PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output. Each bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 PWM output polar inverse Disabled 0 1 PWM output polar inverse Enabled 1 PWM_RCAPDAT0 PWM_RCAPDAT0 PWM Rising Capture Data Register 0 0x20C read-only n 0x0 0x0 RCAPDAT PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened, the PWM counter value will be saved in this register. 0 16 read-only PWM_RCAPDAT1 PWM_RCAPDAT1 PWM Rising Capture Data Register 1 0x214 read-write n 0x0 0x0 PWM_RCAPDAT2 PWM_RCAPDAT2 PWM Rising Capture Data Register 2 0x21C read-write n 0x0 0x0 PWM_RCAPDAT3 PWM_RCAPDAT3 PWM Rising Capture Data Register 3 0x224 read-write n 0x0 0x0 PWM_RCAPDAT4 PWM_RCAPDAT4 PWM Rising Capture Data Register 4 0x22C read-write n 0x0 0x0 PWM_RCAPDAT5 PWM_RCAPDAT5 PWM Rising Capture Data Register 5 0x234 read-write n 0x0 0x0 PWM_SSCTL PWM_SSCTL PWM Synchronous Start Control Register 0x110 read-write n 0x0 0x0 SSEN0 PWM Synchronous Start Function Enable 0\nWhen synchronous start function is enabled, the PWM_CH0 counter enable bit (CNTEN0) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). \n 0 1 read-write 0 PWM synchronous start function Disabled #0 1 PWM synchronous start function Enabled #1 SSEN2 PWM Synchronous Start Function Enable 2\nWhen synchronous start function is enabled, the PWM_CH2 counter enable bit (CNTEN2) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). \n 2 1 read-write 0 PWM synchronous start function Disabled #0 1 PWM synchronous start function Enabled #1 SSEN4 PWM Synchronous Start Function Enable 4\nWhen synchronous start function is enabled, the PWM_CH4 counter enable bit (CNTEN4) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). \n 4 1 read-write 0 PWM synchronous start function Disabled #0 1 PWM synchronous start function Enabled #1 SSRC PWM Synchronous Start Source Select\n 8 2 read-write 0 Synchronous start source come from PWM0 #00 1 Synchronous start source come from PWM1 #01 2 Synchronous start source come from BPWM0 #10 3 Synchronous start source come from BPWM1 #11 PWM_SSTRG PWM_SSTRG PWM Synchronous Start Trigger Register 0x114 write-only n 0x0 0x0 CNTSEN PWM Counter Synchronous Start Enable (Write Only)\nPMW counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated PWM channel counter synchronous start function is enabled. 0 1 write-only PWM_STATUS PWM_STATUS PWM Status Register 0x120 read-write n 0x0 0x0 ADCTRGn ADC Start of Conversion Status\nEach bit n controls the corresponding PWM channel n.\n 16 6 read-write 0 Indicates no ADC start of conversion trigger event has occurred 0 1 Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit 1 CNTMAX0 Time-base Counter 0 Equal to 0xFFFF Latched Status\n 0 1 read-write 0 indicates the time-base counter never reached its maximum value 0xFFFF #0 1 indicates the time-base counter reached its maximum value, software can write 1 to clear this bit #1 CNTMAX2 Time-base Counter 2 Equal to 0xFFFF Latched Status\n 2 1 read-write 0 indicates the time-base counter never reached its maximum value 0xFFFF #0 1 indicates the time-base counter reached its maximum value, software can write 1 to clear this bit #1 CNTMAX4 Time-base Counter 4 Equal to 0xFFFF Latched Status\n 4 1 read-write 0 indicates the time-base counter never reached its maximum value 0xFFFF #0 1 indicates the time-base counter reached its maximum value, software can write 1 to clear this bit #1 PWM_SWBRK PWM_SWBRK PWM Software Brake Control Register 0xDC write-only n 0x0 0x0 BRKETRGn PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nEach bit n controls the corresponding PWM pair n.\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: These bits are write protected. Refer to SYS_REGLCTL register. 0 3 write-only BRKLTRGn PWM Level Brake Software Trigger (Write Only) (Write Protect)\nEach bit n controls the corresponding PWM pair n.\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: These bits are write protected. Refer to SYS_REGLCTL register. 8 3 write-only PWM_WGCTL0 PWM_WGCTL0 PWM Generation Register 0 0xB0 read-write n 0x0 0x0 PRDPCTL0 PWM Period (Center) Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to (PERIODn+1).\nNote: This bit is center point control when PWM counter operating in up-down counter type. 16 2 read-write 0 Do nothing #00 1 PWM period (center) point output Low #01 2 PWM period (center) point output High #10 3 PWM period (center) point output Toggle #11 PRDPCTL1 PWM Period (Center) Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to (PERIODn+1).\nNote: This bit is center point control when PWM counter operating in up-down counter type. 18 2 read-write 0 Do nothing #00 1 PWM period (center) point output Low #01 2 PWM period (center) point output High #10 3 PWM period (center) point output Toggle #11 PRDPCTL2 PWM Period (Center) Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to (PERIODn+1).\nNote: This bit is center point control when PWM counter operating in up-down counter type. 20 2 read-write 0 Do nothing #00 1 PWM period (center) point output Low #01 2 PWM period (center) point output High #10 3 PWM period (center) point output Toggle #11 PRDPCTL3 PWM Period (Center) Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to (PERIODn+1).\nNote: This bit is center point control when PWM counter operating in up-down counter type. 22 2 read-write 0 Do nothing #00 1 PWM period (center) point output Low #01 2 PWM period (center) point output High #10 3 PWM period (center) point output Toggle #11 PRDPCTL4 PWM Period (Center) Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to (PERIODn+1).\nNote: This bit is center point control when PWM counter operating in up-down counter type. 24 2 read-write 0 Do nothing #00 1 PWM period (center) point output Low #01 2 PWM period (center) point output High #10 3 PWM period (center) point output Toggle #11 PRDPCTL5 PWM Period (Center) Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to (PERIODn+1).\nNote: This bit is center point control when PWM counter operating in up-down counter type. 26 2 read-write 0 Do nothing #00 1 PWM period (center) point output Low #01 2 PWM period (center) point output High #10 3 PWM period (center) point output Toggle #11 ZPCTL0 PWM Zero Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to zero. 0 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 ZPCTL1 PWM Zero Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to zero. 2 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 ZPCTL2 PWM Zero Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to zero. 4 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 ZPCTL3 PWM Zero Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to zero. 6 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 ZPCTL4 PWM Zero Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to zero. 8 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 ZPCTL5 PWM Zero Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to zero. 10 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 PWM_WGCTL1 PWM_WGCTL1 PWM Generation Register 1 0xB4 read-write n 0x0 0x0 CMPDCTL0 PWM Compare Down Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter down count to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 16 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPDCTL1 PWM Compare Down Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter down count to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 18 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPDCTL2 PWM Compare Down Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter down count to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 20 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPDCTL3 PWM Compare Down Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter down count to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 22 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPDCTL4 PWM Compare Down Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter down count to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 24 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPDCTL5 PWM Compare Down Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter down count to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 26 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPUCTL0 PWM Compare Up Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter up count to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 0 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 CMPUCTL1 PWM Compare Up Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter up count to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 2 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 CMPUCTL2 PWM Compare Up Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter up count to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 4 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 CMPUCTL3 PWM Compare Up Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter up count to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 6 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 CMPUCTL4 PWM Compare Up Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter up count to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 8 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 CMPUCTL5 PWM Compare Up Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter up count to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 10 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 PWM1 PWM Register Map PWM 0x0 0x0 0x8 registers n 0x10 0x18 registers n 0x110 0x8 registers n 0x120 0x4 registers n 0x200 0x4C registers n 0x250 0x8 registers n 0x30 0x4 registers n 0x304 0x4 registers n 0x30C 0x4 registers n 0x314 0x4 registers n 0x31C 0x18 registers n 0x38 0x4 registers n 0x40 0x4 registers n 0x50 0x18 registers n 0x70 0xC registers n 0x90 0x4 registers n 0x98 0x4 registers n 0xA0 0x4 registers n 0xB0 0x40 registers n 0xF8 0x8 registers n PWM_ADCTS0 PWM_ADCTS0 PWM Trigger ADC Source Select Register 0 0xF8 read-write n 0x0 0x0 TRGEN0 PWM_CH0 Trigger ADC Enable Bit 7 1 read-write TRGEN1 PWM_CH1 Trigger ADC Enable Bit 15 1 read-write TRGEN2 PWM_CH2 Trigger ADC Enable Bit 23 1 read-write TRGEN3 PWM_CH3 Trigger ADC Enable Bit 31 1 read-write TRGSEL0 PWM_CH0 Trigger ADC Source Select\n 0 4 read-write 0 PWM_CH0 zero point #0000 1 PWM_CH0 period point #0001 2 PWM_CH0 zero or period point #0010 3 PWM_CH0 up-count CMPDAT point #0011 4 PWM_CH0 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM_CH1 up-count CMPDAT point #1000 9 PWM_CH1 down-count CMPDAT point #1001 TRGSEL1 PWM_CH1 Trigger ADC Source Select\n 8 4 read-write 0 PWM_CH0 zero point #0000 1 PWM_CH0 period point #0001 2 PWM_CH0 zero or period point #0010 3 PWM_CH0 up-count CMPDAT point #0011 4 PWM_CH0 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM_CH1 up-count CMPDAT point #1000 9 PWM_CH1 down-count CMPDAT point #1001 TRGSEL2 PWM_CH2 Trigger ADC Source Select\n 16 4 read-write 0 PWM_CH2 zero point #0000 1 PWM_CH2 period point #0001 2 PWM_CH2 zero or period point #0010 3 PWM_CH2 up-count CMPDAT point #0011 4 PWM_CH2 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM_CH3 up-count CMPDAT point #1000 9 PWM_CH3 down-count CMPDAT point #1001 TRGSEL3 PWM_CH3 Trigger ADC Source Select\n 24 4 read-write 0 PWM_CH2 zero point #0000 1 PWM_CH2 period point #0001 2 PWM_CH2 zero or period point #0010 3 PWM_CH2 up-count CMPDAT point #0011 4 PWM_CH2 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM_CH3 up-count CMPDAT point #1000 9 PWM_CH3 down-count CMPDAT point #1001 PWM_ADCTS1 PWM_ADCTS1 PWM Trigger ADC Source Select Register 1 0xFC read-write n 0x0 0x0 TRGEN4 PWM_CH4 Trigger ADC Enable Bit 7 1 read-write TRGEN5 PWM_CH5 Trigger ADC Enable Bit 15 1 read-write TRGSEL4 PWM_CH4 Trigger ADC Source Select\n 0 4 read-write 0 PWM_CH4 zero point #0000 1 PWM_CH4 period point #0001 2 PWM_CH4 zero or period point #0010 3 PWM_CH4 up-count CMPDAT point #0011 4 PWM_CH4 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM_CH5 up-count CMPDAT point #1000 9 PWM_CH5 down-count CMPDAT point #1001 TRGSEL5 PWM_CH5 Trigger ADC Source Select\n 8 4 read-write 0 PWM_CH4 zero point #0000 1 PWM_CH4 period point #0001 2 PWM_CH4 zero or period point #0010 3 PWM_CH4 up-count CMPDAT point #0011 4 PWM_CH4 down-count CMPDAT point #0100 5 Reserved #0101 6 Reserved #0110 7 Reserved #0111 8 PWM_CH5 up-count CMPDAT point #1000 9 PWM_CH5 down-count CMPDAT point #1001 PWM_BNF PWM_BNF PWM Brake Noise Filter Register 0xC0 read-write n 0x0 0x0 BK0SRC Brake 0 Pin Source Select\nFor PWM0 setting:\n 16 1 read-write 0 Brake 0 pin source come from PWM0_BRAKE0.\nBrake 0 pin source come from PWM1_BRAKE0 #0 1 Brake 0 pin source come from PWM1_BRAKE0.\nBrake 0 pin source come from PWM0_BRAKE0 #1 BK1SRC Brake 1 Pin Source Select\nFor PWM0 setting:\n 24 1 read-write 0 Brake 1 pin source come from PWM0_BRAKE1.\nBrake 1 pin source come from PWM1_BRAKE1 #0 1 Brake 1 pin source come from PWM1_BRAKE1.\nBrake 1 pin source come from PWM0_BRAKE1 #1 BRK0FCNT Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT. 4 3 read-write BRK0FCS Brake 0 Edge Detector Filter Clock Selection\n 1 3 read-write 0 Filter clock is HCLK #000 1 Filter clock is HCLK/2 #001 2 Filter clock is HCLK/4 #010 3 Filter clock is HCLK/8 #011 4 Filter clock is HCLK/16 #100 5 Filter clock is HCLK/32 #101 6 Filter clock is HCLK/64 #110 7 Filter clock is HCLK/128 #111 BRK0FEN PWM Brake 0 Noise Filter Enable Bit\n 0 1 read-write 0 Noise filter of PWM Brake 0 Disabled #0 1 Noise filter of PWM Brake 0 Enabled #1 BRK0PINV Brake 0 Pin Inverse\n 7 1 read-write 0 The state of pin PWMx_BRAKE0 is passed to the negative edge detector #0 1 The inversed state of pin PWMx_BRAKE10 is passed to the negative edge detector #1 BRK1FCNT Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. 12 3 read-write BRK1FCS Brake 1 Edge Detector Filter Clock Selection\n 9 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 BRK1FEN PWM Brake 1 Noise Filter Enable Bit\n 8 1 read-write 0 Noise filter of PWM Brake 1 Disabled #0 1 Noise filter of PWM Brake 1 Enabled #1 BRK1PINV Brake 1 Pin Inverse\n 15 1 read-write 0 The state of pin PWMx_BRAKE1 is passed to the negative edge detector #0 1 The inversed state of pin PWMx_BRAKE1 is passed to the negative edge detector #1 PWM_BRKCTL0_1 PWM_BRKCTL0_1 PWM Brake Edge Detect Control Register 0_1 0xC8 read-write n 0x0 0x0 BRKAEVEN PWM Brake Action Select for Even Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register. 16 2 read-write 0 PWM even channel level-detect brake function not affect channel output #00 1 PWM even channel output tri-state when level-detect brake happened #01 2 PWM even channel output low level when level-detect brake happened #10 3 PWM even channel output high level when level-detect brake happened #11 BRKAODD PWM Brake Action Select for Odd Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register. 18 2 read-write 0 PWM odd channel level-detect brake function not affect channel output #00 1 PWM odd channel output tri-state when level-detect brake happened #01 2 PWM odd channel output low level when level-detect brake happened #10 3 PWM odd channel output high level when level-detect brake happened #11 BRKP0EEN Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 4 1 read-write 0 BKP0 pin as edge-detect brake source Disabled #0 1 BKP0 pin as edge-detect brake source Enabled #1 BRKP0LEN Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 12 1 read-write 0 PWMx_BRAKE0 pin as level-detect brake source Disabled #0 1 PWMx_BRAKE0 pin as level-detect brake source Enabled #1 BRKP1EEN Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 5 1 read-write 0 BKP1 pin as edge-detect brake source Disabled #0 1 BKP1 pin as edge-detect brake source Enabled #1 BRKP1LEN Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 13 1 read-write 0 PWMx_BRAKE1 pin as level-detect brake source Disabled #0 1 PWMx_BRAKE1 pin as level-detect brake source Enabled #1 SYSEEN Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 7 1 read-write 0 System Fail condition as edge-detect brake source Disabled #0 1 System Fail condition as edge-detect brake source Enabled #1 SYSLEN Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 15 1 read-write 0 System Fail condition as level-detect brake source Disabled #0 1 System Fail condition as level-detect brake source Enabled #1 PWM_BRKCTL2_3 PWM_BRKCTL2_3 PWM Brake Edge Detect Control Register 2_3 0xCC read-write n 0x0 0x0 PWM_BRKCTL4_5 PWM_BRKCTL4_5 PWM Brake Edge Detect Control Register 4_5 0xD0 read-write n 0x0 0x0 PWM_CAPCTL PWM_CAPCTL PWM Capture Control Register 0x204 read-write n 0x0 0x0 CAPENn Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated 0 1 Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) 1 CAPINVn Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n.\n 8 6 read-write 0 Capture source inverter Disabled 0 1 Capture source inverter Enabled. Reverse the input signal from GPIO 1 FCRLDENn Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n.\n 24 6 read-write 0 Falling capture reload counter Disabled 0 1 Falling capture reload counter Enabled 1 RCRLDENn Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n.\n 16 6 read-write 0 Rising capture reload counter Disabled 0 1 Rising capture reload counter Enabled 1 PWM_CAPIEN PWM_CAPIEN PWM Capture Interrupt Enable Register 0x250 read-write n 0x0 0x0 CAPFIENn PWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\n 8 6 read-write 0 Capture falling edge latch interrupt Disabled 0 1 Capture falling edge latch interrupt Enabled 1 CAPRIENn PWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 Capture rising edge latch interrupt Disabled 0 1 Capture rising edge latch interrupt Enabled 1 PWM_CAPIF PWM_CAPIF PWM Capture Interrupt Flag Register 0x254 read-write n 0x0 0x0 CFLIFn PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\n 8 6 read-write 0 No capture falling latch condition happened 0 1 Capture falling latch condition happened, this flag will be set to high 1 CRLIFn PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 No capture rising latch condition happened 0 1 Capture rising latch condition happened, this flag will be set to high 1 PWM_CAPINEN PWM_CAPINEN PWM Capture Input Enable Register 0x200 read-write n 0x0 0x0 CAPINENn Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0 0 1 PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin 1 PWM_CAPSTS PWM_CAPSTS PWM Capture Status Register 0x208 read-only n 0x0 0x0 CFLIFOVn Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF. 8 6 read-only CRLIFOVn Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF. 0 6 read-only PWM_CLKPSC0_1 PWM_CLKPSC0_1 PWM Clock Pre-scale Register 0_1 0x14 read-write n 0x0 0x0 CLKPSC PWM Counter Clock Pre-scale \nThe clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1). 0 12 read-write PWM_CLKPSC2_3 PWM_CLKPSC2_3 PWM Clock Pre-scale Register 2_3 0x18 read-write n 0x0 0x0 PWM_CLKPSC4_5 PWM_CLKPSC4_5 PWM Clock Pre-scale Register 4_5 0x1C read-write n 0x0 0x0 PWM_CLKSRC PWM_CLKSRC PWM Clock Source Register 0x10 read-write n 0x0 0x0 ECLKSRC0 PWM_CH01 External Clock Source Select\n 0 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 ECLKSRC2 PWM_CH23 External Clock Source Select\n 8 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 ECLKSRC4 PWM_CH45 External Clock Source Select\n 16 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 PWM_CMPBUF0 PWM_CMPBUF0 PWM CMPDAT0 Buffer 0x31C read-only n 0x0 0x0 CMPBUF PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register. 0 16 read-only PWM_CMPBUF1 PWM_CMPBUF1 PWM CMPDAT1 Buffer 0x320 read-write n 0x0 0x0 PWM_CMPBUF2 PWM_CMPBUF2 PWM CMPDAT2 Buffer 0x324 read-write n 0x0 0x0 PWM_CMPBUF3 PWM_CMPBUF3 PWM CMPDAT3 Buffer 0x328 read-write n 0x0 0x0 PWM_CMPBUF4 PWM_CMPBUF4 PWM CMPDAT4 Buffer 0x32C read-write n 0x0 0x0 PWM_CMPBUF5 PWM_CMPBUF5 PWM CMPDAT5 Buffer 0x330 read-write n 0x0 0x0 PWM_CMPDAT0 PWM_CMPDAT0 PWM Comparator Register 0 0x50 read-write n 0x0 0x0 CMP PWM Comparator Register\nCMP use to compare with CNT to generate PWM waveform, interrupt and trigger ADC.\nIn independent mode, PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode, PWM_CMPDAT0, 2, 4 denote as first compared point, and PWM_CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM_CH0 and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5. 0 16 read-write PWM_CMPDAT1 PWM_CMPDAT1 PWM Comparator Register 1 0x54 read-write n 0x0 0x0 PWM_CMPDAT2 PWM_CMPDAT2 PWM Comparator Register 2 0x58 read-write n 0x0 0x0 PWM_CMPDAT3 PWM_CMPDAT3 PWM Comparator Register 3 0x5C read-write n 0x0 0x0 PWM_CMPDAT4 PWM_CMPDAT4 PWM Comparator Register 4 0x60 read-write n 0x0 0x0 PWM_CMPDAT5 PWM_CMPDAT5 PWM Comparator Register 5 0x64 read-write n 0x0 0x0 PWM_CNT0 PWM_CNT0 PWM Counter Register 0 0x90 read-only n 0x0 0x0 CNT PWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter. 0 16 read-only DIRF PWM Direction Indicator Flag (Read Only)\n 16 1 read-only 0 Counter is Down count #0 1 Counter is UP count #1 PWM_CNT2 PWM_CNT2 PWM Counter Register 2 0x98 read-write n 0x0 0x0 PWM_CNT4 PWM_CNT4 PWM Counter Register 4 0xA0 read-write n 0x0 0x0 PWM_CNTCLR PWM_CNTCLR PWM Clear Counter Register 0x24 read-write n 0x0 0x0 CNTCLR0 Clear PWM Counter Control Bit 0\nIt is automatically cleared by hardware.\n 0 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0000H #1 CNTCLR2 Clear PWM Counter Control Bit 2\nIt is automatically cleared by hardware.\n 2 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0000H #1 CNTCLR4 Clear PWM Counter Control Bit 4\nIt is automatically cleared by hardware.\n 4 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0000H #1 PWM_CNTEN PWM_CNTEN PWM Counter Enable Register 0x20 read-write n 0x0 0x0 CNTEN0 PWM Counter Enable 0\n 0 1 read-write 0 PWM Counter and clock prescaler Stop Running #0 1 PWM Counter and clock prescaler Start Running #1 CNTEN2 PWM Counter Enable 2\n 2 1 read-write 0 PWM Counter and clock prescaler Stop Running #0 1 PWM Counter and clock prescaler Start Running #1 CNTEN4 PWM Counter Enable 4\n 4 1 read-write 0 PWM Counter and clock prescaler Stop Running #0 1 PWM Counter and clock prescaler Start Running #1 PWM_CTL0 PWM_CTL0 PWM Control Register 0 0x0 read-write n 0x0 0x0 CTRLDn Center Load Enable Bits\n \nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 0 1 read-write 0 Center Lodaing mode is disable for corresponding PWM channel n #0 1 Center Lodaing mode is enable for corresponding PWM channel n #1 DBGHALT ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 30 1 read-write 0 ICE debug mode counter halt disable #0 1 ICE debug mode counter halt enable #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable (Write Protect)\nPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement affects PWM output #0 1 ICE debug mode acknowledgement disabled #1 IMMLDENn Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 16 1 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit #0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT #1 PWM_CTL1 PWM_CTL1 PWM Control Register 1 0x4 read-write n 0x0 0x0 CNTTYPE0 PWM Counter Behavior Type 0\nThe two bits control channel1 and channel0\n 0 2 read-write 0 Up counter type (supports in capture mode) #00 1 Down count type (supports in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 CNTTYPE2 PWM Counter Behavior Type 2\nThe two bits control channel3 and channel2\n 4 2 read-write 0 Up counter type (supports in capture mode) #00 1 Down count type (supports in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 CNTTYPE4 PWM Counter Behavior Type 4\nThe two bits control channel5 and channel4\n 8 2 read-write 0 Up counter type (supports in capture mode) #00 1 Down count type (supports in capture mode) #01 2 Up-down counter type #10 3 Reserved #11 PWMMODEn PWM Mode\nEach bit n controls the corresponding PWM channel n.\nNote: When operating in group function, these bits must all set to the same mode. 24 3 read-write 0 PWM independent mode 0 1 PWM complementary mode 1 PWM_DTCTL0_1 PWM_DTCTL0_1 PWM Dead-time Control Register 0_1 0x70 read-write n 0x0 0x0 DTCKSEL Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 24 1 read-write 0 Dead-time clock source from PWM_CLK #0 1 Dead-time clock source from prescaler output #1 DTCNT Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: These bits are write protected. Refer to SYS_REGLCTL register. 0 12 read-write DTEN Enable Dead-time Insertion for PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 16 1 read-write 0 Dead-time insertion Disabled on the pin pair #0 1 Dead-time insertion Enabled on the pin pair #1 PWM_DTCTL2_3 PWM_DTCTL2_3 PWM Dead-time Control Register 2_3 0x74 read-write n 0x0 0x0 PWM_DTCTL4_5 PWM_DTCTL4_5 PWM Dead-time Control Register 4_5 0x78 read-write n 0x0 0x0 PWM_FAILBRK PWM_FAILBRK PWM System Fail Brake Control Register 0xC4 read-write n 0x0 0x0 BODBRKEN Brown-out Detection Trigger PWM Brake Function 0 Enable Bit\n 1 1 read-write 0 Brake Function triggered by BOD Disabled #0 1 Brake Function triggered by BOD Enabled #1 CORBRKEN Core Lockup Detection Trigger PWM Brake Function 0 Enable Bit\n 3 1 read-write 0 Brake Function triggered by Core lockup detection Disabled #0 1 Brake Function triggered by Core lockup detection Enabled #1 CSSBRKEN Clock Security System Detection Trigger PWM Brake Function 0 Enable Bit\n 0 1 read-write 0 Brake Function triggered by CSS detection Disabled #0 1 Brake Function triggered by CSS detection Enabled #1 PWM_FCAPDAT0 PWM_FCAPDAT0 PWM Falling Capture Data Register 0 0x210 read-only n 0x0 0x0 FCAPDAT PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened, the PWM counter value will be saved in this register. 0 16 read-only PWM_FCAPDAT1 PWM_FCAPDAT1 PWM Falling Capture Data Register 1 0x218 read-write n 0x0 0x0 PWM_FCAPDAT2 PWM_FCAPDAT2 PWM Falling Capture Data Register 2 0x220 read-write n 0x0 0x0 PWM_FCAPDAT3 PWM_FCAPDAT3 PWM Falling Capture Data Register 3 0x228 read-write n 0x0 0x0 PWM_FCAPDAT4 PWM_FCAPDAT4 PWM Falling Capture Data Register 4 0x230 read-write n 0x0 0x0 PWM_FCAPDAT5 PWM_FCAPDAT5 PWM Falling Capture Data Register 5 0x238 read-write n 0x0 0x0 PWM_INTEN0 PWM_INTEN0 PWM Interrupt Enable Register 0 0xE0 read-write n 0x0 0x0 CMPDIENn PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. 24 6 read-write 0 Compare down count interrupt Disabled 0 1 Compare down count interrupt Enabled 1 CMPUIENn PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. 16 6 read-write 0 Compare up count interrupt Disabled 0 1 Compare up count interrupt Enabled 1 PIEN0 PWM Period Point Interrupt Enable 0\nNote: When counter type is up-down, period point means center point. 8 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN2 PWM Period Point Interrupt Enable 2\nNote: When counter type is up-down, period point means center point. 10 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN4 PWM Period Point Interrupt Enable 4\nNote: When counter type is up-down, period point means center point. 12 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 ZIEN0 PWM Zero Point Interrupt Enable 0\nNote: Odd channels will read always 0 at complementary mode. 0 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN2 PWM Zero Point Interrupt Enable 2\nNote: Odd channels will read always 0 at complementary mode. 2 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN4 PWM Zero Point Interrupt Enable 4\nNote: Odd channels will read always 0 at complementary mode. 4 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 PWM_INTEN1 PWM_INTEN1 PWM Interrupt Enable Register 1 0xE4 read-write n 0x0 0x0 BRKEIEN0_1 PWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 Edge-detect Brake interrupt for channel0/1 Disabled #0 1 Edge-detect Brake interrupt for channel0/1 Enabled #1 BRKEIEN2_3 PWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 Edge-detect Brake interrupt for channel2/3 Disabled #0 1 Edge-detect Brake interrupt for channel2/3 Enabled #1 BRKEIEN4_5 PWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bitr is write protected. Refer to SYS_REGLCTL register. 2 1 read-write 0 Edge-detect Brake interrupt for channel4/5 Disabled #0 1 Edge-detect Brake interrupt for channel4/5 Enabled #1 BRKLIEN0_1 PWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 Level-detect Brake interrupt for channel0/1 Disabled #0 1 Level-detect Brake interrupt for channel0/1 Enabled #1 BRKLIEN2_3 PWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 Level-detect Brake interrupt for channel2/3 Disabled #0 1 Level-detect Brake interrupt for channel2/3 Enabled #1 BRKLIEN4_5 PWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 10 1 read-write 0 Level-detect Brake interrupt for channel4/5 Disabled #0 1 Level-detect Brake interrupt for channel4/5 Enabled #1 PWM_INTSTS0 PWM_INTSTS0 PWM Interrupt Flag Register 0 0xE8 read-write n 0x0 0x0 CMPDIFn PWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. 24 6 read-write CMPUIFn PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. 16 6 read-write PIF0 PWM Period Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches PWM_PERIOD0, software can write 1 to clear this bit to zero. 8 1 read-write PIF2 PWM Period Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches PWM_PERIOD2, software can write 1 to clear this bit to zero. 10 1 read-write PIF4 PWM Period Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches PWM_PERIOD4, software can write 1 to clear this bit to zero. 12 1 read-write ZIF0 PWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches zero, software can write 1 to clear this bit to zero. 0 1 read-write ZIF2 PWM Zero Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches zero, software can write 1 to clear this bit to zero. 2 1 read-write ZIF4 PWM Zero Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches zero, software can write 1 to clear this bit to zero. 4 1 read-write PWM_INTSTS1 PWM_INTSTS1 PWM Interrupt Flag Register 1 0xEC read-write n 0x0 0x0 BRKEIF0 PWM Channel0 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 PWM channel0 edge-detect brake event do not happened #0 1 When PWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF1 PWM Channel1 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 PWM channel1 edge-detect brake event do not happened #0 1 When PWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF2 PWM Channel2 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 2 1 read-write 0 PWM channel2 edge-detect brake event do not happened #0 1 When PWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF3 PWM Channel3 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 3 1 read-write 0 PWM channel3 edge-detect brake event do not happened #0 1 When PWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF4 PWM Channel4 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 4 1 read-write 0 PWM channel4 edge-detect brake event do not happened #0 1 When PWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF5 PWM Channel5 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 5 1 read-write 0 PWM channel5 edge-detect brake event do not happened #0 1 When PWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKESTS0 PWM Channel0 Edge-detect Brake Status\n 16 1 read-write 0 PWM channel0 edge-detect brake state is released #0 1 When PWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state, writing 1 to clear #1 BRKESTS1 PWM Channel1 Edge-detect Brake Status\n 17 1 read-write 0 PWM channel1 edge-detect brake state is released #0 1 When PWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state, writing 1 to clear #1 BRKESTS2 PWM Channel2 Edge-detect Brake Status\n 18 1 read-write 0 PWM channel2 edge-detect brake state is released #0 1 When PWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state, writing 1 to clear #1 BRKESTS3 PWM Channel3 Edge-detect Brake Status\n 19 1 read-write 0 PWM channel3 edge-detect brake state is released #0 1 When PWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state, writing 1 to clear #1 BRKESTS4 PWM Channel4 Edge-detect Brake Status\n 20 1 read-write 0 PWM channel4 edge-detect brake state is released #0 1 When PWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state, writing 1 to clear #1 BRKESTS5 PWM Channel5 Edge-detect Brake Status\n 21 1 read-write 0 PWM channel5 edge-detect brake state is released #0 1 When PWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state, writing 1 to clear #1 BRKLIF0 PWM Channel0 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 PWM channel0 level-detect brake event do not happened #0 1 When PWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF1 PWM Channel1 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 PWM channel1 level-detect brake event do not happened #0 1 When PWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF2 PWM Channel2 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 10 1 read-write 0 PWM channel2 level-detect brake event do not happened #0 1 When PWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF3 PWM Channel3 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 11 1 read-write 0 PWM channel3 level-detect brake event do not happened #0 1 When PWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF4 PWM Channel4 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 12 1 read-write 0 PWM channel4 level-detect brake event do not happened #0 1 When PWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF5 PWM Channel5 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 13 1 read-write 0 PWM channel5 level-detect brake event do not happened #0 1 When PWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLSTS0 PWM Channel0 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 24 1 read-only 0 PWM channel0 level-detect brake state is released #0 1 When PWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state #1 BRKLSTS1 PWM Channel1 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 25 1 read-only 0 PWM channel1 level-detect brake state is released #0 1 When PWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state #1 BRKLSTS2 PWM Channel2 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 26 1 read-only 0 PWM channel2 level-detect brake state is released #0 1 When PWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state #1 BRKLSTS3 PWM Channel3 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 27 1 read-only 0 PWM channel3 level-detect brake state is released #0 1 When PWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state #1 BRKLSTS4 PWM Channel4 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 28 1 read-only 0 PWM channel4 level-detect brake state is released #0 1 When PWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state #1 BRKLSTS5 PWM Channel5 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 29 1 read-only 0 PWM channel5 level-detect brake state is released #0 1 When PWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state #1 PWM_MSK PWM_MSK PWM Mask Data Register 0xBC read-write n 0x0 0x0 MSKDATn PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 Output logic low to PWMn 0 1 Output logic high to PWMn 1 PWM_MSKEN PWM_MSKEN PWM Mask Enable Register 0xB8 read-write n 0x0 0x0 MSKENn PWM Mask Enable Bits\nEach bit n controls the corresponding PWM channel n.\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. \n 0 6 read-write 0 PWM output signal is non-masked 0 1 PWM output signal is masked and output MSKDATn data 1 PWM_PBUF0 PWM_PBUF0 PWM PERIOD0 Buffer 0x304 read-only n 0x0 0x0 PBUF PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register. 0 16 read-only PWM_PBUF2 PWM_PBUF2 PWM PERIOD2 Buffer 0x30C read-write n 0x0 0x0 PWM_PBUF4 PWM_PBUF4 PWM PERIOD4 Buffer 0x314 read-write n 0x0 0x0 PWM_PDMACAP0_1 PWM_PDMACAP0_1 PWM Capture Channel 01 PDMA Register 0x240 read-only n 0x0 0x0 CAPBUF PWM Capture PDMA Register (Read Only)\nThis register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA. 0 16 read-only PWM_PDMACAP2_3 PWM_PDMACAP2_3 PWM Capture Channel 23 PDMA Register 0x244 read-write n 0x0 0x0 PWM_PDMACAP4_5 PWM_PDMACAP4_5 PWM Capture Channel 45 PDMA Register 0x248 read-write n 0x0 0x0 PWM_PDMACTL PWM_PDMACTL PWM PDMA Control Register 0x23C read-write n 0x0 0x0 CAPMOD0_1 Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer \n 1 2 read-write 0 Reserved #00 1 PWM_RCAPDAT0/1 #01 2 PWM_FCAPDAT0/1 #10 3 Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1 #11 CAPMOD2_3 Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer \n 9 2 read-write 0 Reserved #00 1 PWM_RCAPDAT2/3 #01 2 PWM_FCAPDAT2/3 #10 3 Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3 #11 CAPMOD4_5 Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer \n 17 2 read-write 0 Reserved #00 1 PWM_RCAPDAT4/5 #01 2 PWM_FCAPDAT4/5 #10 3 Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5 #11 CAPORD0_1 Capture Channel 0/1 Rising/Falling Order \n 3 1 read-write 0 PWM_FCAPDAT0/1 is the first captured data to memory #0 1 PWM_RCAPDAT0/1 is the first captured data to memory #1 CAPORD2_3 Capture Channel 2/3 Rising/Falling Order \n 11 1 read-write 0 PWM_FCAPDAT2/3 is the first captured data to memory #0 1 PWM_RCAPDAT2/3 is the first captured data to memory #1 CAPORD4_5 Capture Channel 4/5 Rising/Falling Order \n 19 1 read-write 0 PWM_FCAPDAT4/5 is the first captured data to memory #0 1 PWM_RCAPDAT4/5 is the first captured data to memory #1 CHEN0_1 Channel 0/1 PDMA Enable Bit\n 0 1 read-write 0 Channel 0/1 PDMA function Disabled #0 1 Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory #1 CHEN2_3 Channel 2/3 PDMA Enable Bit\n 8 1 read-write 0 Channel 2/3 PDMA function Disabled #0 1 Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory #1 CHEN4_5 Channel 4/5 PDMA Enable Bit\n 16 1 read-write 0 Channel 4/5 PDMA function Disabled #0 1 Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory #1 CHSEL0_1 Select Channel 0/1 to Do PDMA Transfer \n 4 1 read-write 0 Channel0 #0 1 Channel1 #1 CHSEL2_3 Select Channel 2/3 to Do PDMA Transfer \n 12 1 read-write 0 Channel2 #0 1 Channel3 #1 CHSEL4_5 Select Channel 4/5 to Do PDMA Transfer \n 20 1 read-write 0 Channel4 #0 1 Channel5 #1 PWM_PERIOD0 PWM_PERIOD0 PWM Period Register 0 0x30 read-write n 0x0 0x0 PERIOD PWM Period Register\nUp-Count mode: In this mode, PWM counter counts from 0 to PERIOD, and restarts from 0.\nDown-Count mode: In this mode, PWM counter counts from PERIOD to 0, and restarts from PERIOD.\n 0 16 read-write PWM_PERIOD2 PWM_PERIOD2 PWM Period Register 2 0x38 read-write n 0x0 0x0 PWM_PERIOD4 PWM_PERIOD4 PWM Period Register 4 0x40 read-write n 0x0 0x0 PWM_POEN PWM_POEN PWM Output Enable Register 0xD8 read-write n 0x0 0x0 POENn PWM Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 PWM pin at tri-state 0 1 PWM pin in output mode 1 PWM_POLCTL PWM_POLCTL PWM Pin Polar Inverse Register 0xD4 read-write n 0x0 0x0 PINVn PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output. Each bit n controls the corresponding PWM channel n.\n 0 6 read-write 0 PWM output polar inverse Disabled 0 1 PWM output polar inverse Enabled 1 PWM_RCAPDAT0 PWM_RCAPDAT0 PWM Rising Capture Data Register 0 0x20C read-only n 0x0 0x0 RCAPDAT PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened, the PWM counter value will be saved in this register. 0 16 read-only PWM_RCAPDAT1 PWM_RCAPDAT1 PWM Rising Capture Data Register 1 0x214 read-write n 0x0 0x0 PWM_RCAPDAT2 PWM_RCAPDAT2 PWM Rising Capture Data Register 2 0x21C read-write n 0x0 0x0 PWM_RCAPDAT3 PWM_RCAPDAT3 PWM Rising Capture Data Register 3 0x224 read-write n 0x0 0x0 PWM_RCAPDAT4 PWM_RCAPDAT4 PWM Rising Capture Data Register 4 0x22C read-write n 0x0 0x0 PWM_RCAPDAT5 PWM_RCAPDAT5 PWM Rising Capture Data Register 5 0x234 read-write n 0x0 0x0 PWM_SSCTL PWM_SSCTL PWM Synchronous Start Control Register 0x110 read-write n 0x0 0x0 SSEN0 PWM Synchronous Start Function Enable 0\nWhen synchronous start function is enabled, the PWM_CH0 counter enable bit (CNTEN0) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). \n 0 1 read-write 0 PWM synchronous start function Disabled #0 1 PWM synchronous start function Enabled #1 SSEN2 PWM Synchronous Start Function Enable 2\nWhen synchronous start function is enabled, the PWM_CH2 counter enable bit (CNTEN2) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). \n 2 1 read-write 0 PWM synchronous start function Disabled #0 1 PWM synchronous start function Enabled #1 SSEN4 PWM Synchronous Start Function Enable 4\nWhen synchronous start function is enabled, the PWM_CH4 counter enable bit (CNTEN4) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). \n 4 1 read-write 0 PWM synchronous start function Disabled #0 1 PWM synchronous start function Enabled #1 SSRC PWM Synchronous Start Source Select\n 8 2 read-write 0 Synchronous start source come from PWM0 #00 1 Synchronous start source come from PWM1 #01 2 Synchronous start source come from BPWM0 #10 3 Synchronous start source come from BPWM1 #11 PWM_SSTRG PWM_SSTRG PWM Synchronous Start Trigger Register 0x114 write-only n 0x0 0x0 CNTSEN PWM Counter Synchronous Start Enable (Write Only)\nPMW counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated PWM channel counter synchronous start function is enabled. 0 1 write-only PWM_STATUS PWM_STATUS PWM Status Register 0x120 read-write n 0x0 0x0 ADCTRGn ADC Start of Conversion Status\nEach bit n controls the corresponding PWM channel n.\n 16 6 read-write 0 Indicates no ADC start of conversion trigger event has occurred 0 1 Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit 1 CNTMAX0 Time-base Counter 0 Equal to 0xFFFF Latched Status\n 0 1 read-write 0 indicates the time-base counter never reached its maximum value 0xFFFF #0 1 indicates the time-base counter reached its maximum value, software can write 1 to clear this bit #1 CNTMAX2 Time-base Counter 2 Equal to 0xFFFF Latched Status\n 2 1 read-write 0 indicates the time-base counter never reached its maximum value 0xFFFF #0 1 indicates the time-base counter reached its maximum value, software can write 1 to clear this bit #1 CNTMAX4 Time-base Counter 4 Equal to 0xFFFF Latched Status\n 4 1 read-write 0 indicates the time-base counter never reached its maximum value 0xFFFF #0 1 indicates the time-base counter reached its maximum value, software can write 1 to clear this bit #1 PWM_SWBRK PWM_SWBRK PWM Software Brake Control Register 0xDC write-only n 0x0 0x0 BRKETRGn PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nEach bit n controls the corresponding PWM pair n.\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: These bits are write protected. Refer to SYS_REGLCTL register. 0 3 write-only BRKLTRGn PWM Level Brake Software Trigger (Write Only) (Write Protect)\nEach bit n controls the corresponding PWM pair n.\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: These bits are write protected. Refer to SYS_REGLCTL register. 8 3 write-only PWM_WGCTL0 PWM_WGCTL0 PWM Generation Register 0 0xB0 read-write n 0x0 0x0 PRDPCTL0 PWM Period (Center) Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to (PERIODn+1).\nNote: This bit is center point control when PWM counter operating in up-down counter type. 16 2 read-write 0 Do nothing #00 1 PWM period (center) point output Low #01 2 PWM period (center) point output High #10 3 PWM period (center) point output Toggle #11 PRDPCTL1 PWM Period (Center) Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to (PERIODn+1).\nNote: This bit is center point control when PWM counter operating in up-down counter type. 18 2 read-write 0 Do nothing #00 1 PWM period (center) point output Low #01 2 PWM period (center) point output High #10 3 PWM period (center) point output Toggle #11 PRDPCTL2 PWM Period (Center) Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to (PERIODn+1).\nNote: This bit is center point control when PWM counter operating in up-down counter type. 20 2 read-write 0 Do nothing #00 1 PWM period (center) point output Low #01 2 PWM period (center) point output High #10 3 PWM period (center) point output Toggle #11 PRDPCTL3 PWM Period (Center) Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to (PERIODn+1).\nNote: This bit is center point control when PWM counter operating in up-down counter type. 22 2 read-write 0 Do nothing #00 1 PWM period (center) point output Low #01 2 PWM period (center) point output High #10 3 PWM period (center) point output Toggle #11 PRDPCTL4 PWM Period (Center) Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to (PERIODn+1).\nNote: This bit is center point control when PWM counter operating in up-down counter type. 24 2 read-write 0 Do nothing #00 1 PWM period (center) point output Low #01 2 PWM period (center) point output High #10 3 PWM period (center) point output Toggle #11 PRDPCTL5 PWM Period (Center) Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to (PERIODn+1).\nNote: This bit is center point control when PWM counter operating in up-down counter type. 26 2 read-write 0 Do nothing #00 1 PWM period (center) point output Low #01 2 PWM period (center) point output High #10 3 PWM period (center) point output Toggle #11 ZPCTL0 PWM Zero Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to zero. 0 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 ZPCTL1 PWM Zero Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to zero. 2 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 ZPCTL2 PWM Zero Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to zero. 4 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 ZPCTL3 PWM Zero Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to zero. 6 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 ZPCTL4 PWM Zero Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to zero. 8 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 ZPCTL5 PWM Zero Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to zero. 10 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 PWM_WGCTL1 PWM_WGCTL1 PWM Generation Register 1 0xB4 read-write n 0x0 0x0 CMPDCTL0 PWM Compare Down Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter down count to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 16 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPDCTL1 PWM Compare Down Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter down count to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 18 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPDCTL2 PWM Compare Down Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter down count to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 20 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPDCTL3 PWM Compare Down Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter down count to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 22 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPDCTL4 PWM Compare Down Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter down count to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 24 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPDCTL5 PWM Compare Down Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter down count to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 26 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPUCTL0 PWM Compare Up Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter up count to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 0 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 CMPUCTL1 PWM Compare Up Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter up count to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 2 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 CMPUCTL2 PWM Compare Up Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter up count to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 4 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 CMPUCTL3 PWM Compare Up Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter up count to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 6 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 CMPUCTL4 PWM Compare Up Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter up count to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 8 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 CMPUCTL5 PWM Compare Up Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter up count to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 10 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 SCS SYST_NVIC_SCS Register Map SYST_NVIC_SCS 0x0 0x10 0xC registers n 0x100 0x4 registers n 0x180 0x4 registers n 0x200 0x4 registers n 0x280 0x4 registers n 0x400 0x20 registers n 0xD00 0x8 registers n 0xD0C 0x8 registers n 0xD1C 0x8 registers n AIRCR SCS_AIRCR Application Interrupt and Reset Control Register 0xD0C read-write n 0x0 0x0 SYSRESETREQ System Reset Request\nWriting this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested.\nThe bit is a write only bit and self-clears as part of the reset sequence. 2 1 read-write VECTCLRACTIVE Exception Active Status Clear Bit\nReserved for debug use. When writing to the register, user must write 0 to this bit, otherwise behavior is unpredictable. 1 1 read-write VECTORKEY Register Access Key\nWrite Operation:\nWhen writing to this register, the VECTORKEY field need to be set to 0x05FA, otherwise the write operation would be ignored. The VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status.\nRead Operation:\nRead as 0xFA05. 16 16 read-write CPUID SCS_CPUID CPUID Register 0xD00 read-only n 0x0 0x0 IMPLEMENTER Implementer Code Assigned by ARM\n 24 8 read-only PART Architecture of the Processor\nRead as 0xC for ARMv6-M parts 16 4 read-only PARTNO Part Number of the Processor\nRead as 0xC20. 4 12 read-only REVISION Revision Number\nRead as 0x0 0 4 read-only ICSR SCS_ICSR Interrupt Control and State Register 0xD04 read-write n 0x0 0x0 ISRPENDING Interrupt Pending Flag, Excluding NMI and Faults:\nThis bit is read only. 22 1 read-write 0 Interrupt not pending #0 1 Interrupt pending #1 ISRPREEMPT If Set, a Pending Exception Will Be Serviced on Exit From the Debug Halt State\nThis bit is read only. 23 1 read-write NMIPENDSET NMI Set-pending Bit\nWrite Operation:\nBecause NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler. 31 1 read-write 0 No effect.\nNMI exception not pending #0 1 Changes NMI exception state to pending.\nNMI exception pending #1 PENDSTCLR SysTick Exception Clear-pending Bit\nWrite Operation:\nThis is a write only bit. When you want to clear PENDST bit, you must "write 0 to PENDSTSET and write 1 to PENDSTCLR" at the same time. 25 1 read-write 0 No effect #0 1 Removes the pending state from the SysTick exception #1 PENDSTSET SysTick Exception Set-pending Bit\nWrite Operation:\n 26 1 read-write 0 No effect.\nSysTick exception is not pending #0 1 Changes SysTick exception state to pending.\nSysTick exception is pending #1 PENDSVCLR PendSV Clear-pending Bit\nWrite Operation:\nThis is a write only bit. When you want to clear PENDSV bit, you must "write 0 to PENDSVSET and write 1 to PENDSVCLR" at the same time. 27 1 read-write 0 No effect #0 1 Removes the pending state from the PendSV exception #1 PENDSVSET PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending. 28 1 read-write 0 No effect.\nPendSV exception is not pending #0 1 Changes PendSV exception state to pending.\nPendSV exception is pending #1 VECTACTIVE Contains the Active Exception Number\n 0 6 read-write 0 Thread mode 0 VECTPENDING Indicates the Exception Number of the Highest Priority Pending Enabled Exception:\n 12 6 read-write 0 No pending exceptions 0 NVIC_ICER NVIC_ICER IRQ0 ~ IRQ31 Clear-enable Control Register 0x180 read-write n 0x0 0x0 CLRENA Interrupt Disable Bits\nDisable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite Operation:\nRead value indicates the current enable status. 0 32 read-write 0 No effect.\nAssociated interrupt status is Disabled 0 1 Write 1 to disable associated interrupt.\nAssociated interrupt status is Enabled 1 NVIC_ICPR NVIC_ICPR IRQ0 ~ IRQ31 Clear-pending Control Register 0x280 read-write n 0x0 0x0 CLRPEND Clear Interrupt Pending Register\nWrite Operation:\nRead value indicates the current pending status. 0 32 read-write 0 No effect.\nAssociated interrupt in not in pending status 0 1 Write 1 to clear pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nAssociated interrupt is in pending status 1 NVIC_IPR0 NVIC_IPR0 IRQ0 ~ IRQ3 Priority Control Register 0x400 read-write n 0x0 0x0 PRI_0 Priority of IRQ0\n"0" denotes the highest priority and "3" denotes the lowest priority. 6 2 read-write PRI_1 Priority of IRQ1\n"0" denotes the highest priority and "3" denotes the lowest priority. 14 2 read-write PRI_2 Priority of IRQ2\n"0" denotes the highest priority and "3" denotes the lowest priority. 22 2 read-write PRI_3 Priority of IRQ3\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write NVIC_IPR1 NVIC_IPR1 IRQ4 ~ IRQ7 Priority Control Register 0x404 read-write n 0x0 0x0 PRI_4 Priority of IRQ4\n"0" denotes the highest priority and "3" denotes the lowest priority. 6 2 read-write PRI_5 Priority of IRQ5\n"0" denotes the highest priority and "3" denotes the lowest priority. 14 2 read-write PRI_6 Priority of IRQ6\n"0" denotes the highest priority and "3" denotes the lowest priority. 22 2 read-write PRI_7 Priority of IRQ7\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write NVIC_IPR2 NVIC_IPR2 IRQ8 ~ IRQ11 Priority Control Register 0x408 read-write n 0x0 0x0 PRI_10 Priority of IRQ10\n"0" denotes the highest priority and "3" denotes the lowest priority. 22 2 read-write PRI_11 Priority of IRQ11\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write PRI_8 Priority of IRQ8\n"0" denotes the highest priority and "3" denotes the lowest priority. 6 2 read-write PRI_9 Priority of IRQ9\n"0" denotes the highest priority and "3" denotes the lowest priority. 14 2 read-write NVIC_IPR3 NVIC_IPR3 IRQ12 ~ IRQ15 Priority Control Register 0x40C read-write n 0x0 0x0 PRI_12 Priority of IRQ12\n"0" denotes the highest priority and "3" denotes the lowest priority. 6 2 read-write PRI_13 Priority of IRQ13\n"0" denotes the highest priority and "3" denotes the lowest priority 14 2 read-write PRI_14 Priority of IRQ14\n"0" denotes the highest priority and "3" denotes the lowest priority. 22 2 read-write PRI_15 Priority of IRQ15\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write NVIC_IPR4 NVIC_IPR4 IRQ16 ~ IRQ19 Priority Control Register 0x410 read-write n 0x0 0x0 PRI_16 Priority of IRQ16\n"0" denotes the highest priority and "3" denotes the lowest priority. 6 2 read-write PRI_17 Priority of IRQ17\n"0" denotes the highest priority and "3" denotes the lowest priority. 14 2 read-write PRI_18 Priority of IRQ18\n"0" denotes the highest priority and "3" denotes the lowest priority. 22 2 read-write PRI_19 Priority of IRQ19\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write NVIC_IPR5 NVIC_IPR5 IRQ20 ~ IRQ23 Priority Control Register 0x414 read-write n 0x0 0x0 PRI_20 Priority of IRQ20\n"0" denotes the highest priority and "3" denotes the lowest priority. 6 2 read-write PRI_21 Priority of IRQ21\n"0" denotes the highest priority and "3" denotes the lowest priority 14 2 read-write PRI_22 Priority of IRQ22\n"0" denotes the highest priority and "3" denotes the lowest priority. 22 2 read-write PRI_23 Priority of IRQ23\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write NVIC_IPR6 NVIC_IPR6 IRQ24 ~ IRQ27 Priority Control Register 0x418 read-write n 0x0 0x0 PRI_24 Priority of IRQ24\n"0" denotes the highest priority and "3" denotes the lowest priority. 6 2 read-write PRI_25 Priority of IRQ25\n"0" denotes the highest priority and "3" denotes the lowest priority. 14 2 read-write PRI_26 Priority of IRQ26\n"0" denotes the highest priority and "3" denotes the lowest priority. 22 2 read-write PRI_27 Priority of IRQ27\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write NVIC_IPR7 NVIC_IPR7 IRQ28 ~ IRQ31 Priority Control Register 0x41C read-write n 0x0 0x0 PRI_28 Priority of IRQ28\n"0" denotes the highest priority and "3" denotes the lowest priority. 6 2 read-write PRI_29 Priority of IRQ29\n"0" denotes the highest priority and "3" denotes the lowest priority. 14 2 read-write PRI_30 Priority of IRQ30\n"0" denotes the highest priority and "3" denotes the lowest priority. 22 2 read-write PRI_31 Priority of IRQ31\n"0" denotes the highest priority and "3" denotes the lowest priority. 30 2 read-write NVIC_ISER NVIC_ISER IRQ0 ~ IRQ31 Set-enable Control Register 0x100 read-write n 0x0 0x0 SETENA Interrupt Enable Register\nEnable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite Operation:\nRead value indicates the current enable status. 0 32 read-write 0 No effect.\nAssociated interrupt status is Disabled 0 1 Write 1 to enable associated interrupt.\nAssociated interrupt status is Enabled 1 NVIC_ISPR NVIC_ISPR IRQ0 ~ IRQ31 Set-pending Control Register 0x200 read-write n 0x0 0x0 SETPEND Set Interrupt Pending Register\nWrite Operation:\nRead value indicates the current pending status. 0 32 read-write 0 No effect.\nAssociated interrupt in not in pending status 0 1 Write 1 to set pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nAssociated interrupt is in pending status 1 SCR SCS_SCR System Control Register 0xD10 read-write n 0x0 0x0 SEVONPEND Send Event on Pending Bit\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event. 4 1 read-write 0 Only enabled interrupts or events can wake up the processor, disabled interrupts are excluded #0 1 Enabled events and all interrupts, including disabled interrupts, can wake up the processor #1 SLEEPDEEP Processor Deep Sleep and Sleep Mode Selection\nControls whether the processor uses sleep or deep sleep as its low power mode:\n 2 1 read-write 0 Sleep mode #0 1 Deep Sleep mode #1 SLEEPONEXIT Sleep-on-exit Enable Bit\nThis bit indicates sleep-on-exit when returning from Handler mode to Thread mode.\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.. 1 1 read-write 0 Do not sleep when returning to Thread mode #0 1 Enter Sleep or Deep Sleep when returning from ISR to Thread mode #1 SHPR2 SCS_SHPR2 System Handler Priority Register 2 0xD1C read-write n 0x0 0x0 PRI_11 Priority of System Handler 11 - SVCall\n"0" denotes the highest priority and "3" denotes the lowest priority 30 2 read-write SHPR3 SCS_SHPR3 System Handler Priority Register 3 0xD20 read-write n 0x0 0x0 PRI_14 Priority of System Handler 14 - PendSV\n"0" denotes the highest priority and "3" denotes the lowest priority 22 2 read-write PRI_15 Priority of System Handler 15 - SysTick\n"0" denotes the highest priority and "3" denotes the lowest priority 30 2 read-write SYST_CTRL SYST_CTRL SysTick Control and Status Register 0x10 read-write n 0x0 0x0 CLKSRC System Tick Clock Source Selection\n 2 1 read-write 0 Clock source is the (optional) external reference clock #0 1 Core clock used for SysTick #1 COUNTFLAG System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register. 16 1 read-write ENABLE System Tick Counter Enabled\n 0 1 read-write 0 Counter Disabled #0 1 Counter will operate in a multi-shot manner #1 TICKINT System Tick Interrupt Enabled\n 1 1 read-write 0 Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred #0 1 Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick current value register by a register write in software will not cause SysTick to be pended #1 SYST_LOAD SYST_LOAD SysTick Reload Value Register 0x14 read-write n 0x0 0x0 RELOAD System Tick Reload Value\nValue to load into the Current Value register when the counter reaches 0. 0 24 read-write SYST_VAL SYST_VAL SysTick Current Value Register 0x18 read-write n 0x0 0x0 CURRENT System Tick Current Value\nCurrent counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. Unsupported bits RAZ (see SysTick Reload Value register). 0 24 read-write SPI SPI Register Map SPI 0x0 0x0 0x18 registers n 0x20 0x4 registers n 0x30 0x4 registers n 0x60 0xC registers n CLKDIV SPI_CLKDIV SPI Clock Divider Register 0x4 read-write n 0x0 0x0 DIVIDER Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.\nNote: Not supported in I2S mode.\nNote: User should set DIVIDER carefully because the peripheral clock frequency must be slower than or equal to system frequency 0 8 read-write CTL SPI_CTL SPI Control Register 0x0 read-write n 0x0 0x0 CLKPOL Clock Polarity\n 3 1 read-write 0 SPI bus clock is idle low #0 1 SPI bus clock is idle high #1 DATDIR Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer.\n 20 1 read-write 0 SPI data is input direction #0 1 SPI data is output direction #1 DWIDTH Data Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n 8 5 read-write HALFDPX SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPI_CTL[20]) can be used to set the data direction in half-duplex transfer.\n 14 1 read-write 0 SPI operates in full-duplex transfer #0 1 SPI operates in half-duplex transfer #1 LSB Send LSB First\n 13 1 read-write 0 The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX) #1 REORDER Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. 19 1 read-write 0 Byte Reorder function Disabled #0 1 Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV #1 RXNEG Receive on Negative Edge\nNote: The setting of TXNEG and RXNEG are mutual exclusive 1 1 read-write 0 Received data input signal is latched on the rising edge of SPI bus clock #0 1 Received data input signal is latched on the falling edge of SPI bus clock #1 RXONLY Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode. In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. \n 15 1 read-write 0 Receive-only mode Disabled #0 1 Receive-only mode Enabled #1 SLAVE Slave Mode Control\n 18 1 read-write 0 Master mode #0 1 Slave mode #1 SPIEN SPI Transfer Control Enable Bit\nIn Master mode, the transfer will start when there is data in the FIFO buffer after this is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1.\nNote: Before changing the configurations of SPI_CTL, SPI_CLKDIV, SPI_SSCTL and SPI_FIFOCTL registers, user shall clear the SPIEN (SPI_CTL[0]) and confirm the SPIENSTS (SPI_STATUS[15]) is 0. 0 1 read-write 0 Transfer control Disabled #0 1 Transfer control Enabled #1 SUSPITV Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\n 4 4 read-write TXNEG Transmit on Negative Edge\nNote: The setting of TXNEG and RXNEG are mutual exclusive 2 1 read-write 0 Transmitted data output signal is changed on the rising edge of SPI bus clock #0 1 Transmitted data output signal is changed on the falling edge of SPI bus clock #1 UNITIEN Unit Transfer Interrupt Enable Bit\n 17 1 read-write 0 SPI unit transfer interrupt Disabled #0 1 SPI unit transfer interrupt Enabled #1 FIFOCTL SPI_FIFOCTL SPI FIFO Control Register 0x10 read-write n 0x0 0x0 RXFBCLR Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared. 8 1 read-write 0 No effect #0 1 Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1 #1 RXOVIEN Receive FIFO Overrun Interrupt Enable Bit\n 5 1 read-write 0 Receive FIFO overrun interrupt Disabled #0 1 Receive FIFO overrun interrupt Enabled #1 RXRST Receive Reset (Only for SPI)\n 0 1 read-write 0 No effect #0 1 Reset receive FIFO pointer and receive circuit. The RXFULL (SPI_STATUS[9]) bit will be cleared to 0 and the RXEMPTY (SPI_STATUS[8]) bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not #1 RXTH Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0. 24 2 read-write RXTHIEN Receive FIFO Threshold Interrupt Enable Bit\n 2 1 read-write 0 RX FIFO threshold interrupt Disabled #0 1 RX FIFO threshold interrupt Enabled #1 RXTOIEN Slave Receive Time-out Interrupt Enable Bit\n 4 1 read-write 0 Receive time-out interrupt Disabled #0 1 Receive time-out interrupt Enabled #1 TXFBCLR Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared. 9 1 read-write 0 No effect #0 1 Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1 #1 TXRST Transmit Reset (Only for SPI)\nNote: If TX under-run event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state. 1 1 read-write 0 No effect #0 1 Reset transmit FIFO pointer and transmit circuit. The TXFULL (SPI_STATUS[17]) bit will be cleared to 0 and the TXEMPTY (SPI_STATUS[16]) bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not #1 TXTH Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0. 28 2 read-write TXTHIEN Transmit FIFO Threshold Interrupt Enable Bit\n 3 1 read-write 0 TX FIFO threshold interrupt Disabled #0 1 TX FIFO threshold interrupt Enabled #1 TXUFIEN TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode, TXUFIF (SPI_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt. \n 7 1 read-write 0 Slave TX underflow interrupt Disabled #0 1 Slave TX underflow interrupt Enabled #1 TXUFPOL TX Underflow Data Polarity\nNote:\n1. The TX underflow event occurs if there is not any data in TX FIFO when the slave selection signal is active.\n2. This bit should be set as 0 in I2S mode.\n3. When TX underflow event occurs, SPI_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward. Data stored in TX FIFO will be sent through SPI_MISO pin in the next transfer frame. 6 1 read-write 0 The SPI data out is keep 0 if there is TX underflow event in Slave mode #0 1 The SPI data out is keep 1 if there is TX underflow event in Slave mode #1 I2SCLK SPI_I2SCLK I2S Clock Divider Control Register 0x64 read-write n 0x0 0x0 BCLKDIV Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode. The clock frequency of bit clock, fBCLK, is determined by the following expression:\n\nwhere \n is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.\nIn I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by . \nThe peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock.\nNote: User should set BCLKDIV carefully because the peripheral clock frequency must be slower than or equal to system frequency 8 9 read-write MCLKDIV Master Clock Divider\nIf MCLKEN is set to 1, I2S controller will generate master clock for external audio devices. The frequency of master clock, fMCLK, is determined by the following expressions:\nwhere\n is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. In general, the master clock rate is 256 times sampling clock rate. 0 6 read-write I2SCTL SPI_I2SCTL I2S Control Register 0x60 read-write n 0x0 0x0 FORMAT Data Format Selection\n 28 2 read-write 0 I2S data format #00 1 MSB justified data format #01 2 PCM mode A #10 3 PCM mode B #11 I2SEN I2S Controller Enable Bit\nNote 2: Before changing the configurations of SPI_I2SCTL, SPI_I2SCLK, and SPI_FIFOCTL registers, user shall clear the I2SEN (SPI_I2SCTL[0]) and confirm the I2SENSTS (SPI_I2SSTS[15]) is 0. 0 1 read-write 0 Disabled I2S mode #0 1 Enabled I2S mode #1 LZCEN Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPI_I2SSTS register is set to 1. This function is only available in transmit operation.\n 17 1 read-write 0 Left channel zero cross detection Disabled #0 1 Left channel zero cross detection Enabled #1 LZCIEN Left Channel Zero-cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero-cross event occurs.\n 25 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 MCLKEN Master Clock Enable Bit\nIf MCLKEN is set to 1, I2S controller will generate master clock on I2Sn_MCLK pin for external audio devices.\n 15 1 read-write 0 Master clock Disabled #0 1 Master clock Enabled #1 MONO Monaural Data\n 6 1 read-write 0 Data is stereo format #0 1 Data is monaural format #1 MUTE Transmit Mute Enable Bit\n 3 1 read-write 0 Transmit data is shifted from buffer #0 1 Transmit channel zero #1 ORDER Stereo Data Order in FIFO\n 7 1 read-write 0 Left channel data at high byte #0 1 Left channel data at low byte #1 RXEN Receive Enable Bit\n 2 1 read-write 0 Data receive Disabled #0 1 Data receive Enabled #1 RXLCH Receive Left Channel Enable Bit\n 23 1 read-write 0 Receive right channel data in Mono mode #0 1 Receive left channel data in Mono mode #1 RZCEN Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPI_I2SSTS register is set to 1. This function is only available in transmit operation.\n 16 1 read-write 0 Right channel zero cross detection Disabled #0 1 Right channel zero cross detection Enabled #1 RZCIEN Right Channel Zero-cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero-cross event occurs.\n 24 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 SLAVE Slave Mode\nI2S can operate as master or slave. For Master mode, I2Sn_BCLK and I2Sn_LRCLK pins are output mode and send bit clock from the NUC121/125 series to audio CODEC chip. In Slave mode, I2Sn_BCLK and I2Sn_LRCLK pins are input mode and I2Sn_BCLK and I2Sn_LRCLK signals are received from outer audio CODEC chip.\n 8 1 read-write 0 Master mode #0 1 Slave mode #1 TXEN Transmit Enable Bit\n 1 1 read-write 0 Data transmit Disabled #0 1 Data transmit Enabled #1 WDWIDTH Word Width\n 4 2 read-write 0 data size is 8-bit #00 1 data size is 16-bit #01 2 data size is 24-bit #10 3 data size is 32-bit #11 I2SSTS SPI_I2SSTS I2S Status Register 0x68 read-write n 0x0 0x0 I2SENSTS I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S controller logic is disabled, this bit indicates the real status of SPI/I2S controller logic for user. 15 1 read-only 0 The SPI/I2S control logic is disabled #0 1 The SPI/I2S control logic is enabled #1 LZCIF Left Channel Zero Cross Interrupt Flag\n 21 1 read-write 0 No zero cross event occurred on left channel #0 1 Zero cross event occurred on left channel #1 RIGHT Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel.\n 4 1 read-only 0 Left channel #0 1 Right channel #1 RXCNT Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 24 3 read-only RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only)\n 8 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RXFULL Receive FIFO Buffer Full Indicator (Read Only)\n 9 1 read-only 0 Receive FIFO buffer is not full #0 1 Receive FIFO buffer is full #1 RXOVIF Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 11 1 read-write RXTHIF Receive FIFO Threshold Interrupt Flag (Read Only)\n 10 1 read-only 0 The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RXTH #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RXTH #1 RXTOIF Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it. 12 1 read-write 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 RZCIF Right Channel Zero Cross Interrupt Flag\n 20 1 read-write 0 No zero cross event occurred on right channel #0 1 Zero cross event occurred on right channel #1 TXCNT Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 28 3 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only)\n 16 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only)\n 17 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TXRXRST TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done. 23 1 read-only 0 The reset function of TXRST or RXRST is done #0 1 Doing the reset function of TXRST or RXRST #1 TXTHIF Transmit FIFO Threshold Interrupt Flag (Read Only)\n 18 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH #1 TXUFIF Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 19 1 read-write PDMACTL SPI_PDMACTL SPI PDMA Control Register 0xC read-write n 0x0 0x0 PDMARST PDMA Reset\n 2 1 read-write 0 No effect #0 1 Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0 #1 RXPDMAEN Receive PDMA Enable Bit\n 1 1 read-write 0 Receiver PDMA function Disabled #0 1 Receiver PDMA function Enabled #1 TXPDMAEN Transmit PDMA Enable Bit\nNote: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously. 0 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 RX SPI_RX SPI Data Receive Register 0x30 read-only n 0x0 0x0 RX Data Receive Register\nThere are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPI_STATUS[8] or SPI_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. This is a read only register. 0 32 read-only SSCTL SPI_SSCTL SPI Slave Select Control Register 0x8 read-write n 0x0 0x0 AUTOSS Automatic Slave Selection Function Enable Bit (Master Only)\n 3 1 read-write 0 Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (SPI_SSCTL[0]) #0 1 Automatic slave selection function Enabled #1 SLVBEIEN Slave Mode Bit Count Error Interrupt Enable Bit\n 8 1 read-write 0 Slave mode bit count error interrupt Disabled #0 1 Slave mode bit count error interrupt Enabled #1 SLVURIEN Slave Mode TX Under Run Interrupt Enable Bit\n 9 1 read-write 0 Slave mode TX under run interrupt Disabled #0 1 Slave mode TX under run interrupt Enabled #1 SS Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0,\n 0 1 read-write 0 set the SPI_SS line to inactive state.\nKeep the SPI_SS line at inactive state #0 1 set the SPI_SS line to active state.\nSPI_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPI_SS is specified in SSACTPOL (SPI_SSCTL[2]) #1 SSACTIEN Slave Select Active Interrupt Enable Bit\n 12 1 read-write 0 Slave select active interrupt Disabled #0 1 Slave select active interrupt Enabled #1 SSACTPOL Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPI_SS).\n 2 1 read-write 0 The slave selection signal SPI_SS is active low #0 1 The slave selection signal SPI_SS is active high #1 SSINAIEN Slave Select Inactive Interrupt Enable Bit\n 13 1 read-write 0 Slave select inactive interrupt Disabled #0 1 Slave select inactive interrupt Enabled #1 STATUS SPI_STATUS SPI Status Register 0x14 read-write n 0x0 0x0 BUSY Busy Status (Read Only)\n 0 1 read-only 0 SPI controller is in idle state #0 1 SPI controller is in busy state #1 RXCNT Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 24 4 read-only RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only)\n 8 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RXFULL Receive FIFO Buffer Full Indicator (Read Only)\n 9 1 read-only 0 Receive FIFO buffer is not full #0 1 Receive FIFO buffer is full #1 RXOVIF Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 11 1 read-write 0 No FIFO is over run #0 1 Receive FIFO over run #1 RXTHIF Receive FIFO Threshold Interrupt Flag (Read Only)\n 10 1 read-only 0 The valid data count within the RX FIFO buffer is smaller than or equal to the setting value of RXTH #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RXTH #1 RXTOIF Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it. 12 1 read-write 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock periods in Master mode or over 576 peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 SLVBEIF Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.\nNote: If the slave select is active but there is no any bus clock input, the SLVBCEIF is also active when the slave select goes to inactive state. This bit will be cleared by writing 1 to it. 6 1 read-write 0 No Slave mode bit count error event #0 1 Slave mode bit count error event occurs #1 SLVURIF Slave Mode TX Under Run Interrupt Flag\nIn Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 7 1 read-write 0 No Slave TX under run event #0 1 Slave TX under run occurs #1 SPIENSTS SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller. 15 1 read-only 0 The SPI controller is disabled #0 1 The SPI controller is enabled #1 SSACTIF Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it. 2 1 read-write 0 Slave select active interrupt was cleared or not occurred #0 1 Slave select active interrupt event occurred #1 SSINAIF Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it. 3 1 read-write 0 Slave select inactive interrupt was cleared or not occurred #0 1 Slave select inactive interrupt event occurred #1 SSLINE Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (SPI_SSCTL[2]) is set to 0, and the SSLINE is 1, the SPI slave select is in inactive status. 4 1 read-only 0 The slave select line status is 0 #0 1 The slave select line status is 1 #1 TXCNT Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 28 4 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only)\n 16 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only)\n 17 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TXRXRST TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done. 23 1 read-only 0 The reset function of TXRST or RXRST is done #0 1 Doing the reset function of TXRST or RXRST #1 TXTHIF Transmit FIFO Threshold Interrupt Flag (Read Only)\n 18 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH #1 TXUFIF TX Underflow Interrupt Flag\nWhen the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. 19 1 read-write 0 No effect #0 1 No data in Transmit FIFO and TX shift register when the slave selection signal is active #1 UNITIF Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it. 1 1 read-write 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 TX SPI_TX SPI Data Transmit Register 0x20 write-only n 0x0 0x0 TX Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffer. The number of valid bits depends on the setting of DWIDTH (SPI_CTL[12:8]) in SPI mode or WDWIDTH (SPI_I2SCTL[5:4]) in I2S mode.\nIn SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.\nIn I2S mode, if WDWIDTH (SPI_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[24:0]. If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section\nNote: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. 0 32 write-only SYS SYS Register Map SYS 0x0 0x0 0x14 registers n 0x100 0x4 registers n 0x114 0x4 registers n 0x18 0x8 registers n 0x24 0x4 registers n 0x34 0x20 registers n 0x58 0x4 registers n 0x80 0xC registers n 0xC0 0x4 registers n BODCTL SYS_BODCTL Brown-out Detector Control Register 0x18 -1 read-write n 0x0 0x0 BODDGSEL Brown-out Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 8 3 read-write 0 BOD output is sampled by LIRC clock #000 1 4 system clock (HCLK) #001 2 8 system clock (HCLK) #010 3 16 system clock (HCLK) #011 4 32 system clock (HCLK) #100 5 64 system clock (HCLK) #101 6 128 system clock (HCLK) #110 7 256 system clock (HCLK) #111 BODEN Brown-out Detector Enable Bit (Write Protect)\nThe default value is set by flash controller user configuration register CBODEN (CONFIG0 [23]).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 Brown-out Detector function Disabled #0 1 Brown-out Detector function Enabled #1 BODIF Brown-out Detector Interrupt Flag\nNote: This bit can be cleared by software writing '1'. 4 1 read-write 0 Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting #0 1 When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled #1 BODLPM Brown-out Detector Low Power Mode (Write Protect)\nNote1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register. 5 1 read-write 0 BOD operate in normal mode (default) #0 1 BOD Low Power mode Enabled #1 BODOUT Brown-out Detector Output Status\nIt means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function disabled, this bit always responds 0. 6 1 read-write 0 Brown-out Detector output status is 0 #0 1 Brown-out Detector output status is 1 #1 BODRSTEN Brown-out Reset Enable Bit (Write Protect) The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit. Note1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. BOD interrupt will keep till to the BODEN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 3 1 read-write 0 Brown-out INTERRUPT function Enabled #0 1 Brown-out RESET function Enabled #1 BODVL Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by flash controller user configuration register CBOV (CONFIG0 [22:21]).\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 1 2 read-write 0 Brown-Out Detector threshold voltage is 2.2V #00 1 Brown-Out Detector threshold voltage is 2.7V #01 2 Brown-Out Detector threshold voltage is 3.7V #10 3 Brown-Out Detector threshold voltage is 4.5V #11 LVRDGSEL LVR Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 12 3 read-write 0 Without de-glitch function #000 1 4 system clock (HCLK) #001 2 8 system clock (HCLK) #010 3 16 system clock (HCLK) #011 4 32 system clock (HCLK) #100 5 64 system clock (HCLK) #101 6 128 system clock (HCLK) #110 7 256 system clock (HCLK) #111 LVREN Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.\nNote1: After enabling the bit, the LVR function will be active with 200us delay for LVR output stable (default).\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register. 7 1 read-write 0 Low Voltage Reset function Disabled #0 1 Low Voltage Reset function Enabled #1 GPA_MFPH SYS_GPA_MFPH GPIOA High Byte Multiple Function Control Register 0x34 read-write n 0x0 0x0 PA10MFP PA.10 Multi-function Pin Selection 8 4 read-write PA11MFP PA.11 Multi-function Pin Selection 12 4 read-write PA12MFP PA.12 Multi-function Pin Selection 16 4 read-write PA13MFP PA.13 Multi-function Pin Selection 20 4 read-write PA14MFP PA.14 Multi-function Pin Selection 24 4 read-write PA15MFP PA.15 Multi-function Pin Selection 28 4 read-write GPB_MFPH SYS_GPB_MFPH GPIOB High Byte Multiple Function Control Register 0x3C read-write n 0x0 0x0 PB10MFP PB.10 Multi-function Pin Selection 8 4 read-write PB12MFP PB.12 Multi-function Pin Selection 16 4 read-write PB13MFP PB.13 Multi-function Pin Selection 20 4 read-write PB14MFP PB.14 Multi-function Pin Selection 24 4 read-write PB15MFP PB.15 Multi-function Pin Selection 28 4 read-write PB8MFP PB.8 Multi-function Pin Selection 0 4 read-write PB9MFP PB.9 Multi-function Pin Selection 4 4 read-write GPB_MFPL SYS_GPB_MFPL GPIOB Low Byte Multiple Function Control Register 0x38 read-write n 0x0 0x0 PB0MFP PB.0 Multi-function Pin Selection 0 4 read-write PB1MFP PB.1 Multi-function Pin Selection 4 4 read-write PB2MFP PB.2 Multi-function Pin Selection 8 4 read-write PB3MFP PB.3 Multi-function Pin Selection 12 4 read-write PB4MFP PB.4 Multi-function Pin Selection 16 4 read-write PB5MFP PB.5 Multi-function Pin Selection 20 4 read-write PB6MFP PB.6 Multi-function Pin Selection 24 4 read-write PB7MFP PB.7 Multi-function Pin Selection 28 4 read-write GPC_MFPH SYS_GPC_MFPH GPIOC High Byte Multiple Function Control Register 0x44 read-write n 0x0 0x0 PC10MFP PC.10 Multi-function Pin Selection 8 4 read-write PC11MFP PC.11 Multi-function Pin Selection 12 4 read-write PC12MFP PC.12 Multi-function Pin Selection 16 4 read-write PC13MFP PC.13 Multi-function Pin Selection 20 4 read-write PC8MFP PC.8 Multi-function Pin Selection 0 4 read-write PC9MFP PC.9 Multi-function Pin Selection 4 4 read-write GPC_MFPL SYS_GPC_MFPL GPIOC Low Byte Multiple Function Control Register 0x40 read-write n 0x0 0x0 PC0MFP PC.0 Multi-function Pin Selection 0 4 read-write PC1MFP PC.1 Multi-function Pin Selection. 4 4 read-write PC2MFP PC.2 Multi-function Pin Selection 8 4 read-write PC3MFP PC.3 Multi-function Pin Selection 12 4 read-write PC4MFP PC.4 Multi-function Pin Selection 16 4 read-write PC5MFP PC.5 Multi-function Pin Selection 20 4 read-write GPD_MFPH SYS_GPD_MFPH GPIOD High Byte Multiple Function Control Register 0x4C read-write n 0x0 0x0 PD10MFP PD.10 Multi-function Pin Selection 8 4 read-write PD11MFP PD.11 Multi-function Pin Selection 12 4 read-write PD8MFP PD.8 Multi-function Pin Selection 0 4 read-write PD9MFP PD.9 Multi-function Pin Selection 4 4 read-write GPD_MFPL SYS_GPD_MFPL GPIOD Low Byte Multiple Function Control Register 0x48 read-write n 0x0 0x0 PD0MFP PD.0 Multi-function Pin Selection 0 4 read-write PD1MFP PD.1 Multi-function Pin Selection 4 4 read-write PD2MFP PD.2 Multi-function Pin Selection 8 4 read-write PD3MFP PD.3 Multi-function Pin Selection 12 4 read-write PD4MFP PD.4 Multi-function Pin Selection 16 4 read-write PD5MFP PD.5 Multi-function Pin Selection 20 4 read-write GPE_MFPL SYS_GPE_MFPL GPIOE Low Byte Multiple Function Control Register 0x50 read-write n 0x0 0x0 PE0MFP PE.0 Multi-function Pin Selection 0 4 read-write PE1MFP PE.1 Multi-function Pin Selection 4 4 read-write PE2MFP PE.2 Multi-function Pin Selection 8 4 read-write GPF_MFPL SYS_GPF_MFPL GPIOF Low Byte Multiple Function Control Register 0x58 -1 read-write n 0x0 0x0 PF0MFP PF.0 Multi-function Pin Selection 0 4 read-write PF1MFP PF.1 Multi-function Pin Selection 4 4 read-write PF2MFP PF.2 Multi-function Pin Selection 8 4 read-write PF3MFP PF.3 Multi-function Pin Selection 12 4 read-write PF4MFP PF.4 Multi-function Pin Selection 16 4 read-write PF5MFP PF.5 Multi-function Pin Selection 20 4 read-write IPRST0 SYS_IPRST0 Peripheral Reset Control Register 0 0x8 read-write n 0x0 0x0 CHIPRST Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.\nAbout the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 Chip normal operation #0 1 Chip one-shot reset #1 CPURST Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 Processor core normal operation #0 1 Processor core one-shot reset #1 PDMARST PDMA Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 2 1 read-write 0 PDMA controller normal operation #0 1 PDMA controller reset #1 IPRST1 SYS_IPRST1 Peripheral Reset Control Register 1 0xC read-write n 0x0 0x0 ADCRST ADC Controller Reset\n 28 1 read-write 0 ADC controller normal operation #0 1 ADC controller reset #1 BPWM0RST BPWM0 Controller Reset \n 20 1 read-write 0 BPWM0 controller normal operation #0 1 BPWM0 controller reset #1 BPWM1RST BPWM1 Controller Reset \n 21 1 read-write 0 BPWM1 controller normal operation #0 1 BPWM1 controller reset #1 GPIORST GPIO Controller Reset\n 1 1 read-write 0 GPIO controller normal operation #0 1 GPIO controller reset #1 I2C0RST I2C0 Controller Reset\n 8 1 read-write 0 I2C0 controller normal operation #0 1 I2C0 controller reset #1 I2C1RST I2C1 Controller Reset\n 9 1 read-write 0 I2C1 controller normal operation #0 1 I2C1 controller reset #1 PWM0RST PWM0 Controller Reset \n 22 1 read-write 0 PWM0 controller normal operation #0 1 PWM0 controller reset #1 PWM1RST PWM1 Controller Reset \n 23 1 read-write 0 PWM1 controller normal operation #0 1 PWM1 controller reset #1 SPI0RST SPI0 Controller Reset\n 12 1 read-write 0 SPI0 controller normal operation #0 1 SPI0 controller reset #1 TMR0RST Timer0 Controller Reset\n 2 1 read-write 0 Timer0 controller normal operation #0 1 Timer0 controller reset #1 TMR1RST Timer1 Controller Reset\n 3 1 read-write 0 Timer1 controller normal operation #0 1 Timer1 controller reset #1 TMR2RST Timer2 Controller Reset\n 4 1 read-write 0 Timer2 controller normal operation #0 1 Timer2 controller reset #1 TMR3RST Timer3 Controller Reset\n 5 1 read-write 0 Timer3 controller normal operation #0 1 Timer3 controller reset #1 UART0RST UART0 Controller Reset\n 16 1 read-write 0 UART0 controller normal operation #0 1 UART0 controller reset #1 USBDRST USB Device Controller Reset\n 27 1 read-write 0 USB device controller normal operation #0 1 USB device controller reset #1 IPRST2 SYS_IPRST2 Peripheral Reset Control Register 2 0x10 read-write n 0x0 0x0 USCI0RST USCI0 Controller Reset \n 8 1 read-write 0 USCI0 controller normal operation #0 1 USCI0 controller reset #1 IRCTCTL SYS_IRCTCTL HIRC Trim Control Register 0x80 read-write n 0x0 0x0 CESTOPEN Clock Error Stop Enable Bit\nNote1: CESTOPEN is set to 0 and FREQLOCK is set to 1, CLKERRIF will be set to 1 once and auto-trim function will stop trimming HIRC until LXT or SOF works normally.\nNote2: After FREQLOCK is set to 1, CLKERRIF will be set to 1 only once and RC_TRIM will hang on and stop trimming RC until a reference clock is recovered when CESTOPEN is 0. 8 1 read-write 0 The trim operation is keep going if clock is inaccuracy #0 1 The trim operation is stopped if clock is inaccuracy #1 FREQSEL Trim Frequency Selection\nThis field indicates the target frequency of internal high speed RC oscillator (HIRC) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN(SYS_IRCTCTL1[8]) is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.\n 0 2 read-write 0 Disable HIRC auto trim function #00 1 Reserved #01 2 Enable HIRC auto trim function and trim HIRC to 48 MHz #10 3 Reserved #11 LOOPSEL Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many clocks of reference clock .\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. 4 2 read-write 0 Trim value calculation is based on average difference in 4 clocks of reference clock #00 1 Trim value calculation is based on average difference in 8 clocks of reference clock #01 2 Trim value calculation is based on average difference in 16 clocks of reference clock #10 3 Trim value calculation is based on average difference in 32 clocks of reference clock #11 REFCKSEL Reference Clock Selection\n 10 1 read-write 0 HIRC trim reference clock is from LXT (32.768 kHz) #0 1 HIRC trim reference clock is from USB SOF (Start-Of-Frame) packet #1 RETRYCNT Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL(SYS_IRCTCTL1[1:0]) will be cleared to 00.\n 6 2 read-write 0 Trim retry count limitation is 64 loops #00 1 Trim retry count limitation is 128 loops #01 2 Trim retry count limitation is 256 loops #10 3 Trim retry count limitation is 512 loops #11 IRCTIEN SYS_IRCTIEN HIRC Trim Interrupt Enable Register 0x84 read-write n 0x0 0x0 CLKEIEN HIRC Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_IRCTSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.\n 2 1 read-write 0 Disable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU #0 1 Enable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU #1 TFAILIEN HIRC Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL1[1:0]).\nIf this bit is high and TFAILIF(SYS_IRCTSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.\n 1 1 read-write 0 Disable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU #0 1 Enable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU #1 IRCTISTS SYS_IRCTISTS HIRC Trim Interrupt Status Register 0x88 read-write n 0x0 0x0 CLKERRIF HIRC Clock Error Interrupt Status\nWhen the frequency of SOF or 48 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_IRCTIEN1[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.\n 2 1 read-write 0 HIRC Clock frequency is accuracy #0 1 HIRC Clock frequency is inaccuracy #1 FREQLOCK HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt.\nWrite 1 to clear this to 0. This bit will be set automatically, if the frequecy is lock and the RC_TRIM is enabled.\n 0 1 read-write 0 The internal high-speed RC oscillator 1 frequency doesn't lock at 48 MHz yet #0 1 The internal high-speed RC oscillator 1 frequency locked at 48 MHz #1 TFAILIF HIRC Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_iRCTCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_IRCTIEN1[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0.\n 1 1 read-write 0 HIRC trim value update limitation count does not reach #0 1 HIRC trim value update limitation count reached and frequency still not locked #1 IVSCTL SYS_IVSCTL Internal Voltage Source Control Register 0x1C read-write n 0x0 0x0 VTEMPEN Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function.\nNote: After this bit is set to 1, the value of temperature sensor output can be obtained from ADC conversion result. Please refer to ADC function chapter for details. 0 1 read-write 0 Temperature sensor function Disabled (default) #0 1 Temperature sensor function Enabled #1 MODCTL SYS_MODCTL Modulation Control Register 0xC0 read-write n 0x0 0x0 MODEN Modulation Function Enable Bit\nThis bit enables modulation funcion by modulating with BPWM2 channel output and USCI0(USCI0_DAT0) or UART0(UART0_TXD) output.\n 0 1 read-write 0 Modulation Function Disabled #0 1 Modulation Function Enabled #1 MODH Modulation at Data High\nSelect modulation pulse(BPWM2) at UART0_TXD high or low\n0: Modulation pulse at UART0_TXD or USCI0_DAT0 low.\n1: Modulation pulse at UART0_TXD or USCI0_DAT0 high. 1 1 read-write MODPWMSEL BPWM2 Channel Select for Modulation\nSelect the BPWM2 channel to modulate with the UART0_TXD or USCI0_DAT0.\n0000: BPWM2 Channel 0 modulate with UART0_TXD.\n0001: BPWM2 Channel 1 modulate with UART0_TXD.\n0010: BPWM2 Channel 2 modulate with UART0_TXD.\n0011: BPWM2 Channel 3 modulete with UART0_TXD.\n0100: BPWM2 Channel 4 modulete with UART0_TXD.\n0101: BPWM2 Channel 5 modulete with UART0_TXD.\n0110: Reserved.\n0111: Reserved.\n1000: BPWM2 Channel 0 modulate with USCI0_DAT0.\n1001: BPWM2 Channel 1 modulate with USCI0_DAT0.\n1010: BPWM2 Channel 2 modulate with USCI0_DAT0.\n1011: BPWM2 Channel 3 modulete with USCI0_DAT0.\n1100: BPWM2 Channel 4 modulete with USCI0_DAT0.\n1101: BPWM2 Channel 5 modulete with USCI0_DAT0.\n1110: Reserved.\n1111: Reserved.\nNote: This bis is valid while MODEN (SYS_MODCTL[0]) is set to 1. 4 4 read-write PDID SYS_PDID Part Device Identification Number Register 0x0 -1 read-only n 0x0 0x0 PDID Part Device Identification Number (Read Only)\nThis register reflects device part number code. Software can read this register to identify which device is used. 0 32 read-only PORCTL SYS_PORCTL Power-On-reset Controller Register 0x24 read-write n 0x0 0x0 POROFF Power-on Reset Enable Bit (Write Protect)\nWhen powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.\nThe POR function will be active again when this field is set to another value or chip is reset by other reset source, including:\nnRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 0 16 read-write REGLCTL SYS_REGLCTL Register Lock Control Register 0x100 read-write n 0x0 0x0 REGLCTL Register Lock Control Code (Write) Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 59h , 16h , 88h to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. Register Lock Control Disable Index (Read) The Protected registers are: SYS_IPRST0: address 0x5000_0008 SYS_BODCTL: address 0x5000_0018 SYS_PORCTL: address 0x5000_0024 SYS_TSOFFSET: address 0x5000_0114 CLK_PWRCTL: address 0x5000_0200 (bit[6] is not protected for power-down wake-up interrupt clear) CLK_APBCLK0 [0]: address 0x5000_0208 (bit[0] is watchdog clock enable) CLK_CLKSEL0: address 0x5000_0210 (for HCLK and CPU STCLK clock source select) CLK_CLKSEL1 [1:0]: address 0x5000_0214 (for watchdog clock source select) CLK_CLKSEL3 [8]: address 0x5000_0234 (for USBD clock source select) CLK_CLKDSTS: address 0x5000_0274 FMC_ISPCTL: address 0x4000_C000 (Flash ISP Control register) FMC_ISPTRG: address 0x4000_C010 (ISP Trigger Control register) FMC_ISPSTS: address 0x4000_C040 WDT_CTL: address 0x4000_4000 WDT_ALTCTL: address 0x4000_4004 FMC_FTCTL: address 0x4000_5018 FMC_ICPCMD: address 0x4000_501C EADC_TEST: address 0x4004_3200 AHBMCTL: address 0x40000400 CLK_PLLCTL: address 0x40000240 PWM_CTL0: address 0x4005_8000 PWM_CTL0: address 0x4005_9000 PWM_DTCTL0_1: address 0x4005_8070 PWM_DTCTL0_1: address 0x4005_9070 PWM_DTCTL2_3: address 0x4005_8074 PWM_DTCTL2_3: address 0x4005_9074 PWM_DTCTL4_5: address 0x4005_8078 PWM_DTCTL4_5: address 0x4005_9078 PWM_BRKCTL0_1: address 0x4005_80C8 PWM_BRKCTL0_1: address 0x4005_90C8 PWM_BRKCTL2_3: address 0x4005_80CC PWM_BRKCTL2_3: address 0x4005_90CC PWM_BRKCTL4_5: address 0x4005_80D0 PWM_BRKCTL4_5: address 0x4005_90D0 PWM_INTEN1: address 0x4005_80E4 PWM_INTEN1: address 0x4005_90E4 PWM_INTSTS1: address 0x4005_80EC PWM_INTSTS1: address 0x4005_90EC PWM_SELFTEST: address 0x4005_8300 PWM_SELFTEST: address 0x4005_9300 0 8 read-write 0 Write-protection Enabled for writing protected registers. Any write to the protected register is ignored 0 1 Write-protection Disabled for writing protected registers 1 RSTSTS SYS_RSTSTS System Reset Status Register 0x4 -1 read-write n 0x0 0x0 BODRF BOD Reset Flag The BOD reset flag is set by the Reset Signal from the Brown-Out Detector to indicate the previous reset source. Note: This bit can be cleared by software writing '1'. 4 1 read-write 0 No reset from BOD #0 1 The BOD had issued the reset signal to reset the system #1 CPULKRF the CPULK Reset Flag Is Set by Hardware If Cortex-M0 Lockup Happened\nNote: This bit can be cleared by software writing '1'. 8 1 read-write 0 No reset from CPU lockup happened #0 1 The Cortex-M0 lockup happened and chip is reset #1 CPURF CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 Core and Flash Memory Controller (FMC).\nNote: This bit can be cleared by software writing '1'. 7 1 read-write 0 No reset from CPU #0 1 The Cortex-M0 Core and FMC are reset by software setting CPURST to 1 #1 LVRF LVR Reset Flag The LVR reset flag is set by the Reset Signal from the Low Voltage Reset Controller to indicate the previous reset source. Note: This bit can be cleared by software writing '1'. 3 1 read-write 0 No reset from LVR #0 1 LVR controller had issued the reset signal to reset the system #1 MCURF MCU Reset Flag The MCU reset flag is set by the Reset Signal from the Cortex-M0 Core to indicate the previous reset source. Note: This bit can be cleared by software writing '1'. 5 1 read-write 0 No reset from Cortex-M0 #0 1 The Cortex-M0 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 core #1 PINRF NRESET Pin Reset Flag The nRESET pin reset flag is set by the Reset Signal from the nRESET Pin to indicate the previous reset source. Note: This bit can be cleared by software writing '1'. 1 1 read-write 0 No reset from nRESET pin #0 1 Pin nRESET had issued the reset signal to reset the system #1 PORF POR Reset Flag The POR reset flag is set by the Reset Signal from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. Note: This bit can be cleared by software writing '1'. 0 1 read-write 0 No reset from POR or CHIPRST #0 1 Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system #1 WDTRF WDT Reset Flag The WDT reset flag is set by the Reset Signal from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source. Note1: This bit can be cleared by software writing '1'. Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset. 2 1 read-write 0 No reset from watchdog timer or window watchdog timer #0 1 The watchdog timer or window watchdog timer had issued the reset signal to reset the system #1 TSOFFSET SYS_TSOFFSET Temperature Sensor Offset Register 0x114 read-only n 0x0 0x0 VTEMP Temperature Sensor Offset Value \nThis field reflects temperature sensor output voltage offset at 25oC.\nBased on this value, with the value of temperature sensor output obtained from ADC conversion result and temperature sensor characteristics, it's easily to get temperature result by roughly calculation. 0 12 read-only TMR01 TIMER Register Map TIMER 0x0 0x0 0x1C registers n 0x20 0x1C registers n TIMER0_CAP TIMER0_CAP Timer0 Capture Data Register 0x10 read-only n 0x0 0x0 CAPDAT Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT pin is matched with the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. 0 24 read-only TIMER0_CMP TIMER0_CMP Timer0 Compare Register 0x4 read-write n 0x0 0x0 CMPDAT Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field. 0 24 read-write TIMER0_CNT TIMER0_CNT Timer0 Data Register 0xC read-only n 0x0 0x0 CNT Timer Data Register\nIf EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value to get current 24- bit counter value .\nIf EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value to get current 24- bit event input counter value. 0 24 read-only TIMER0_CTL TIMER0_CTL Timer0 Control and Status Register 0x0 read-write n 0x0 0x0 ACTSTS Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\n 25 1 read-only 0 24-bit up counter is not active #0 1 24-bit up counter is active #1 CNTEN Timer Counting Enable Bit\n 30 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 EXTCNTEN Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source. 24 1 read-write 0 Event counter mode Disabled #0 1 Event counter mode Enabled #1 ICEDEBUG ICE Debug Mode Acknowledge Disable (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement affects TIMER counting #0 1 ICE debug mode acknowledgement Disabled #1 INTEN Timer Interrupt Enable Bit\nNote: If this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. 29 1 read-write 0 Timer Interrupt Disabled #0 1 Timer Interrupt Enabled #1 OPMODE Timer Operating Mode Select\n 27 2 read-write 0 The Timer controller is operated in One-shot mode #00 1 The Timer controller is operated in Periodic mode #01 2 The Timer controller is operated in Toggle-output mode #10 3 The Timer controller is operated in Continuous Counting mode #11 PSC Prescale Counter\n 0 8 read-write RSTCNT Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\n 26 1 read-write 0 No effect #0 1 Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit #1 TGLPINSEL Toggle-output Pin Select\n 22 1 read-write 0 Toggle mode output to Tx (Timer Event Counter Pin) #0 1 Toggle mode output to Tx_EXT (Timer External Capture Pin) #1 TRGADC Trigger ADC Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger ADC.\n 21 1 read-write 0 Timer interrupt trigger ADC Disabled #0 1 Timer interrupt trigger ADC Enabled #1 TRGBPWM Trigger BPWM Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger BPWM.\n 9 1 read-write 0 Timer interrupt trigger BPWM Disabled #0 1 Timer interrupt trigger BPWM Enabled #1 TRGDAC Trigger DAC Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger DAC.\n 20 1 read-write 0 Timer interrupt trigger DAC Disabled #0 1 Timer interrupt trigger DAC Enabled #1 TRGPDMA Trigger PDMA Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PDMA.\n 8 1 read-write 0 Timer interrupt trigger PDMA Disabled #0 1 Timer interrupt trigger PDMA Enabled #1 TRGPWM Trigger PWM Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PWM.\n 19 1 read-write 0 Timer interrupt trigger PWM Disabled #0 1 Timer interrupt trigger PWM Enabled #1 TRGSSEL Trigger Source Select Bit\nThis bit is used to select trigger source from Timer time-out interrupt signal or capture interrupt signal.\n 18 1 read-write 0 Timer time-out interrupt signal is used to trigger PWM, BPWM, PDMA,ADC and DAC #0 1 Capture interrupt signal is used to trigger PWM, BPWM, PDMA, ADC and DAC #1 WKEN Wake-up Function Enable Bit\nIf this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.\n 23 1 read-write 0 Wake-up function Disabled if timer interrupt signal generated #0 1 Wake-up function Enabled if timer interrupt signal generated #1 TIMER0_EINTSTS TIMER0_EINTSTS Timer0 External Interrupt Status Register 0x18 read-write n 0x0 0x0 CAPIF Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. 0 1 read-write 0 Tx_EXT (x= 0~3) pin interrupt did not occur #0 1 Tx_EXT (x= 0~3) pin interrupt occurred #1 TIMER0_EXTCTL TIMER0_EXTCTL Timer0 External Control Register 0x14 read-write n 0x0 0x0 CAPDBEN Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of Tx_EXT pin is detected with de-bounce circuit. 6 1 read-write 0 Tx_EXT (x= 0~3) pin de-bounce Disabled #0 1 Tx_EXT (x= 0~3) pin de-bounce Enabled #1 CAPEDGE Timer External Capture Pin Edge Detect\n 1 2 read-write 0 A Falling edge on Tx_EXT (x= 0~3) pin will be detected #00 1 A Rising edge on Tx_EXT (x= 0~3) pin will be detected #01 2 Either Rising or Falling edge on Tx_EXT (x= 0~3) pin will be detected #10 3 Reserved #11 CAPEN Timer External Capture Pin Enable \nThis bit enables the Tx_EXT pin. \n 3 1 read-write 0 Tx_EXT (x= 0~3) pin Disabled #0 1 Tx_EXT (x= 0~3) pin Enabled #1 CAPFUNCS Capture Function Selection\n 4 1 read-write 0 External Capture Mode Enabled #0 1 External Reset Mode Enabled #1 CAPIEN Timer External Capture Interrupt Enable Bit\n 5 1 read-write 0 Tx_EXT (x= 0~3) pin detection Interrupt Disabled #0 1 Tx_EXT (x= 0~3) pin detection Interrupt Enabled #1 CNTDBEN Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of Tx pin is detected with de-bounce circuit. 7 1 read-write 0 Tx (x= 0~3) pin de-bounce Disabled #0 1 Tx (x= 0~3) pin de-bounce Enabled #1 CNTPHASE Timer External Count Phase \n 0 1 read-write 0 A Falling edge of external counting pin will be counted #0 1 A Rising edge of external counting pin will be counted #1 TIMER0_INTSTS TIMER0_INTSTS Timer0 Interrupt Status Register 0x8 read-write n 0x0 0x0 TIF Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 CNT value matches the CMPDAT value #1 TWKF Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it. 1 1 read-write 0 Timer does not cause CPU wake-up #0 1 CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated #1 TIMER1_CAP TIMER1_CAP Timer1 Capture Data Register 0x30 read-write n 0x0 0x0 TIMER1_CMP TIMER1_CMP Timer1 Compare Register 0x24 read-write n 0x0 0x0 TIMER1_CNT TIMER1_CNT Timer1 Data Register 0x2C read-write n 0x0 0x0 TIMER1_CTL TIMER1_CTL Timer1 Control and Status Register 0x20 read-write n 0x0 0x0 TIMER1_EINTSTS TIMER1_EINTSTS Timer1 External Interrupt Status Register 0x38 read-write n 0x0 0x0 TIMER1_EXTCTL TIMER1_EXTCTL Timer1 External Control Register 0x34 read-write n 0x0 0x0 TIMER1_INTSTS TIMER1_INTSTS Timer1 Interrupt Status Register 0x28 read-write n 0x0 0x0 TMR23 TIMER Register Map TIMER 0x0 0x0 0x1C registers n 0x20 0x1C registers n TIMER2_CAP TIMER2_CAP Timer2 Capture Data Register 0x10 read-only n 0x0 0x0 CAPDAT Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT pin is matched with the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. 0 24 read-only TIMER2_CMP TIMER2_CMP Timer2 Compare Register 0x4 read-write n 0x0 0x0 CMPDAT Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field. 0 24 read-write TIMER2_CNT TIMER2_CNT Timer2 Data Register 0xC read-only n 0x0 0x0 CNT Timer Data Register\nIf EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value to get current 24- bit counter value .\nIf EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value to get current 24- bit event input counter value. 0 24 read-only TIMER2_CTL TIMER2_CTL Timer2 Control and Status Register 0x0 read-write n 0x0 0x0 ACTSTS Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\n 25 1 read-only 0 24-bit up counter is not active #0 1 24-bit up counter is active #1 CNTEN Timer Counting Enable Bit\n 30 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 EXTCNTEN Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source. 24 1 read-write 0 Event counter mode Disabled #0 1 Event counter mode Enabled #1 ICEDEBUG ICE Debug Mode Acknowledge Disable (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement affects TIMER counting #0 1 ICE debug mode acknowledgement Disabled #1 INTEN Timer Interrupt Enable Bit\nNote: If this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. 29 1 read-write 0 Timer Interrupt Disabled #0 1 Timer Interrupt Enabled #1 OPMODE Timer Operating Mode Select\n 27 2 read-write 0 The Timer controller is operated in One-shot mode #00 1 The Timer controller is operated in Periodic mode #01 2 The Timer controller is operated in Toggle-output mode #10 3 The Timer controller is operated in Continuous Counting mode #11 PSC Prescale Counter\n 0 8 read-write RSTCNT Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\n 26 1 read-write 0 No effect #0 1 Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit #1 TGLPINSEL Toggle-output Pin Select\n 22 1 read-write 0 Toggle mode output to Tx (Timer Event Counter Pin) #0 1 Toggle mode output to Tx_EXT (Timer External Capture Pin) #1 TRGADC Trigger ADC Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger ADC.\n 21 1 read-write 0 Timer interrupt trigger ADC Disabled #0 1 Timer interrupt trigger ADC Enabled #1 TRGBPWM Trigger BPWM Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger BPWM.\n 9 1 read-write 0 Timer interrupt trigger BPWM Disabled #0 1 Timer interrupt trigger BPWM Enabled #1 TRGDAC Trigger DAC Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger DAC.\n 20 1 read-write 0 Timer interrupt trigger DAC Disabled #0 1 Timer interrupt trigger DAC Enabled #1 TRGPDMA Trigger PDMA Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PDMA.\n 8 1 read-write 0 Timer interrupt trigger PDMA Disabled #0 1 Timer interrupt trigger PDMA Enabled #1 TRGPWM Trigger PWM Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PWM.\n 19 1 read-write 0 Timer interrupt trigger PWM Disabled #0 1 Timer interrupt trigger PWM Enabled #1 TRGSSEL Trigger Source Select Bit\nThis bit is used to select trigger source from Timer time-out interrupt signal or capture interrupt signal.\n 18 1 read-write 0 Timer time-out interrupt signal is used to trigger PWM, BPWM, PDMA,ADC and DAC #0 1 Capture interrupt signal is used to trigger PWM, BPWM, PDMA, ADC and DAC #1 WKEN Wake-up Function Enable Bit\nIf this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.\n 23 1 read-write 0 Wake-up function Disabled if timer interrupt signal generated #0 1 Wake-up function Enabled if timer interrupt signal generated #1 TIMER2_EINTSTS TIMER2_EINTSTS Timer2 External Interrupt Status Register 0x18 read-write n 0x0 0x0 CAPIF Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. 0 1 read-write 0 Tx_EXT (x= 0~3) pin interrupt did not occur #0 1 Tx_EXT (x= 0~3) pin interrupt occurred #1 TIMER2_EXTCTL TIMER2_EXTCTL Timer2 External Control Register 0x14 read-write n 0x0 0x0 CAPDBEN Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of Tx_EXT pin is detected with de-bounce circuit. 6 1 read-write 0 Tx_EXT (x= 0~3) pin de-bounce Disabled #0 1 Tx_EXT (x= 0~3) pin de-bounce Enabled #1 CAPEDGE Timer External Capture Pin Edge Detect\n 1 2 read-write 0 A Falling edge on Tx_EXT (x= 0~3) pin will be detected #00 1 A Rising edge on Tx_EXT (x= 0~3) pin will be detected #01 2 Either Rising or Falling edge on Tx_EXT (x= 0~3) pin will be detected #10 3 Reserved #11 CAPEN Timer External Capture Pin Enable \nThis bit enables the Tx_EXT pin. \n 3 1 read-write 0 Tx_EXT (x= 0~3) pin Disabled #0 1 Tx_EXT (x= 0~3) pin Enabled #1 CAPFUNCS Capture Function Selection\n 4 1 read-write 0 External Capture Mode Enabled #0 1 External Reset Mode Enabled #1 CAPIEN Timer External Capture Interrupt Enable Bit\n 5 1 read-write 0 Tx_EXT (x= 0~3) pin detection Interrupt Disabled #0 1 Tx_EXT (x= 0~3) pin detection Interrupt Enabled #1 CNTDBEN Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of Tx pin is detected with de-bounce circuit. 7 1 read-write 0 Tx (x= 0~3) pin de-bounce Disabled #0 1 Tx (x= 0~3) pin de-bounce Enabled #1 CNTPHASE Timer External Count Phase \n 0 1 read-write 0 A Falling edge of external counting pin will be counted #0 1 A Rising edge of external counting pin will be counted #1 TIMER2_INTSTS TIMER2_INTSTS Timer2 Interrupt Status Register 0x8 read-write n 0x0 0x0 TIF Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 CNT value matches the CMPDAT value #1 TWKF Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it. 1 1 read-write 0 Timer does not cause CPU wake-up #0 1 CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated #1 TIMER3_CAP TIMER3_CAP Timer3 Capture Data Register 0x30 read-write n 0x0 0x0 TIMER3_CMP TIMER3_CMP Timer3 Compare Register 0x24 read-write n 0x0 0x0 TIMER3_CNT TIMER3_CNT Timer3 Data Register 0x2C read-write n 0x0 0x0 TIMER3_CTL TIMER3_CTL Timer3 Control and Status Register 0x20 read-write n 0x0 0x0 TIMER3_EINTSTS TIMER3_EINTSTS Timer3 External Interrupt Status Register 0x38 read-write n 0x0 0x0 TIMER3_EXTCTL TIMER3_EXTCTL Timer3 External Control Register 0x34 read-write n 0x0 0x0 TIMER3_INTSTS TIMER3_INTSTS Timer3 Interrupt Status Register 0x28 read-write n 0x0 0x0 UART0 UART Register Map UART 0x0 0x0 0x4C registers n UART_ALTCTL UART_ALTCTL UART Alternate Control/Status Register 0x2C read-write n 0x0 0x0 ABRDBITS Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing "1" to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]). 17 1 read-only 0 No auto-baud rate interrupt flag is generated #0 1 Auto-baud rate interrupt flag is generated #1 ADDRDEN RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 ADDRMV Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write BRKFL UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1.\n 0 4 read-write LINRXEN LIN RX Enable Bit\n 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LINTXEN LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 RS485AAD RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485AUD RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation function (AUD) Disabled #0 1 RS-485 Auto Direction Operation function (AUD) Enabled #1 RS485NMM RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UART_BAUD UART_BAUD UART Baud Rate Divider Register 0x24 read-write n 0x0 0x0 BAUDM0 BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.133. 28 1 read-write BAUDM1 BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.133.\nNote: In IrDA mode must be operated in mode 0. 29 1 read-write BRD Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.133. 0 16 read-write EDIVM1 Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in Mode 0 and Mode 2. The detail description is shown in Table 6.133. 24 4 read-write UART_BRCOMP UART_BRCOMP UART Baud Rate Compensation Register 0x3C read-write n 0x0 0x0 BRCOMP Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit. 0 9 read-write BRCOMPDEC Baud Rate Compensation Decrease\n 31 1 read-write 0 Positive (increase one module clock) compensation for each compensated bit #0 1 Negative (decrease one module clock) compensation for each compensated bit #1 UART_DAT UART_DAT UART Receive/Transmit Buffer Register 0x0 read-write n 0x0 0x0 DAT Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead Operation:\nBy reading this register, the UART controller will return an 8-bit data received from receiver FIFO. 0 8 read-write PARITY Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit, the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.\nRead Operation:\nIf PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.\nNote: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. 8 1 read-write UART_DWKCOMP UART_DWKCOMP UART Imcoming Data Wake-up Compensation Register 0x48 read-write n 0x0 0x0 STCOMP Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode.\nNote: It is valid only when WKDATEN (UART_WKCTL[1]) is set. 0 16 read-write UART_FIFO UART_FIFO UART FIFO Control Register 0x8 read-write n 0x0 0x0 RFITL RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).\n 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RTSTRGLV nRTS Trigger Level for Auto-flow Control Use\nNote: This field is used for auto nRTS flow control. 16 4 read-write 0 nRTS Trigger Level is 1 byte #0000 1 nRTS Trigger Level is 4 bytes #0001 2 nRTS Trigger Level is 8 bytes #0010 3 nRTS Trigger Level is 14 bytes #0011 RXOFF Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RXRST RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 TXRST TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register 0x18 read-write n 0x0 0x0 ABRDIF Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic "1" when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing "1" to it. 1 1 read-write 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic "1" in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing "1" to it. 2 1 read-write 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 ADDRDETF RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing "1" to it. 3 1 read-write 0 Receiver detects a data that is not an address bit (bit 9 ='0') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 BIF Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits).\nNote: This bit can be cleared by writing "1" to it. 6 1 read-write 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing "1" to it. 5 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid "parity bit".\nNote: This bit can be cleared by writing "1" to it. 4 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXEMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RXFULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RXIDLE RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle.\n 29 1 read-only 0 RX is busy #0 1 RX is idle. (Default) #1 RXOVIF RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.\nNote: This bit can be cleared by writing "1" to it. 0 1 read-write 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RXPTR RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. 8 6 read-only TXEMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXEMPTYF Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty or the STOP bit of the last byte has been not transmitted #0 1 TX FIFO is empty and the STOP bit of the last byte has been transmitted #1 TXFULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TXOVIF TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing "1" to it. 24 1 read-write 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TXPTR TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. 16 6 read-only TXRXACT TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set. 31 1 read-only 0 TX and RX are inactive #0 1 TX and RX are active. (Default) #1 UART_FUNCSEL UART_FUNCSEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUNCSEL Function Select\n 0 2 read-write 0 UART function #00 1 LIN function #01 2 IrDA function #10 3 RS-485 function #11 TXRXDIS TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared. 3 1 read-write 0 TX and RX Enabled #0 1 TX and RX Disabled #1 UART_INTEN UART_INTEN UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit\n 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 ATOCTSEN nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). 13 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 ATORTSEN nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. 12 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 BUFERRIEN Buffer Error Interrupt Enable Bit\n 5 1 read-write 0 Buffer error interrupt Disabled #0 1 Buffer error interrupt Enabled #1 LINIEN LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode. 8 1 read-write 0 LIN bus interrupt Disabled #0 1 LIN bus interrupt Enabled #1 MODEMIEN Modem Status Interrupt Enable Bit\n 3 1 read-write 0 Modem status interrupt Disabled #0 1 Modem status interrupt Enabled #1 RDAIEN Receive Data Available Interrupt Enable Bit\n 0 1 read-write 0 Receive data available interrupt Disabled #0 1 Receive data available interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit\n 2 1 read-write 0 Receive Line Status interrupt Disabled #0 1 Receive Line Status interrupt Enabled #1 RXPDMAEN RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to '1', the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stop. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. 15 1 read-write 0 RX PDMA Disabled #0 1 RX PDMA Enabled #1 RXTOIEN RX Time-out Interrupt Enable Bit\n 4 1 read-write 0 RX time-out interrupt Disabled #0 1 RX time-out interrupt Enabled #1 THREIEN Transmit Holding Register Empty Interrupt Enable Bit\n 1 1 read-write 0 Transmit holding register empty interrupt Disabled #0 1 Transmit holding register empty interrupt Enabled #1 TOCNTEN Receive Buffer Time-out Counter Enable Bit\n 11 1 read-write 0 Receive Buffer Time-out counter Disabled #0 1 Receive Buffer Time-out counter Enabled #1 TXENDIEN Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).\n 22 1 read-write 0 Transmitter empty interrupt Disabled #0 1 Transmitter empty interrupt Enabled #1 TXPDMAEN TX PDMA Enable Bit\nThis bit can enable or disable TX PDMA service.\n 14 1 read-write 0 TX PDMA Disabled #0 1 TX PDMA Enabled.Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to '1', the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stop. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue #1 WKIEN Wake-up Interrupt Enable Bit\n 6 1 read-write 0 Wake-up Interrupt Disabled #0 1 Wake-up Interrupt Enabled #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register 0x1C read-write n 0x0 0x0 ABRINT Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.\n 31 1 read-only 0 No Auto-baud Rate interrupt is generated #0 1 The Auto-baud Rate interrupt is generated #1 BUFERRIF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]). 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUFERRINT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.\n 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 HWBUFEIF PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared. 21 1 read-only 0 No buffer error interrupt flag is generated in PDMA mode #0 1 Buffer error interrupt flag is generated in PDMA mode #1 HWBUFEINT PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.\n 29 1 read-only 0 No buffer error interrupt is generated in PDMA mode #0 1 Buffer error interrupt is generated in PDMA mode #1 HWMODIF PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]). 19 1 read-only 0 No Modem interrupt flag is generated in PDMA mode #0 1 Modem interrupt flag is generated in PDMA mode #1 HWMODINT PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.\n 27 1 read-only 0 No Modem interrupt is generated inP DMA mode #0 1 Modem interrupt is generated in PDMA mode #1 HWRLSIF PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. \nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 18 1 read-only 0 No RLS interrupt flag is generated in PDMA mode #0 1 RLS interrupt flag is generated in PDMA mode #1 HWRLSINT PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.\n 26 1 read-only 0 No RLS interrupt is generated in PDMA mode #0 1 RLS interrupt is generated in PDMA mode #1 HWTOIF PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated . \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 20 1 read-only 0 No RX time-out interrupt flag is generated in PDMA mode #0 1 RX time-out interrupt flag is generated in PDMA mode #1 HWTOINT PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.\n 28 1 read-only 0 No RX time-out interrupt is generated in PDMA mode #0 1 RX time-out interrupt is generated in PDMA mode #1 LINIF LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7]). 7 1 read-write 0 None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #0 1 At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #1 LININT LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1.\n 15 1 read-only 0 No LIN Bus interrupt is generated #0 1 The LIN Bus interrupt is generated #1 MODEMIF MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEMINT MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1\n 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated. #1 RDAIF Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]). 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDAINT Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.\n 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLSIF Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.\nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLSINT Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.\n 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 RXTOIF RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty, RX does not receive data and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.\nNote1: This bit is read only and user can read UART_DAT (RX is in active) to clear it.\nNote2: This bit is set once if RX does not receive data after this bis is clear. 4 1 read-only 0 No RX time-out interrupt flag is generated #0 1 RX time-out interrupt flag is generated #1 RXTOINT RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.\n 12 1 read-only 0 No RX time-out interrupt is generated #0 1 RX time-out interrupt is generated #1 THREIF Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THREINT Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.\n 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TXENDIF Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 22 1 read-write 0 No transmitter empty interrupt flag is generated #0 1 Transmitter empty interrupt flag is generated #1 TXENDINT Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.\n 30 1 read-only 0 No Transmitter Empty interrupt is generated #0 1 Transmitter Empty interrupt is generated #1 WKIF UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. 6 1 read-only 0 No UART wake-up interrupt flag is generated #0 1 UART wake-up interrupt flag is generated #1 WKINT UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.\n 14 1 read-only 0 No UART wake-up interrupt is generated #0 1 UART wake-up interrupt is generated #1 UART_IRDA UART_IRDA UART IrDA Control Register 0x28 read-write n 0x0 0x0 RXINV IrDA Inverse Receive Input Signal \nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal. (Default) #1 TXEN IrDA Receiver/Transmitter Selection Enable Bit\nNote: In IrDA mode, the BAUDM1 (UART_BAUD [29]) register must be disabled, the baud equation must be Clock / (16 * (BRD + 2)). 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled. (Default) #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 TXINV IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. 5 1 read-write 0 None inverse transmitting signal. (Default) #0 1 Inverse transmitting output signal #1 UART_LINCTL UART_LINCTL UART LIN Control Register 0x34 read-write n 0x0 0x0 BITERREN Bit Error Detect Enable Bit \n 12 1 read-write 0 Bit error detection function Disabled #0 1 Bit error detection function Enabled #1 BRKDETEN LIN Break Detection Enable Bit\n 10 1 read-write 0 LIN break detection Disabled #0 1 LIN break detection Enabled #1 BRKFL LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]), User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]).\nNote2: This break field length is BRKFL + 1.\n 16 4 read-write BSL LIN Break/Sync Delimiter Length \nNote: This bit used for LIN master to sending header field. 20 2 read-write 0 The LIN break/sync delimiter length is 1-bit time #00 1 The LIN break/sync delimiter length is 2-bit time #01 2 The LIN break/sync delimiter length is 3-bit time #10 3 The LIN break/sync delimiter length is 4-bit time #11 HSEL LIN Header Select \n 22 2 read-write 0 The LIN header includes "break field" #00 1 The LIN header includes "break field" and "sync field" #01 2 The LIN header includes "break field", "sync field" and "frame ID field" #10 3 Reserved #11 IDPEN LIN ID Parity Enable Bit\n 9 1 read-write 0 LIN frame ID parity Disabled #0 1 LIN frame ID parity Enabled #1 LINRXOFF LIN Receiver Disable Bit\n 11 1 read-write 0 LIN receiver Enabled #0 1 LIN receiver Disabled #1 MUTE LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in 6.16.5.10 (LIN slave mode). 4 1 read-write 0 LIN mute mode Disabled #0 1 LIN mute mode Enabled #1 PID LIN PID Bits\nIf the parity generated by hardware, user fill ID0~ID5 (PID [29:24] ), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field.\nNote1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).\nNote2: This field can be used for LIN master mode or slave mode. 24 8 read-write SENDH LIN TX Send Header Enable Bit\nThe LIN TX header can be "break field" or "break and sync field" or "break, sync and frame ID field", it is depend on setting HSEL (UART_LINCTL[23:22]).\nNote1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]); user can read/write it by setting LINTXEN (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]).\nNote2: When transmitter header field (it may be "break" or "break + sync" or "break + sync + frame ID" selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically. 8 1 read-write 0 Send LIN TX header Disabled #0 1 Send LIN TX header Enabled #1 SLVAREN LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).\nNote3: The control and interactions of this field are explained in 6.16.5.10 (Slave mode with automatic resynchronization). 2 1 read-write 0 LIN automatic resynchronization Disabled #0 1 LIN automatic resynchronization Enabled #1 SLVDUEN LIN Slave Divider Update Method Enable Bit\nNote2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) \nNote3: The control and interactions of this field are explained in 6.16.5.10 (Slave mode with automatic resynchronization). 3 1 read-write 0 UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time) #0 1 UART_BAUD is updated at the next received character. User must set the bit before checksum reception #1 SLVEN LIN Slave Mode Enable Bit\n 0 1 read-write 0 LIN slave mode Disabled #0 1 LIN slave mode Enabled #1 SLVHDEN LIN Slave Header Detection Enable Bit\n 1 1 read-write 0 LIN slave header detection Disabled #0 1 LIN slave header detection Enabled #1 UART_LINE UART_LINE UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nNote: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 6 1 read-write 0 Break Control Disabled #0 1 Break Control Enabled #1 EPE Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of "STOP Bit"\n 2 1 read-write 0 One "STOP bit" is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 "STOP bit" is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 "STOP bit" is generated in the transmitted data #1 PBE Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data. 3 1 read-write 0 Parity bit generated Disabled #0 1 Parity bit generated Enabled #1 PSS Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0, the parity bit is transmitted and checked automatically. If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]). 7 1 read-write 0 Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically #0 1 Parity bit generated and checked by software #1 RXDINV RX Data Inverted\nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. 9 1 read-write 0 Received data signal inverted Disabled #0 1 Received data signal inverted Enabled #1 SPE Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is '0' then the parity bit is transmitted and checked as 1. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 TXDINV TX Data Inverted\nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. 8 1 read-write 0 Transmitted data signal inverted Disabled #0 1 Transmitted data signal inverted Enabled #1 WLS Word Length Selection\nThis field sets UART word length.\n 0 2 read-write 0 5 bits #00 1 6 bits #01 2 7 bits #10 3 8 bits #11 UART_LINSTS UART_LINSTS UART LIN Status Register 0x38 read-write n 0x0 0x0 BITEF Bit Error Detect Status Flag \nAt TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set.\n 9 1 read-write 0 Bit error not detected #0 1 Bit error detected #1 BRKDETF LIN Break Detection Flag\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.\n 8 1 read-write 0 LIN break not detected #0 1 LIN break detected #1 SLVHDETF LIN Slave Header Detection Flag\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header ("break + sync + frame ID"), the SLVHDETF will be set whether the frame ID correct or not. 0 1 read-write 0 LIN header not detected #0 1 LIN header detected (break + sync + frame ID) #1 SLVHEF LIN Slave Header Error Flag\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include "break delimiter is too short (less than 0.5 bit time)", "frame error in sync field or Identifier field", "sync field data is not 0x55 in Non-Automatic Resynchronization mode", "sync field deviation error with Automatic Resynchronization mode", "sync field measure time-out with "Automatic Resynchronization mode" and "LIN header reception time-out".\n 1 1 read-write 0 LIN header error not detected #0 1 LIN header error detected #1 SLVIDPEF LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct.\n 2 1 read-write 0 No active #0 1 Receipted frame ID parity is not correct #1 SLVSYNCF LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit can be cleared by writing 1 to it.\nNote3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header. 3 1 read-write 0 The current character is not at LIN sync state #0 1 The current character is at LIN sync state #1 UART_MODEM UART_MODEM UART Modem Control Register 0x10 read-write n 0x0 0x0 RTS nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. 1 1 read-write 0 nRTS signal is active #0 1 nRTS signal is inactive #1 RTSACTLV nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1613 and Figure 6.1614 for UART function mode.\nNote2: Refer to Figure 6.1624 and Figure 6.1625 for RS-485 function mode.\nNote3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 9 1 read-write 0 nRTS pin output is high level active #0 1 nRTS pin output is low level active. (Default) #1 RTSSTS nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status.\n 13 1 read-only 0 nRTS pin output is low level voltage logic state #0 1 nRTS pin output is high level voltage logic state #1 UART_MODEMSTS UART_MODEMSTS UART Modem Status Register 0x14 read-write n 0x0 0x0 CTSACTLV nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 8 1 read-write 0 nCTS pin input is high level active #0 1 nCTS pin input is low level active. (Default) #1 CTSDETF Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing "1" to it. 0 1 read-write 0 nCTS input has not change state #0 1 nCTS input has change state #1 CTSSTS nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. 4 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 UART_TOUT UART_TOUT UART Time-out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time. 8 8 read-write TOIC Time-out Interrupt Comparator\n 0 8 read-write UART_WKCTL UART_WKCTL UART Wake-up Control Register 0x40 read-write n 0x0 0x0 WKCTSEN nCTS Wake-up Enable Bit\n 0 1 read-write 0 nCTS Wake-up system function Disabled #0 1 nCTS Wake-up system function Enabled, when the system is in Power-down mode, an external nCTS change will wake-up system from Power-down mode #1 WKDATEN Incoming Data Wake-up Enable Bit\n 1 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled, when the system is in Power-down mode, incoming data will wake-up system from Power-down mode #1 WKRFRTEN Received Data FIFO Reached Threshold Wake-up Enable Bit\nPower-down mode. 2 1 read-write 0 Received Data FIFO reached threshold wake-up system function Disabled #0 1 Received Data FIFO reached threshold wake-up system function Enabled, when the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from #1 WKRS485EN RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nPower-down mode, RS-485 Address Match will wake-up system from Power-down mode.\nNote: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode\nand ADDRDEN (UART_ALTCTL[15]) is set to 1. 3 1 read-write 0 RS-485 Address Match (AAD mode) wake-up system function Disabled #0 1 RS-485 Address Match (AAD mode) wake-up system function Enabled, when the system is in #1 WKTOUTEN Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. 4 1 read-write 0 Received Data FIFO reached threshold time-out wake-up system function Disabled #0 1 Received Data FIFO reached threshold time-out wake-up system function Enabled, when the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake-up system from Power-down mode #1 UART_WKSTS UART_WKSTS UART Wake-up Status Register 0x44 read-write n 0x0 0x0 CTSWKF nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 0 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKF Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Incoming Data wake-up #1 RFRTWKF Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up #1 RS485WKF RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up #1 TOUTWKF Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 4 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO reached threshold time-out wake-up #1 UI2C0 UI2C Register Map UI2C 0x0 0x0 0x4 registers n 0x2C 0xC registers n 0x44 0x24 registers n 0x8 0x4 registers n 0x88 0x8 registers n UI2C_ADDRMSK0 UI2C_ADDRMSK0 USCI Device Address Mask Register 0 0x4C read-write n 0x0 0x0 ADDRMSK USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 0 10 read-write 0 Mask Disabled (the received corresponding register bit should be exact the same as address register.) 0 1 Mask Enabled (the received corresponding address bit is don't care.) 1 UI2C_ADDRMSK1 UI2C_ADDRMSK1 USCI Device Address Mask Register 1 0x50 read-write n 0x0 0x0 UI2C_ADMAT UI2C_ADMAT I2C Slave Match Address Register 0x88 read-write n 0x0 0x0 ADMAT0 USCI Address 0 Match Status Register\nWhen address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 0 1 read-write ADMAT1 USCI Address 1 Match Status Register\nWhen address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 1 1 read-write UI2C_BRGEN UI2C_BRGEN USCI Baud Rate Generator Register 0x8 read-write n 0x0 0x0 CLKDIV Clock Divider\nNote1: I2C function, the minimum value of CLKDIV is 8.\nNote2: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UI2C_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (UI2C_PROTCTL[24:16]) to calculate the precise baud rate. 16 10 read-write DSCNT Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value. 10 5 read-write PDSCNT Pre-divider for Sample Counter\n 8 2 read-write PTCLKSEL Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK). \n 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK). \n 0 1 read-write 0 Peripheral device clock fPCLK #0 1 Reserved #1 SPCLKSEL Sample Clock Source Selection\nThis bit field is used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.\n 2 2 read-write 0 fSAMP_CLK = fDIV_CLK #00 1 fSAMP_CLK = fPROT_CLK #01 2 fSAMP_CLK = fSCLK #10 3 fSAMP_CLK = fREF_CLK #11 TMCNTEN Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.\n 4 1 read-write 0 Time measurement counter is Disabled #0 1 Time measurement counter is Enabled #1 TMCNTSRC Time Measurement Counter Clock Source Selection\n 5 1 read-write 0 Time measurement counter with fPROT_CLK #0 1 Time measurement counter with fDIV_CLK #1 UI2C_CTL UI2C_CTL USCI Control Register 0x0 read-write n 0x0 0x0 FUNMODE Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state #000 1 The SPI protocol is selected #001 2 The UART protocol is selected #010 4 The I2C protocol is selected #100 UI2C_DEVADDR0 UI2C_DEVADDR0 USCI Device Address Register 0 0x44 read-write n 0x0 0x0 DEVADDR Device Address\nIn I2C protocol, this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit. Then the second address byte is also compared to DEVADDR[7:0].\nNote: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode. 0 10 read-write UI2C_DEVADDR1 UI2C_DEVADDR1 USCI Device Address Register 1 0x48 read-write n 0x0 0x0 UI2C_LINECTL UI2C_LINECTL USCI Line Control Register 0x2C read-write n 0x0 0x0 DWIDTH Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].\nNote: In I2C protocol, the length must be configured as 8 bits. 8 4 read-write LSB LSB First Transmission Selection\n 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 UI2C_PROTCTL UI2C_PROTCTL USCI Protocol Control Register 0x5C read-write n 0x0 0x0 AA Assert Acknowledge Control\n 1 1 read-write ADDR10EN Address 10-bit Function Enable Bit\n 4 1 read-write 0 Address match 10 bit function is disabled #0 1 Address match 10 bit function is enabled #1 GCFUNC General Call Function\n 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 MONEN Monitor Mode Enable Bit\nThis bit enables monitor mode. In monitor mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.\nNote: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line. 9 1 read-write 0 The monitor mode is disabled #0 1 The monitor mode is enabled #1 PROTEN I2C Protocol Enable Bit\n 31 1 read-write 0 I2C Protocol disable #0 1 I2C Protocol enable #1 PTRG I2C Protocol Trigger\nWhen a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled.\n 5 1 read-write 0 I2C's stretch disabled and the I2C protocol function will go ahead #0 1 I2C's stretch active #1 SCLOUTEN SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low. This monitor will pull SCL to low until it has had time to respond to an I2C interrupt.\n 8 1 read-write 0 SCL output will be forced high due to open drain mechanism #0 1 I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt #1 STA I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 3 1 read-write STO I2C STOP Control\n 2 1 read-write TOCNT Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. \nNote: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode. 16 10 read-write UI2C_PROTIEN UI2C_PROTIEN USCI Protocol Interrupt Enable Register 0x60 read-write n 0x0 0x0 ACKIEN Acknowledge Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.\n 6 1 read-write 0 The acknowledge interrupt is disabled #0 1 The acknowledge interrupt is enabled #1 ARBLOIEN Arbitration Lost Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected.\n 4 1 read-write 0 The arbitration lost interrupt is disabled #0 1 The arbitration lost interrupt is enabled #1 ERRIEN Error Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])).\n 5 1 read-write 0 The error interrupt is disabled #0 1 The error interrupt is enabled #1 NACKIEN Non - Acknowledge Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master.\n 3 1 read-write 0 The non - acknowledge interrupt is disabled #0 1 The non - acknowledge interrupt is enabled #1 STARIEN Start Condition Received Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if a start condition is detected.\n 1 1 read-write 0 The start condition interrupt is disabled #0 1 The start condition interrupt is enabled #1 STORIEN Stop Condition Received Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if a stop condition is detected.\n 2 1 read-write 0 The stop condition interrupt is disabled #0 1 The stop condition interrupt is enabled #1 TOIEN Time-out Interrupt Enable Control\nIn I2C protocol, this bit enables the interrupt generation in case of a time-out event.\n 0 1 read-write 0 The time-out interrupt is disabled #0 1 The time-out interrupt is enabled #1 UI2C_PROTSTS UI2C_PROTSTS USCI Protocol Status Register 0x64 read-write n 0x0 0x0 ACKIF Acknowledge Received Interrupt Flag\nIt is cleared by software writing one into this bit 13 1 read-write 0 An acknowledge has not been received #0 1 An acknowledge has been received #1 ARBLOIF Arbitration Lost Interrupt Flag\nIt is cleared by software writing one into this bit 11 1 read-write 0 An arbitration has not been lost #0 1 An arbitration has been lost #1 ERRIF Error Interrupt Flag\nIt is cleared by software writing one into this bit\nNote: This bit is set when slave mode, user must write one into STO register to the defined "not addressed" slave mode. 12 1 read-write 0 An I2C error has not been detected #0 1 An I2C error has been detected #1 NACKIF Non - Acknowledge Received Interrupt Flag\nIt is cleared by software writing one into this bit 10 1 read-write 0 A non - acknowledge has not been received #0 1 A non - acknowledge has been received #1 ONBUSY On Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected\n 6 1 read-write 0 The bus is IDLE (both SCLK and SDA High) #0 1 The bus is busy #1 SLAREAD Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware. 15 1 read-write 0 A slave read request has not been detected #0 1 A slave read request has been detected #1 SLASEL Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware. 14 1 read-write 0 The device is not selected as slave #0 1 The device is selected as slave #1 STARIF Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode. However, this bit also indicates that a repeated start condition has been detected on slave mode.\nIt is cleared by software writing one into this bit 8 1 read-write 0 A start condition has not yet been detected #0 1 A start condition has been detected #1 STORIF Stop Condition Received Interrupt Flag\nIt is cleared by software writing one into this bit 9 1 read-write 0 A stop condition has not yet been detected #0 1 A stop condition has been detected #1 TOIF Time-out Interrupt Flag\nNote: It is cleared by software writing one into this bit 5 1 read-write 0 A time-out interrupt status has not occurred #0 1 A time-out interrupt status has occurred #1 WKAKDONE Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release when WKF is set. 16 1 read-write 0 The ACK bit cycle of address match frame isn't done #0 1 The ACK bit cycle of address match frame is done in power-down #1 WRSTSWK Read/Write Status Bit in Address Wakeup Frame\n 17 1 read-write 0 Write command be record on the address match wakeup frame #0 1 Read command be record on the address match wakeup frame #1 UI2C_RXDAT UI2C_RXDAT USCI Receive Data Register 0x34 read-only n 0x0 0x0 RXDAT Received Data\nThis bit field monitors the received data which stored in receive data buffer. 0 16 read-only UI2C_TMCTL UI2C_TMCTL I2C Timing Configure Control Register 0x8C read-write n 0x0 0x0 HTCTL Hold Time Configure Control Register\nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode.\n 6 6 read-write STCTL Setup Time Configure Control Register\nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode..\n 0 6 read-write UI2C_TXDAT UI2C_TXDAT USCI Transmit Data Register 0x30 write-only n 0x0 0x0 TXDAT Transmit Data\nSoftware can use this bit field to write 8-bit transmit data for transmission. 0 16 write-only UI2C_WKCTL UI2C_WKCTL USCI Wake-up Control Register 0x54 read-write n 0x0 0x0 WKADDREN Wake-up Address Match Enable Bit\n 1 1 read-write 0 The chip is woken up according data toggle #0 1 The chip is woken up according address match #1 WKEN Wake-up Enable Bit\n 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 UI2C_WKSTS UI2C_WKSTS USCI Wake-up Status Register 0x58 read-write n 0x0 0x0 WKF Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write USBD USBD Register Map USBD 0x0 0x0 0x1C registers n 0x500 0x80 registers n 0x88 0xC registers n ATTR USBD_ATTR USB Device Bus Status and Attribution Register 0x10 read-write n 0x0 0x0 BYTEM CPU Access USB SRAM Size Mode Selection\n 10 1 read-write 0 Word mode: The size of the transfer from CPU to USB SRAM can be Word only #0 1 Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only #1 DPPUEN Pull-up Resistor on USB_DP Enable Bit\n 8 1 read-write 0 Pull-up resistor in USB_D+ bus Disabled #0 1 Pull-up resistor in USB_D+ bus Active #1 L1RESUME LPM L1 Resume \nNote: This bit is read only. 13 1 read-write 0 Bus no LPM L1 state resume #0 1 LPM L1 state Resume from LPM L1 state suspend #1 L1SUSPEND LPM L1 Suspend \nNote: This bit is read only. 12 1 read-write 0 Bus no L1 state suspend #0 1 This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged #1 LPMACK LPM Token Acknowledge Enable Bit\n 11 1 read-write 0 the valid LPM Token will be NYET #0 1 the valid LPM Token will be ACK #1 PHYEN PHY Transceiver Function Enable Bit\n 4 1 read-write 0 PHY transceiver function Disabled #0 1 PHY transceiver function Enabled #1 PWRDN Power-down PHY Transceiver, Low Active\n 9 1 read-write 0 Power donw related circuit of PHY transceiver #0 1 Turn on related circuit of PHY transceiver #1 RESUME Resume Status\nNote: This bit is read only. 2 1 read-write 0 No bus resume #0 1 Resume from suspend #1 RWAKEUP Remote Wake-up\n 5 1 read-write 0 Release the USB bus from K state #0 1 Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up #1 SOFITH Start of Frame Interrupt Threshold Control Bits\n 16 3 read-write 0 every SOF trigger one SOF interrupt #000 1 every 2 SOFs trigger one SOF interrupt #001 2 every 4 SOFs trigger one SOF interrupt #010 3 every 8 SOFs trigger one SOF interrupt #011 4 every 16 SOFs trigger one SOF interrupt #100 5 every 32 SOFs trigger one SOF interrupt #101 6 every 64 SOFs trigger one SOF interrupt #110 7 every 128 SOFs trigger one SOF interrupt #111 SUSPEND Suspend Status\nNote: This bit is read only. 1 1 read-write 0 Bus no suspend #0 1 Bus idle more than 3ms, either cable is plugged off or host is sleeping #1 TOUT Time-out Status\nNote: This bit is read only. 3 1 read-write 0 No time-out #0 1 No Bus response more than 18 bits time #1 USBEN USB Controller Enable Bit\n 7 1 read-write 0 USB Controller Disabled #0 1 USB Controller Enabled #1 USBRST USB Reset Status\nNote: This bit is read only. 0 1 read-write 0 Bus no reset #0 1 Bus reset when SE0 (single-ended 0) more than 2.5us #1 BUFSEG0 USBD_BUFSEG0 Endpoint 0 Buffer Segmentation Register 0x500 read-write n 0x0 0x0 BUFSEG Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address. The effective starting address of the endpoint is\nUSBD_SRAM address + { BUFSEG[9:3], 3'b000}\nRefer to the section 6.19.5.7 for the endpoint SRAM structure and its description. 3 7 read-write BUFSEG1 USBD_BUFSEG1 Endpoint 1 Buffer Segmentation Register 0x510 read-write n 0x0 0x0 BUFSEG2 USBD_BUFSEG2 Endpoint 2 Buffer Segmentation Register 0x520 read-write n 0x0 0x0 BUFSEG3 USBD_BUFSEG3 Endpoint 3 Buffer Segmentation Register 0x530 read-write n 0x0 0x0 BUFSEG4 USBD_BUFSEG4 Endpoint 4 Buffer Segmentation Register 0x540 read-write n 0x0 0x0 BUFSEG5 USBD_BUFSEG5 Endpoint 5 Buffer Segmentation Register 0x550 read-write n 0x0 0x0 BUFSEG6 USBD_BUFSEG6 Endpoint 6 Buffer Segmentation Register 0x560 read-write n 0x0 0x0 BUFSEG7 USBD_BUFSEG7 Endpoint 7 Buffer Segmentation Register 0x570 read-write n 0x0 0x0 CFG0 USBD_CFG0 Endpoint 0 Configuration Register 0x508 read-write n 0x0 0x0 CSTALL Clear STALL Response\n 9 1 read-write 0 Disable the device to clear the STALL handshake in setup stage #0 1 Clear the device to response STALL handshake in setup stage #1 DSQSYNC Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token base on the bit. 7 1 read-write 0 DATA0 PID #0 1 DATA1 PID #1 EPNUM Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint 0 4 read-write ISOCH Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint, no handshake.\n 4 1 read-write 0 No Isochronous endpoint #0 1 Isochronous endpoint #1 STATE Endpoint STATE\n 5 2 read-write 0 Endpoint is Disabled #00 1 Out endpoint #01 2 IN endpoint #10 3 Undefined #11 CFG1 USBD_CFG1 Endpoint 1 Configuration Register 0x518 read-write n 0x0 0x0 CFG2 USBD_CFG2 Endpoint 2 Configuration Register 0x528 read-write n 0x0 0x0 CFG3 USBD_CFG3 Endpoint 3 Configuration Register 0x538 read-write n 0x0 0x0 CFG4 USBD_CFG4 Endpoint 4 Configuration Register 0x548 read-write n 0x0 0x0 CFG5 USBD_CFG5 Endpoint 5 Configuration Register 0x558 read-write n 0x0 0x0 CFG6 USBD_CFG6 Endpoint 6 Configuration Register 0x568 read-write n 0x0 0x0 CFG7 USBD_CFG7 Endpoint 7 Configuration Register 0x578 read-write n 0x0 0x0 CFGP0 USBD_CFGP0 Endpoint 0 Set Stall and Clear In/Out Ready Control Register 0x50C read-write n 0x0 0x0 CLRRDY Clear Ready\nFor IN token, write '1' to clear the IN token had ready to transmit the data to USB.\nFor OUT token, write '1' to clear the OUT token had ready to receive the data from USB.\nThis bit is write 1 only and is always 0 when it is read back. 0 1 read-write SSTALL Set STALL\n 1 1 read-write 0 Disable the device to response STALL #0 1 Set the device to respond STALL automatically #1 CFGP1 USBD_CFGP1 Endpoint 1 Set Stall and Clear In/Out Ready Control Register 0x51C read-write n 0x0 0x0 CFGP2 USBD_CFGP2 Endpoint 2 Set Stall and Clear In/Out Ready Control Register 0x52C read-write n 0x0 0x0 CFGP3 USBD_CFGP3 Endpoint 3 Set Stall and Clear In/Out Ready Control Register 0x53C read-write n 0x0 0x0 CFGP4 USBD_CFGP4 Endpoint 4 Set Stall and Clear In/Out Ready Control Register 0x54C read-write n 0x0 0x0 CFGP5 USBD_CFGP5 Endpoint 5 Set Stall and Clear In/Out Ready Control Register 0x55C read-write n 0x0 0x0 CFGP6 USBD_CFGP6 Endpoint 6 Set Stall and Clear In/Out Ready Control Register 0x56C read-write n 0x0 0x0 CFGP7 USBD_CFGP7 Endpoint 7 Set Stall and Clear In/Out Ready Control Register 0x57C read-write n 0x0 0x0 EPSTS USBD_EPSTS USB Device Endpoint Status Register 0xC read-only n 0x0 0x0 EPSTS0 Endpoint 0 Status\nThese bits are used to indicate the current status of this endpoint\n 8 3 read-only 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 EPSTS1 Endpoint 1 Status\nThese bits are used to indicate the current status of this endpoint\n 11 3 read-only 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 EPSTS2 Endpoint 2 Status\nThese bits are used to indicate the current status of this endpoint\n 14 3 read-only 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 EPSTS3 Endpoint 3 Status\nThese bits are used to indicate the current status of this endpoint\n 17 3 read-only 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 EPSTS4 Endpoint 4 Status\nThese bits are used to indicate the current status of this endpoint\n 20 3 read-only 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 EPSTS5 Endpoint 5 Status\nThese bits are used to indicate the current status of this endpoint\n 23 3 read-only 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 EPSTS6 Endpoint 6 Status\nThese bits are used to indicate the current status of this endpoint\n 26 3 read-only 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 EPSTS7 Endpoint 7 Status\nThese bits are used to indicate the current status of this endpoint\n 29 3 read-only 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 OV Overrun\nIt indicates that the received data is over the maximum payload number or not.\n 7 1 read-only 0 No overrun #0 1 Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes #1 FADDR USBD_FADDR USB Device Function Address Register 0x8 read-write n 0x0 0x0 FADDR USB Device Function Address 0 7 read-write FN USBD_FN USB Frame Number Register 0x8C read-only n 0x0 0x0 FN Frame Number\nThese bits contain the 11-bits frame number in the last received SOF packet. 0 11 read-only INTEN USBD_INTEN USB Device Interrupt Enable Register 0x0 read-write n 0x0 0x0 BUSIEN Bus Event Interrupt Enable Bit\n 0 1 read-write 0 BUS event interrupt Disabled #0 1 BUS event interrupt Enabled #1 INNAKEN Active NAK Function and Its Status in IN Token\n 15 1 read-write 0 When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS register, so that the USB interrupt event will not be asserted #0 1 IN NAK status will be updated to USBD_EPSTS register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token #1 NEVWKIEN USB No-event-wake-up Interrupt Enable Bit\n 3 1 read-write 0 No-event-wake-up Interrupt Disabled #0 1 No-event-wake-up Interrupt Enabled #1 SOFIEN Start of Frame Interrupt Enable Bit\n 4 1 read-write 0 SOF Interrupt Disabled #0 1 SOF Interrupt Enabled #1 USBIEN USB Event Interrupt Enable Bit\n 1 1 read-write 0 USB event interrupt Disabled #0 1 USB event interrupt Enabled #1 VBDETIEN VBUS Detection Interrupt Enable Bit\n 2 1 read-write 0 VBUS detection Interrupt Disabled #0 1 VBUS detection Interrupt Enabled #1 WKEN Wake-up Function Enable Bit\n 8 1 read-write 0 USB wake-up function Disabled #0 1 USB wake-up function Enabled #1 INTSTS USBD_INTSTS USB Device Interrupt Event Status Register 0x4 read-write n 0x0 0x0 BUSIF BUS Interrupt Status\nThe BUS event means that there is one of the suspense or the resume function in the bus.\n 0 1 read-write 0 No BUS event occurred #0 1 Bus event occurred; check USBD_ATTR[3:0] and USBD_ATTR[13:12] to know which kind of bus event was occurred, cleared by write 1 to USBD_INTSTS[0] #1 EPEVT0 Endpoint 0's USB Event Status\n 16 1 read-write 0 No event occurred in endpoint 0 #0 1 USB event occurred on Endpoint 0, check USBD_EPSTS[10:8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[16] or USBD_INTSTS[1] #1 EPEVT1 Endpoint 1's USB Event Status\n 17 1 read-write 0 No event occurred in endpoint 1 #0 1 USB event occurred on Endpoint 1, check USBD_EPSTS[13:11] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[17] or USBD_INTSTS[1] #1 EPEVT2 Endpoint 2's USB Event Status\n 18 1 read-write 0 No event occurred in endpoint 2 #0 1 USB event occurred on Endpoint 2, check USBD_EPSTS[16:14] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[18] or USBD_INTSTS[1] #1 EPEVT3 Endpoint 3's USB Event Status\n 19 1 read-write 0 No event occurred in endpoint 3 #0 1 USB event occurred on Endpoint 3, check USBD_EPSTS[19:17] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[19] or USBD_INTSTS[1] #1 EPEVT4 Endpoint 4's USB Event Status\n 20 1 read-write 0 No event occurred in endpoint 4 #0 1 USB event occurred on Endpoint 4, check USBD_EPSTS[22:20] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[20] or USBD_INTSTS[1] #1 EPEVT5 Endpoint 5's USB Event Status\n 21 1 read-write 0 No event occurred in endpoint 5 #0 1 USB event occurred on Endpoint 5, check USBD_EPSTS[25:23] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[21] or USBD_INTSTS[1] #1 EPEVT6 Endpoint 6's USB Event Status\n 22 1 read-write 0 No event occurred in endpoint 6 #0 1 USB event occurred on Endpoint 6, check USBD_EPSTS[28:26] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[22] or USBD_INTSTS[1] #1 EPEVT7 Endpoint 7's USB Event Status\n 23 1 read-write 0 No event occurred in endpoint 7 #0 1 USB event occurred on Endpoint 7, check USBD_EPSTS[31:29] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[23] or USBD_INTSTS[1] #1 NEVWKIF No-event-wake-up Interrupt Status\n 3 1 read-write 0 NEVWK event does not occur #0 1 No-event-wake-up event occurred, cleared by write 1 to USBD_INTSTS[3] #1 SETUP Setup Event Status\n 31 1 read-write 0 No Setup event #0 1 Setup event occurred, cleared by write 1 to USBD_INTSTS[31] #1 SOFIF Start of Frame Interrupt Status\n 4 1 read-write 0 SOF event does not occur #0 1 SOF event occurred, cleared by write 1 to USBD_INTSTS[4] #1 USBIF USB Event Interrupt Status\nThe USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.\n 1 1 read-write 0 No USB event occurred #0 1 USB event occurred, check EPSTS0~5[2:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[1] or EPSTS0~7 and SETUP (USBD_INTSTS[31]) #1 VBDETIF VBUS Detection Interrupt Status\n 2 1 read-write 0 There is not attached/detached event in the USB #0 1 There is attached/detached event in the USB bus and it is cleared by write 1 to USBD_INTSTS[2] #1 LPMATTR USBD_LPMATTR USB LPM Attribution Register 0x88 read-only n 0x0 0x0 LPMBESL LPM Best Effort Service Latency\nThese bits contain the BESL value received with last ACK LPM Token\n 4 4 read-only 0 125us #0000 1 150us #0001 2 200us #0010 3 300us #0011 4 400us #0100 5 500us #0101 6 1000us #0110 7 2000us #0111 8 3000us #1000 9 4000us #1001 10 5000us #1010 11 6000us #1011 12 7000us #1100 13 8000us #1101 14 9000us #1110 15 10000us #1111 LPMLINKSTS LPM Link State\nThese bits contain the bLinkState received with last ACK LPM Token\n 0 4 read-only 0 Reserve #0000 1 L1 (Sleep) #0001 LPMRWAKUP LPM Remote Wakeup\nThis bit contains the bRemoteWake value received with last ACK LPM Token 8 1 read-only MXPLD0 USBD_MXPLD0 Endpoint 0 Maximal Payload Register 0x504 read-write n 0x0 0x0 MXPLD Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.\n(1) When the register is written by CPU, \nFor IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.\nFor OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.\n(2) When the register is read by CPU,\nFor IN token, the value of MXPLD is indicated by the data length be transmitted to host\nFor OUT token, the value of MXPLD is indicated the actual data length receiving from host.\nNote: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 0 10 read-write MXPLD1 USBD_MXPLD1 Endpoint 1 Maximal Payload Register 0x514 read-write n 0x0 0x0 MXPLD2 USBD_MXPLD2 Endpoint 2 Maximal Payload Register 0x524 read-write n 0x0 0x0 MXPLD3 USBD_MXPLD3 Endpoint 3 Maximal Payload Register 0x534 read-write n 0x0 0x0 MXPLD4 USBD_MXPLD4 Endpoint 4 Maximal Payload Register 0x544 read-write n 0x0 0x0 MXPLD5 USBD_MXPLD5 Endpoint 5 Maximal Payload Register 0x554 read-write n 0x0 0x0 MXPLD6 USBD_MXPLD6 Endpoint 6 Maximal Payload Register 0x564 read-write n 0x0 0x0 MXPLD7 USBD_MXPLD7 Endpoint 7 Maximal Payload Register 0x574 read-write n 0x0 0x0 SE0 USBD_SE0 USB Device Drive SE0 Control Register 0x90 read-write n 0x0 0x0 SE0 Drive Single Ended Zero in USB Bus\nThe Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.\n 0 1 read-write 0 Normal operation #0 1 Force USB PHY transceiver to drive SE0 #1 STBUFSEG USBD_STBUFSEG Setup Token Buffer Segmentation Register 0x18 read-write n 0x0 0x0 STBUFSEG SETUP Token Buffer Segmentation\nNote: It is used for SETUP token only. 3 7 read-write VBUSDET USBD_VBUSDET USB Device VBUS Detection Register 0x14 read-only n 0x0 0x0 VBUSDET Device VBUS Detection\n 0 1 read-only 0 Controller is not attached to the USB host #0 1 Controller is attached to the USB host #1 USPI0 USPI Register Map USPI 0x0 0x0 0xC registers n 0x10 0x4 registers n 0x20 0x4 registers n 0x28 0x1C registers n 0x54 0x14 registers n USPI_BRGEN USPI_BRGEN USCI Baud Rate Generator Register 0x8 read-write n 0x0 0x0 CLKDIV Clock Divider\n 16 10 read-write PTCLKSEL Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK). \n 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK). \n 0 1 read-write 0 Peripheral device clock fPCLK #0 1 Reserved #1 SPCLKSEL Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor.\n 2 2 read-write 0 fDIV_CLK #00 1 fPROT_CLK #01 2 fSCLK #10 3 fREF_CLK #11 TMCNTEN Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.\n 4 1 read-write 0 Time measurement counter Disabled #0 1 Time measurement counter Enabled #1 TMCNTSRC Time Measurement Counter Clock Source Selection\n 5 1 read-write 0 Time measurement counter with fPROT_CLK #0 1 Time measurement counter with fDIV_CLK #1 USPI_BUFCTL USPI_BUFCTL USCI Transmit/Receive Buffer Control Register 0x38 read-write n 0x0 0x0 RXCLR Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle. 15 1 read-write 0 No effect #0 1 The receive buffer is cleared. Should only be used while the buffer is not taking part in data traffic #1 RXOVIEN Receive Buffer Overrun Interrupt Enable Control\n 14 1 read-write 0 Receive overrun interrupt Disabled #0 1 Receive overrun interrupt Enabled #1 RXRST Receive Reset\nNote: It is cleared automatically after one PCLK cycle. 17 1 read-write 0 No effect #0 1 Reset the receive-related counters, state machine, and the content of receive shift register and data buffer #1 TXCLR Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle. 7 1 read-write 0 No effect #0 1 The transmit buffer is cleared. Should only be used while the buffer is not taking part in data traffic #1 TXRST Transmit Reset\n 16 1 read-write 0 No effect #0 1 Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer #1 TXUDRIEN Slave Transmit Under Run Interrupt Enable Bit\n 6 1 read-write 0 Transmit under-run interrupt Disabled #0 1 Transmit under-run interrupt Enabled #1 USPI_BUFSTS USPI_BUFSTS USCI Transmit/Receive Buffer Status Register 0x3C read-write n 0x0 0x0 RXEMPTY Receive Buffer Empty Indicator \n 0 1 read-write 0 Receive buffer is not empty #0 1 Receive buffer is empty #1 RXFULL Receive Buffer Full Indicator\n 1 1 read-write 0 Receive buffer is not full #0 1 Receive buffer is full #1 RXOVIF Receive Buffer Over-run Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit.\n 3 1 read-write 0 A receive buffer overrun event has not been detected #0 1 A receive buffer overrun event has been detected #1 TXEMPTY Transmit Buffer Empty Indicator\n 8 1 read-write 0 Transmit buffer is not empty #0 1 Transmit buffer is empty and available for the next transmission datum #1 TXFULL Transmit Buffer Full Indicator\n 9 1 read-write 0 Transmit buffer is not full #0 1 Transmit buffer is full #1 TXUDRIF Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit\n 11 1 read-write 0 A transmit buffer under-run event has not been detected #0 1 A transmit buffer under-run event has been detected #1 USPI_CLKIN USPI_CLKIN USCI Input Clock Signal Configuration Register 0x28 read-write n 0x0 0x0 SYNCSEL Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol, we suggest this bit should be set as 0. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 USPI_CTL USPI_CTL USCI Control Register 0x0 read-write n 0x0 0x0 FUNMODE Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 0x0 to FUNMODE.\nNote: Other bit combinations are reserved. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state 0x0 1 The SPI protocol is selected 0x1 2 The UART protocol is selected 0x2 4 The I2C protocol is selected 0x4 USPI_CTLIN0 USPI_CTLIN0 USCI Input Control Signal Configuration Register 0 0x20 read-write n 0x0 0x0 ININV Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\n 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol, we suggest this bit should be set as 0. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 USPI_DATIN0 USPI_DATIN0 USCI Input Data Signal Configuration Register 0 0x10 read-write n 0x0 0x0 ININV Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol, we suggest this bit should be set as 0. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol, we suggest this bit should be set as 0. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 USPI_INTEN USPI_INTEN USCI Interrupt Enable Register 0x4 read-write n 0x0 0x0 RXENDIEN Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event.\n 4 1 read-write 0 The receive end interrupt Disabled #0 1 The receive end interrupt Enabled #1 RXSTIEN Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event.\n 3 1 read-write 0 The receive start interrupt Disabled #0 1 The receive start interrupt Enabled #1 TXENDIEN Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event.\n 2 1 read-write 0 The transmit finish interrupt Disabled #0 1 The transmit finish interrupt Enabled #1 TXSTIEN Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event.\n 1 1 read-write 0 The transmit start interrupt Disabled #0 1 The transmit start interrupt Enabled #1 USPI_LINECTL USPI_LINECTL USCI Line Control Register 0x2C read-write n 0x0 0x0 CTLOINV Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol. In SPI protocol, the control signal means slave select signal. 7 1 read-write 0 No effect #0 1 The control signal will be inverted before its output #1 DATOINV Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin.\n 5 1 read-write 0 Data output level is not inverted #0 1 Data output level is inverted #1 DWIDTH Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0]. 8 4 read-write LSB LSB First Transmission Selection\n 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 USPI_PDMACTL USPI_PDMACTL USCI PDMA Control Register 0x40 read-write n 0x0 0x0 PDMAEN PDMA Mode Enable Bit\n 3 1 read-write 0 PDMA function Disabled #0 1 PDMA function Enabled #1 PDMARST PDMA Reset\n 0 1 read-write 0 No effect #0 1 Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically #1 RXPDMAEN PDMA Receive Channel Available\n 2 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TXPDMAEN PDMA Transmit Channel Available\n 1 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 USPI_PROTCTL USPI_PROTCTL USCI Protocol Control Register 0x5C read-write n 0x0 0x0 AUTOSS Automatic Slave Select Function Enable (Master Only)\n 3 1 read-write 0 Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit #0 1 Slave select signal will be generated automatically. The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished #1 PROTEN SPI Protocol Enable Bit\n 31 1 read-write 0 SPI Protocol Disabled #0 1 SPI Protocol Enabled #1 SCLKMODE Serial Bus Clock Mode\nThis bit field defines the SCLK idle status, data transmit, and data receive edge.\n 6 2 read-write SLAVE Slave Mode Selection\n 0 1 read-write 0 Master mode #0 1 Slave mode #1 SLV3WIRE Slave 3-wire Mode Selection (Slave Only)\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode.\n 1 1 read-write 0 4-wire bi-direction interface #0 1 3-wire bi-direction interface #1 SLVTOCNT Slave Mode Time-out Period (Slave Only)\nIn Slave mode, this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event. Writing 0x0 into this bit field will disable the Slave time-out function.\nExample: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK. 16 10 read-write SS Slave Select Control (Master Only)\nIf AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select back to inactive state.\nNote: In SPI protocol, the internal slave select signal is active high. 2 1 read-write SUSPITV Suspend Interval (Master Only)\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle\nExample:\n 8 4 read-write TSMSEL Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nOther values are reserved.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically. 12 3 read-write 0 Full-duplex SPI 0x0 4 Half-duplex SPI 0x4 TXUDRPOL Transmit Under-run Data Polarity (for Slave)\nThis bit defines the transmitting data level when no data is available for transferring. \n 28 1 read-write 0 The output data level is 0 if TX under run event occurs #0 1 The output data level is 1 if TX under run event occurs #1 USPI_PROTIEN USPI_PROTIEN USCI Protocol Interrupt Enable Register 0x60 read-write n 0x0 0x0 SLVBEIEN Slave Mode Bit Count Error Interrupt Enable Control\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]). Bit count error event occurs.\n 3 1 read-write 0 The Slave mode bit count error interrupt Disabled #0 1 The Slave mode bit count error interrupt Enabled #1 SLVTOIEN Slave Time-out Interrupt Enable Control\nIn SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event.\n 2 1 read-write 0 The Slave time-out interrupt Disabled #0 1 The Slave time-out interrupt Enabled #1 SSACTIEN Slave Select Active Interrupt Enable Control\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active.\n 1 1 read-write 0 Slave select active interrupt generation Disabled #0 1 Slave select active interrupt generation Enabled #1 SSINAIEN Slave Select Inactive Interrupt Enable Control\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive.\n 0 1 read-write 0 Slave select inactive interrupt generation Disabled #0 1 Slave select inactive interrupt generation Enabled #1 USPI_PROTSTS USPI_PROTSTS USCI Protocol Status Register 0x64 read-write n 0x0 0x0 BUSY Busy Status (Read Only)\n 17 1 read-only 0 SPI is in idle state #0 1 SPI is in busy state #1 RXENDIF Receive End Interrupt Flag\nNote: It is cleared by software writes 1 to this bit 4 1 read-write 0 Receive end event does not occur #0 1 Receive end event occurs #1 RXSTIF Receive Start Interrupt Flag\nNote: It is cleared by software writes 1 to this bit 3 1 read-write 0 Receive start event does not occur #0 1 Receive start event occurs #1 SLVBEIF Slave Bit Count Error Interrupt Flag (for Slave Only)\nNote: It is cleared by software writes 1 to this bit. 6 1 read-write 0 Slave bit count error event does not occur #0 1 Slave bit count error event occurs #1 SLVTOIF Slave Time-out Interrupt Flag (for Slave Only)\nNote: It is cleared by software writes 1 to this bit 5 1 read-write 0 Slave time-out event does not occur #0 1 Slave time-out event occurs #1 SLVUDR Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1. This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not.\n 18 1 read-only 0 Slave transmit under run event does not occur #0 1 Slave transmit under run event occurs #1 SSACTIF Slave Select Active Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit\nNote: The internal slave select signal is active high. 9 1 read-write 0 The slave select signal has not changed to active #0 1 The slave select signal has changed to active #1 SSINAIF Slave Select Inactive Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit\nNote: The internal slave select signal is active high. 8 1 read-write 0 The slave select signal has not changed to inactive #0 1 The slave select signal has changed to inactive #1 SSLINE Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus.\n 16 1 read-only 0 The slave select line status is 0 #0 1 The slave select line status is 1 #1 TXENDIF Transmit End Interrupt Flag\nNote: It is cleared by software writes 1 to this bit 2 1 read-write 0 Transmit end event does not occur #0 1 Transmit end event occurs #1 TXSTIF Transmit Start Interrupt Flag\nNote: It is cleared by software writes 1 to this bit 1 1 read-write 0 Transmit start event does not occur #0 1 Transmit start event occurs #1 USPI_RXDAT USPI_RXDAT USCI Receive Data Register 0x34 read-only n 0x0 0x0 RXDAT Received Data\nThis bit field monitors the received data which stored in receive data buffer. 0 16 read-only USPI_TXDAT USPI_TXDAT USCI Transmit Data Register 0x30 write-only n 0x0 0x0 PORTDIR Port Direction Control\n 16 1 write-only 0 The data pin is configured as output mode #0 1 The data pin is configured as input mode #1 TXDAT Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field. 0 16 write-only USPI_WKCTL USPI_WKCTL USCI Wake-up Control Register 0x54 read-write n 0x0 0x0 PDBOPT Power Down Blocking Option\n 2 1 read-write 0 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately #0 1 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately #1 WKEN Wake-up Enable Bit\n 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 USPI_WKSTS USPI_WKSTS USCI Wake-up Status Register 0x58 read-write n 0x0 0x0 WKF Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write UUART0 UUART Register Map UUART 0x0 0x0 0xC registers n 0x10 0x4 registers n 0x20 0x4 registers n 0x28 0x1C registers n 0x54 0x14 registers n UUART_BRGEN UUART_BRGEN USCI Baud Rate Generator Register 0x8 read-write n 0x0 0x0 CLKDIV Clock Divider\nNote: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate. 16 10 read-write DSCNT Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value. 10 5 read-write PDSCNT Pre-divider for Sample Counter\n 8 2 read-write PTCLKSEL Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK). \n 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK). \n 0 1 read-write 0 Peripheral device clock fPCLK #0 1 Reserved #1 SPCLKSEL Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.\n 2 2 read-write 0 fSAMP_CLK = fDIV_CLK #00 1 fSAMP_CLK = fPROT_CLK #01 2 fSAMP_CLK = fSCLK #10 3 fSAMP_CLK = fREF_CLK #11 TMCNTEN Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.\n 4 1 read-write 0 Timing measurement counter is Disabled #0 1 Timing measurement counter is Enabled #1 TMCNTSRC Timing Measurement Counter Clock Source Selection\n 5 1 read-write 0 Timing measurement counter with fPROT_CLK #0 1 Timing measurement counter with fDIV_CLK #1 UUART_BUFCTL UUART_BUFCTL USCI Transmit/Receive Buffer Control Register 0x38 read-write n 0x0 0x0 RXCLR Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle. 15 1 read-write 0 No effect #0 1 The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic #1 RXOVIEN Receive Buffer Overrun Error Interrupt Enable Control\n 14 1 read-write 0 Receive overrun interrupt Disabled #0 1 Receive overrun interrupt Enabled #1 RXRST Receive Reset\nNote 1: It is cleared automatically after one PCLK cycle.\nNote 2: It is suggested to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1. 17 1 read-write 0 No effect #0 1 Reset the receive-related counters, state machine, and the content of receive shift register and data buffer #1 TXCLR Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle. 7 1 read-write 0 No effect #0 1 The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic #1 TXRST Transmit Reset\nNote: It is cleared automatically after one PCLK cycle. 16 1 read-write 0 No effect #0 1 Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer #1 UUART_BUFSTS UUART_BUFSTS USCI Transmit/Receive Buffer Status Register 0x3C read-write n 0x0 0x0 RXEMPTY Receive Buffer Empty Indicator \n 0 1 read-write 0 Receive buffer is not empty #0 1 Receive buffer is empty #1 RXFULL Receive Buffer Full Indicator\n 1 1 read-write 0 Receive buffer is not full #0 1 Receive buffer is full #1 RXOVIF Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit.\n 3 1 read-write 0 A receive buffer overrun error event has not been detected #0 1 A receive buffer overrun error event has been detected #1 TXEMPTY Transmit Buffer Empty Indicator\n 8 1 read-write 0 Transmit buffer is not empty #0 1 Transmit buffer is empty #1 TXFULL Transmit Buffer Full Indicator\n 9 1 read-write 0 Transmit buffer is not full #0 1 Transmit buffer is full #1 UUART_CLKIN UUART_CLKIN USCI Input Clock Signal Configuration Register 0x28 read-write n 0x0 0x0 SYNCSEL Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\n 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_CTL UUART_CTL USCI Control Register 0x0 read-write n 0x0 0x0 FUNMODE Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 0x0 to FUNMODE.\nNote: Other bit combinations are reserved. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state 0x0 1 The SPI protocol is selected 0x1 2 The UART protocol is selected 0x2 4 The I2C protocol is selected 0x4 UUART_CTLIN0 UUART_CTLIN0 USCI Input Control Signal Configuration Register 0 0x20 read-write n 0x0 0x0 ININV Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\n 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\n 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_DATIN0 UUART_DATIN0 USCI Input Data Signal Configuration Register 0 0x10 read-write n 0x0 0x0 EDGEDET Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode, it is suggested to set this bit field as 10. 3 2 read-write 0 The trigger event activation is disabled #00 1 A rising edge activates the trigger event of input data signal #01 2 A falling edge activates the trigger event of input data signal #10 3 Both edges activate the trigger event of input data signal #11 ININV Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\n 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\n 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_INTEN UUART_INTEN USCI Interrupt Enable Register 0x4 read-write n 0x0 0x0 RXENDIEN Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event.\n 4 1 read-write 0 The receive end interrupt is disabled #0 1 The receive end interrupt is enabled #1 RXSTIEN Receive Start Interrupt Enable BIt\nThis bit enables the interrupt generation in case of a receive start event.\n 3 1 read-write 0 The receive start interrupt is disabled #0 1 The receive start interrupt is enabled #1 TXENDIEN Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event.\n 2 1 read-write 0 The transmit finish interrupt is disabled #0 1 The transmit finish interrupt is enabled #1 TXSTIEN Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event.\n 1 1 read-write 0 The transmit start interrupt is disabled #0 1 The transmit start interrupt is enabled #1 UUART_LINECTL UUART_LINECTL USCI Line Control Register 0x2C read-write n 0x0 0x0 CTLOINV Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol, the control signal means nRTS signal. 7 1 read-write 0 No effect #0 1 The control signal will be inverted before its output #1 DATOINV Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin.\n 5 1 read-write 0 The value of USCIx_DAT1 is equal to the data shift register #0 1 The value of USCIx_DAT1 is the inversion of data shift register #1 DWIDTH Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].\nNote: In UART protocol, the length can be configured as 6~13 bits. 8 4 read-write LSB LSB First Transmission Selection\n 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 UUART_PDMACTL UUART_PDMACTL USCI PDMA Control Register 0x40 read-write n 0x0 0x0 PDMAEN PDMA Mode Enable Bit\n 3 1 read-write 0 PDMA function Disabled #0 1 PDMA function Enabled #1 PDMARST PDMA Reset\n 0 1 read-write 0 No effect #0 1 Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically #1 RXPDMAEN PDMA Receive Channel Available\n 2 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TXPDMAEN PDMA Transmit Channel Available\n 1 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 UUART_PROTCTL UUART_PROTCTL USCI Protocol Control Register 0x5C read-write n 0x0 0x0 ABREN Auto-baud Rate Detect Enable Bit\nNote: When the auto baud rate detect operation finishes, hardware will clear this bit. The associated interrupt ABRDETIF (UUART_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled). 6 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 BCEN Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 29 1 read-write 0 Transmit Break Control Disabled #0 1 Transmit Break Control Enabled #1 BRDETITV Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55). The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set.\nNote: This bit can be cleared to 0 by software writing '0' to the BRDETITV. 16 9 read-write CTSAUTOEN nCTS Auto-flow Control Enable Bit\nWhen nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted).\n 4 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 CTSWKEN nCTS Wake-up Mode Enable Bit\n 10 1 read-write 0 nCTS wake-up mode Disabled #0 1 nCTS wake-up mode Enabled #1 DATWKEN Data Wake-up Mode Enable Bit\n 9 1 read-write 0 Data wake-up mode Disabled #0 1 Data wake-up mode Enabled #1 EVENPARITY Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set. 2 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 PARITYEN Parity Enable Bit\nThis bit defines the parity bit is enabled in an UART frame.\n 1 1 read-write 0 The parity bit Disabled #0 1 The parity bit Enabled #1 PROTEN UART Protocol Enable Bit\n 31 1 read-write 0 UART Protocol Disabled #0 1 UART Protocol Enabled #1 RTSAUDIREN nRTS Auto Direction Enable Bit\nWhen nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the UART will reassert nRTS signal.\nNote 1: This bit is used for nRTS auto direction control for RS485.\nNote 2: This bit has effect only when the RTSAUTOEN is not set. 5 1 read-write 0 nRTS auto direction control Disabled #0 1 nRTS auto direction control Enabled #1 RTSAUTOEN nRTS Auto-flow Control Enable Bit\nNote: This bit has effect only when the RTSAUDIREN is not set. 3 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 STICKEN Stick Parity Enable Bit\nNote: Refer to section 6.13.5.9 for detailed information. 26 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 STOPB Stop Bits\nThis bit defines the number of stop bits in an UART frame.\n 0 1 read-write 0 The number of stop bits is 1 #0 1 The number of stop bits is 2 #1 WAKECNT Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode. 11 4 read-write UUART_PROTIEN UUART_PROTIEN USCI Protocol Interrupt Enable Register 0x60 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit\n 1 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt. 2 1 read-write 0 Receive line status interrupt Disabled #0 1 Receive line status interrupt Enabled #1 UUART_PROTSTS UUART_PROTSTS USCI Protocol Status Register 0x64 read-write n 0x0 0x0 ABERRSTS Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again.\nNote 1: This bit is set at the same time of ABRDETIF.\nNote 2: This bit can be cleared by writing "1" to ABRDETIF or ABERRSTS. 11 1 read-write 0 Auto-baud rate detect counter is not overrun #0 1 Auto-baud rate detect counter is overrun #1 ABRDETIF Auto-baud Rate Interrupt Flag \nThis bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated. This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus.\nNote: This bit can be cleared by writing "1" to it. 9 1 read-write 0 Auto-baud rate detect function is not done #0 1 One Bit auto-baud rate detect function is done #1 BREAK Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits).\nNote: This bit can be cleared by write "1" among the BREAK, FRMERR and PARITYERR bits. 7 1 read-write 0 No Break is generated #0 1 Break is generated in the receiver bus #1 CTSLV nCTS Pin Status (Read Only)\nThis bit used to monitor the current status of nCTS pin input.\n 17 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 CTSSYNCLV nCTS Synchronized Level Status (Read Only)\nThis bit used to indicate the current status of the internal synchronized nCTS signal. \n 16 1 read-only 0 The internal synchronized nCTS is low #0 1 The internal synchronized nCTS is high #1 FRMERR Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by write "1" among the BREAK, FRMERR and PARITYERR bits. 6 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PARITYERR Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid "parity bit".\nNote: This bit can be cleared by write "1" among the BREAK, FRMERR and PARITYERR bits. 5 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXBUSY RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver.\n 10 1 read-only 0 The receiver is Idle #0 1 The receiver is BUSY #1 RXENDIF Receive End Interrupt Flag\nNote: It is cleared by software writing one into this bit. 4 1 read-write 0 A receive finish interrupt status has not occurred #0 1 A receive finish interrupt status has occurred #1 RXSTIF Receive Start Interrupt Flag\nNote: It is cleared by software writing one into this bit. 3 1 read-write 0 A receive start interrupt status has not occurred #0 1 A receive start interrupt status has occurred #1 TXENDIF Transmit End Interrupt Flag\nNote: It is cleared by software writing one into this bit. 2 1 read-write 0 A transmit end interrupt status has not occurred #0 1 A transmit end interrupt status has occurred #1 TXSTIF Transmit Start Interrupt Flag\nNote 1: It is cleared by software writing one into this bit.\nNote 2: Used for user to load next transmit data when there is no data in transmit buffer. 1 1 read-write 0 A transmit start interrupt status has not occurred #0 1 A transmit start interrupt status has occurred #1 UUART_RXDAT UUART_RXDAT USCI Receive Data Register 0x34 read-only n 0x0 0x0 RXDAT Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]). 0 16 read-only UUART_TXDAT UUART_TXDAT USCI Transmit Data Register 0x30 write-only n 0x0 0x0 TXDAT Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. 0 16 write-only UUART_WKCTL UUART_WKCTL USCI Wake-up Control Register 0x54 read-write n 0x0 0x0 PDBOPT Power Down Blocking Option\n 2 1 read-write 0 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately #0 1 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately #1 WKEN Wake-up Enable Bit\n 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 UUART_WKSTS UUART_WKSTS USCI Wake-up Status Register 0x58 read-write n 0x0 0x0 WKF Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write WDT WDT Register Map WDT 0x0 0x0 0xC registers n 0xFFC 0x4 registers n ALTCTL WDT_ALTCTL WDT Alternative Control Register 0x4 read-write n 0x0 0x0 RSTDSEL WDT Reset Delay Selection (Write Protect)\nWhen WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened. User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: This register will be reset to 0 if WDT time-out reset happened. 0 2 read-write 0 WDT Reset Delay Period is 1026 * WDT_CLK #00 1 WDT Reset Delay Period is 130 * WDT_CLK #01 2 WDT Reset Delay Period is 18 * WDT_CLK #10 3 WDT Reset Delay Period is 3 * WDT_CLK #11 CTL WDT_CTL WDT Control Register 0x0 read-write n 0x0 0x0 ICEDEBUG ICE Debug Mode Acknowledge Disable Control (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement affects WDT counting #0 1 ICE debug mode acknowledgement Disabled #1 IF WDT Time-out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval\nNote: This bit is cleared by writing 1 to it. 3 1 read-write 0 WDT time-out interrupt did not occur #0 1 WDT time-out interrupt occurred #1 INTEN WDT Time-out Interrupt Enable Control (Write Protect)\nIf this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. \nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write 0 WDT time-out interrupt Disabled #0 1 WDT time-out interrupt Enabled #1 RSTCNT Reset WDT Up Counter (Write Protect)\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: This bit will be automatically cleared by hardware. 0 1 read-write 0 No effect #0 1 Reset the internal 18-bit WDT up counter value #1 RSTEN WDT Time-out Reset Enable Control (Write Protect)\nSetting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 WDT time-out reset function Disabled #0 1 WDT time-out reset function Enabled #1 RSTF WDT Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it. 2 1 read-write 0 WDT time-out reset did not occur #0 1 WDT time-out reset occurred #1 TOUTSEL WDT Time-out Interval Selection (Write Protect)\nThese three bits select the time-out interval period for the WDT.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 8 3 read-write 0 24 * WDT_CLK #000 1 26 * WDT_CLK #001 2 28 * WDT_CLK #010 3 210 * WDT_CLK #011 4 212 * WDT_CLK #100 5 214 * WDT_CLK #101 6 216 * WDT_CLK #110 7 218 * WDT_CLK #111 WDTEN WDT Enable Control (Write Protect)\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configure to 111B, this bit is forced as 1 and user cannot change this bit to 0.\nNote3: Disabled this bit needs 2 * WDT_CLK. 7 1 read-write 0 WDT Disabled (This action will reset the internal up counter value) #0 1 WDT Enabled #1 WKEN WDT Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz (LIRC) or LXT. 4 1 read-write 0 Wake-up trigger event Disabled if WDT time-out interrupt signal generated #0 1 Wake-up trigger event Enabled if WDT time-out interrupt signal generated #1 WKF WDT Time-out Wake-up Flag (Write Protect)\nThis bit indicates the interrupt wake-up flag status of WDT\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: This bit is cleared by writing 1 to it. 5 1 read-write 0 WDT does not cause chip wake-up #0 1 Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated #1 WSYNC WDT Enable Control SYNC Flag Indicator (Read Only)\nDue to synchronization, software can check this flag after enable WDTEN(WDT_CTL[7]),\nSYNC delay is\nNote:\nThis bit enabled needs 2 * WDT_CLK 30 1 read-only 0 WDT enable control synchronizing is completion #0 1 WDT enable control is synchronizing #1 RSTCNT WDT_RSTCNT WDT Reset Counter Register 0x8 write-only n 0x0 0x0 RSTCNT WDT Reset Counter Register\nWriting 0x00005AA5 to this register will reset the internal 18-bit WDT up counter value to 0.\nNote: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active. 0 32 write-only VERSION WDT_VERSION WDT RTL Design Version Register 0xFFC read-only n 0x0 0x0 WWDT WWDT Register Map WWDT 0x0 0x0 0x10 registers n CNT WWDT_CNT WWDT Counter Value Register 0xC read-only n 0x0 0x0 CNTDAT WWDT Counter Value\nCNTDAT will be updated continuously 0 6 read-only CTL WWDT_CTL WWDT Control Register 0x4 read-write n 0x0 0x0 CMPDAT WWDT Window Compare Value\nSet this field to adjust the valid reload window interval when WWDTIF (WWDT_STATUS[0]) is generated.\nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current CNTDAT (WWDT_CNT[5:0]) is between 1 and CMPDAT. If user writes 0x00005AA5 in WWDT_RLDCNT register when current CNTDAT is larger than CMPDAT, WWDT reset system event will be generated immediately. 16 6 read-write ICEDEBUG ICE Debug Mode Acknowledge Disable Control\nWWDT down counter will keep going no matter CPU is held by ICE or not. 31 1 read-write 0 ICE debug mode acknowledgement effects WWDT counting #0 1 ICE debug mode acknowledgement Disabled #1 INTEN WWDT Interrupt Enable Control Bit\nIf this bit is enabled, when WWDTIF (WWDT_STATUS[0]) is set to 1, the WWDT counter compare match interrupt signal is generated and inform to CPU.\n 1 1 read-write 0 WWDT counter compare match interrupt Disabled #0 1 WWDT counter compare match interrupt Enabled #1 PSCSEL WWDT Counter Prescale Period Selection\n 8 4 read-write 0 Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK #0000 1 Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK #0001 2 Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK #0010 3 Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK #0011 4 Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK #0100 5 Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK #0101 6 Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK #0110 7 Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK #0111 8 Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK #1000 9 Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK #1001 10 Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK #1010 11 Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK #1011 12 Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK #1100 13 Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK #1101 14 Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK #1110 15 Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK #1111 WWDTEN WWDT Enable Control Bit\nSet this bit to enable WWDT counter counting.\n 0 1 read-write 0 WWDT counter is stopped #0 1 WWDT counter is starting counting #1 RLDCNT WWDT_RLDCNT WWDT Reload Counter Register 0x0 write-only n 0x0 0x0 RLDCNT WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.\nNote1: User can only execute the reload WWDT counter value command when current CNTDAT (WWDT_CNT[5:0]) is between 1 and CMPDAT (WWDT_CTL[21:16]). If user writes 0x00005AA5 in WWDT_RLDCNT register when current CNTDAT is larger than CMPDAT, WWDT reset system event will be generated immediately.\nNote2: Execute WWDT counter reload always needs (WWDT_CLK *3) period to reload CNTDAT to 0x3F and internal prescale counter will be reset also. 0 32 write-only STATUS WWDT_STATUS WWDT Status Register 0x8 read-write n 0x0 0x0 WWDTIF WWDT Compare Match Interrupt Flag\nThis bit indicates that current CNTDAT (WWDT_CNT[5:0]) matches the CMPDAT (WWDT_CTL[21:16]).\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 WWDT counter value matches CMPDAT #1 WWDTRF WWDT Timer-out Reset Flag\nIf this bit is set to 1, it indicates that system has been reset by WWDT counter time-out reset system event.\nNote: This bit is cleared by writing 1 to it. 1 1 read-write 0 WWDT time-out reset system event did not occur #0 1 WWDT time-out reset system event occurred #1