nuvoTon
NUC200AN_v1
2024.04.27
NUC200AN_v1 SVD file
8
32
ACMP
ACMP Register Map
ACMP
0x0
0x0
0xC
registers
n
CMPCR0
CMPCR0
Comparator 0 Control Register
0x0
read-write
n
0x0
0x0
CMPCN
Comparator Negative Input Selection\n
4
1
read-write
0
The source of the negative comparator input is from CMPx_N pin (x = 0, 1)
#0
1
Internal band-gap reference voltage is selected as the source of negative comparator input
#1
CMPEN
Comparator Enable\nComparator output needs to wait 2 us stable time after CMPEN is set.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
CMPIE
Comparator Interrupt Enable\n
1
1
read-write
0
Interrupt function Disabled
#0
1
Interrupt function Enabled
#1
CMP_HYSEN
Comparator Hysteresis Enable\n
2
1
read-write
0
Hysteresis function Disabled (Default)
#0
1
Hysteresis function Enabled. The typical range is 20mV
#1
CMPCR1
CMPCR1
Comparator 1 Control Register
0x4
read-write
n
0x0
0x0
CMPSR
CMPSR
Comparator Status Register
0x8
read-write
n
0x0
0x0
CMPF0
Comparator 0 Flag\nThis bit is set by hardware whenever the comparator 0 output changes state. This will cause an interrupt if CMPCR0[1] is set to 1.\nWrite 1 to clear this bit to 0.
0
1
read-write
CMPF1
Comparator 1 Flag\nThis bit is set by hardware whenever the comparator 1 output changes state. This will cause an interrupt if CMPCR1[1] is set to 1.\nWrite 1 to clear this bit to 0.
1
1
read-write
CO0
Comparator 0 Output\n
2
1
read-write
CO1
Comparator 1 Output\n
3
1
read-write
ADC
ADC Register Map
ADC
0x0
0x0
0x30
registers
n
0x40
0x4
registers
n
ADCHER
ADCHER
ADC Channel Enable Register
0x24
read-write
n
0x0
0x0
CHEN
Analog Input Channel Enable\nSet CHEN[7:0] to enable the corresponding analog input channel 7 ~ 0. If DIFFEN bit is set to 1, only the even number channels need to be enabled.\n
0
8
read-write
0
ADC input channel Disabled
0
1
ADC input channel Enabled
1
PRESEL
Analog Input Channel 7 Select\nNote:\nWhen software select the band-gap voltage as the analog input source of ADC channel 7, ADC clock rate needs to be limited to slower than 300 kHz.
8
2
read-write
0
External analog input
#00
1
Internal band-gap voltage
#01
2
Internal temperature sensor
#10
3
Reserved
#11
ADCMPR0
ADCMPR0
ADC Compare Register 0
0x28
read-write
n
0x0
0x0
CMPCH
Compare Channel Selection\n
3
3
read-write
0
Channel 0 conversion result is selected to be compared
#000
1
Channel 1 conversion result is selected to be compared
#001
2
Channel 2 conversion result is selected to be compared
#010
3
Channel 3 conversion result is selected to be compared
#011
4
Channel 4 conversion result is selected to be compared
#100
5
Channel 5 conversion result is selected to be compared
#101
6
Channel 6 conversion result is selected to be compared
#110
7
Channel 7 conversion result is selected to be compared
#111
CMPCOND
Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.
2
1
read-write
0
Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one
#0
1
Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one
#1
CMPD
Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nWhen DMOF bit is set to 0, ADC comparator compares CMPD with conversion result with unsigned format. CMPD should be filled in unsigned format.\nWhen DMOF bit is set to 1, ADC comparator compares CMPD with conversion result with 2'complement format. CMPD should be filled in 2'complement format.
16
12
read-write
CMPEN
Compare Enable\nSet this bit to 1 to enable ADC controller to compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADDR register.
0
1
read-write
0
Compare function Disabled
#0
1
Compare function Enabled
#1
CMPIE
Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated.
1
1
read-write
0
Compare function interrupt Disabled
#0
1
Compare function interrupt Enabled
#1
CMPMATCNT
Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.
8
4
read-write
ADCMPR1
ADCMPR1
ADC Compare Register 1
0x2C
read-write
n
0x0
0x0
ADCR
ADCR
ADC Control Register
0x20
read-write
n
0x0
0x0
ADEN
A/D Converter Enable\nBefore starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit for saving power consumption.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
ADIE
A/D Interrupt Enable\nA/D conversion end interrupt request is generated if ADIE bit is set to 1.
1
1
read-write
0
A/D interrupt function Disabled
#0
1
A/D interrupt function Enabled
#1
ADMD
A/D Converter Operation Mode\nWhen changing the operation mode, software should disable ADST bit firstly.
2
2
read-write
0
Single conversion
#00
1
Reserved
#01
2
Single-cycle scan
#10
3
Continuous scan
#11
ADST
A/D Conversion Start\nADST bit can be set to 1 from three sources: software, PWM Center-aligned trigger and external pin STADC. ADST will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode. In continuous scan mode, A/D conversion is continuously performed until software writes 0 to this bit or chip reset.
11
1
read-write
0
Conversion stops and A/D converter enter idle state
#0
1
Conversion starts
#1
DIFFEN
Differential Input Mode Enable\n
10
1
read-write
0
Single-end analog input mode
#0
1
Differential analog input mode
#1
DMOF
A/D Differential Input Mode Output Format\n
31
1
read-write
0
A/D Conversion result will be filled in RSLT at ADDRx registers with unsigned format
#0
1
A/D Conversion result will be filled in RSLT at ADDRx registers with 2'complement format
#1
PTEN
PDMA Transfer Enable\n
9
1
read-write
0
PDMA data transfer Disabled
#0
1
PDMA data transfer in ADDR 0~7 Enabled
#1
TRGCOND
External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state for edge trigger.\n
6
2
read-write
0
Low level
#00
1
High level
#01
2
Falling edge
#10
3
Rising edge
#11
TRGEN
Hardware Trigger Enable\nEnable or disable triggering of A/D conversion by hardware (external STADC pin or PWM Center-aligned trigger).\nADC hardware trigger function is only supported in single-cycle scan mode.\nIf hardware trigger mode, the ADST bit can be set to 1 by the selected hardware trigger source.
8
1
read-write
0
Disabled
#0
1
Enabled
#1
TRGS
Hardware Trigger Source\nSoftware should disable TRGEN and ADST before change TRGS.
4
2
read-write
0
A/D conversion is started by external STADC pin
#00
3
A/D conversion is started by PWM Center-aligned trigger
#11
ADDR0
ADDR0
ADC Data Register 0
0x0
read-only
n
0x0
0x0
OVERRUN
Overrun Flag\nIf converted data in RSLT[15:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1 and previous conversion result is gone. It is cleared by hardware after ADDR register is read.\nThis is a read only bit.
16
1
read-only
0
Data in RSLT[15:0] is recent conversion result
#0
1
Data in RSLT[15:0] is overwritten
#1
RSLT
A/D Conversion Result\nThis field contains conversion result of ADC.\nWhen DMOF bit (ADCR[31]) set to 0, 12-bit ADC conversion result with unsigned format will be filled in RSLT[11:0] and zero will be filled in RSLT[15:12].\nWhen DMOF bit (ADCR[31]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RSLT[11:0] and signed bits to will be filled in RSLT[15:12].
0
16
read-only
VALID
Valid Flag\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit.
17
1
read-only
0
Data in RSLT[15:0] bits is not valid
#0
1
Data in RSLT[15:0] bits is valid
#1
ADDR1
ADDR1
ADC Data Register 1
0x4
read-write
n
0x0
0x0
ADDR2
ADDR2
ADC Data Register 2
0x8
read-write
n
0x0
0x0
ADDR3
ADDR3
ADC Data Register 3
0xC
read-write
n
0x0
0x0
ADDR4
ADDR4
ADC Data Register 4
0x10
read-write
n
0x0
0x0
ADDR5
ADDR5
ADC Data Register 5
0x14
read-write
n
0x0
0x0
ADDR6
ADDR6
ADC Data Register 6
0x18
read-write
n
0x0
0x0
ADDR7
ADDR7
ADC Data Register 7
0x1C
read-write
n
0x0
0x0
ADPDMA
ADPDMA
ADC PDMA Current Transfer Data Register
0x40
read-only
n
0x0
0x0
AD_PDMA
ADC PDMA Current Transfer Data Register\nWhen PDMA transferring, read this register can monitor current PDMA transfer data.\nCurrent PDMA transfer data is the content of ADDR0 ~ ADDR7.\nThis is a read only register.
0
18
read-only
ADSR
ADSR
ADC Status Register
0x30
read-write
n
0x0
0x0
ADF
A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to 1 at these two conditions:\n1. When A/D conversion ends in Single mode.\n2. When A/D conversion ends on all specified channels in Scan mode.\nThis flag can be cleared by writing 1 to itself.
0
1
read-write
BUSY
BUSY/IDLE\nThis bit is mirror of as ADST bit in ADCR.\nIt is read only.
3
1
read-write
0
A/D converter is in idle state
#0
1
A/D converter is busy at conversion
#1
CHANNEL
Current Conversion Channel\nIt is read only.
4
3
read-write
CMPF0
Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by writing 1 to self.\n
1
1
read-write
0
Conversion result in ADDR does not meet ADCMPR0 setting
#0
1
Conversion result in ADDR meets ADCMPR0 setting
#1
CMPF1
Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1. And it is cleared by writing 1 to self.\n
2
1
read-write
0
Conversion result in ADDR does not meet ADCMPR1 setting
#0
1
Conversion result in ADDR meets ADCMPR1 setting
#1
OVERRUN
Overrun Flag\nIt is a mirror to OVERRUN bit in ADDRx.\nIt is read only.
16
8
read-write
VALID
Data Valid Flag\nIt is a mirror of VALID bit in ADDRx.\nIt is read only.
8
8
read-write
CLK
CLK Register Map
CLK
0x0
0x0
0x28
registers
n
0x30
0xC
registers
n
AHBCLK
AHBCLK
AHB Devices Clock Enable Control Register
0x4
-1
read-write
n
0x0
0x0
ISP_EN
Flash ISP Controller Clock Enable Control\n
2
1
read-write
0
Flash ISP peripheral clock Disabled
#0
1
Flash ISP peripheral clock Enabled
#1
PDMA_EN
PDMA Controller Clock Enable Control\n
1
1
read-write
0
PDMA peripheral clock Disabled
#0
1
PDMA peripheral clock Enabled
#1
APBCLK
APBCLK
APB Devices Clock Enable Control Register
0x8
read-write
n
0x0
0x0
ACMP_EN
Analog Comparator Clock Enable\n
30
1
read-write
0
Analog Comparator clock Disabled
#0
1
Analog Comparator clock Enabled
#1
ADC_EN
Analog-digital-converter (ADC) Clock Enable\n
28
1
read-write
0
ADC clock Disabled
#0
1
ADC clock Enabled
#1
FDIV_EN
Frequency Divider Output Clock Enable\n
6
1
read-write
0
FDIV clock Disabled
#0
1
FDIV clock Enabled
#1
I2C0_EN
I2C0 Clock Enable\n
8
1
read-write
0
I2C0 clock Disabled
#0
1
I2C0 clock Enabled
#1
I2C1_EN
I2C1 Clock Enable\n
9
1
read-write
0
I2C1 clock Disabled
#0
1
I2C1 clock Enabled
#1
I2S_EN
I2S Clock Enable\n
29
1
read-write
0
I2S clock Disabled
#0
1
I2S clock Enabled
#1
PS2_EN
PS/2 Clock Enable\n
31
1
read-write
0
PS/2 clock Disabled
#0
1
PS/2 clock Enabled
#1
PWM01_EN
PWM_01 Clock Enable\n
20
1
read-write
0
PWM01 clock Disabled
#0
1
PWM01 clock Enabled
#1
PWM23_EN
PWM_23 Clock Enable\n
21
1
read-write
0
PWM23 clock Disabled
#0
1
PWM23 clock Enabled
#1
PWM45_EN
PWM_45 Clock Enable \n
22
1
read-write
0
PWM45 clock Disabled
#0
1
PWM45 clock Enabled
#1
PWM67_EN
PWM_67 Clock Enable \n
23
1
read-write
0
PWM67 clock Disabled
#0
1
PWM67 clock Enabled
#1
RTC_EN
Real-time-clock APB Interface Clock Enable\nThis bit is used to control the RTC APB clock only, The RTC peripheral clock source is from the external 32.768 kHz low speed crystal.\n
1
1
read-write
0
RTC clock Disabled
#0
1
RTC clock Enabled
#1
SPI0_EN
SPI0 Clock Enable\n
12
1
read-write
0
SPI0 clock Disabled
#0
1
SPI0 clock Enabled
#1
SPI1_EN
SPI1 Clock Enable\n
13
1
read-write
0
SPI1 clock Disabled
#0
1
SPI1 clock Enabled
#1
SPI2_EN
SPI2 Clock Enable\n
14
1
read-write
0
SPI2 clock Disabled
#0
1
SPI2 clock Enabled
#1
SPI3_EN
SPI3 Clock Enable \n
15
1
read-write
0
SPI3 clock Disabled
#0
1
SPI3 clock Enabled
#1
TMR0_EN
Timer0 Clock Enable\n
2
1
read-write
0
Timer0 clock Disabled
#0
1
Timer0 clock Enabled
#1
TMR1_EN
Timer1 Clock Enable\n
3
1
read-write
0
Timer1 clock Disabled
#0
1
Timer1 clock Enabled
#1
TMR2_EN
Timer2 Clock Enable\n
4
1
read-write
0
Timer2 clock Disabled
#0
1
Timer2 clock Enabled
#1
TMR3_EN
Timer3 Clock Enable\n
5
1
read-write
0
Timer3 clock Disabled
#0
1
Timer3 clock Enabled
#1
UART0_EN
UART0 Clock Enable\n
16
1
read-write
0
UART0 clock Disabled
#0
1
UART0 clock Enabled
#1
UART1_EN
UART1 Clock Enable\n
17
1
read-write
0
UART1 clock Disabled
#0
1
UART1 clock Enabled
#1
UART2_EN
UART2 Clock Enable \n
18
1
read-write
0
UART2 clock Disabled
#0
1
UART2 clock Enabled
#1
USBD_EN
USB 2.0 FS Device Controller Clock Enable\n
27
1
read-write
0
USB clock Enabled
#0
1
USB clock Enabled
#1
WDT_EN
Watchdog Timer Clock Enable (Write Protected)
This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
0
1
read-write
0
Watchdog Timer clock Disabled
#0
1
Watchdog Timer clock Enabled
#1
APBCLK1
APBCLK1
APB Devices Clock Enable Control Register 1
0x30
read-write
n
0x0
0x0
SC0_EN
SC0 Clock Enable\n
0
1
read-write
0
SC0 Clock Disabled
#0
1
SC0 Clock Enabled
#1
SC1_EN
SC1 Clock Enable\n
1
1
read-write
0
SC1 clock Disabled
#0
1
SC1 clock Enabled
#1
SC2_EN
SC2 Clock Enable\n
2
1
read-write
0
SC2 clock Disabled
#0
1
SC2 clock Enabled
#1
CLKDIV
CLKDIV
Clock Divider Number Register
0x18
read-write
n
0x0
0x0
ADC_N
ADC Clock Divide Number From ADC Clock Source\n
16
8
read-write
HCLK_N
HCLK Clock Divide Number From HCLK Clock Source\n
0
4
read-write
UART_N
UART Clock Divide Number From UART Clock Source\n
8
4
read-write
USB_N
USB Clock Divide Number From PLL Clock\n
4
4
read-write
CLKDIV1
CLKDIV1
Clock Divider Number Register 1
0x38
read-write
n
0x0
0x0
SC0_N
SC0 Clock Divide Number From SC0 Clock Source\n
0
8
read-write
SC1_N
SC1 Clock Divide Number From SC1 Clock Source\n
8
8
read-write
SC2_N
SC2 Clock Divide Number From SC2 Clock Source\n
16
8
read-write
CLKSEL0
CLKSEL0
Clock Source Select Control Register 0
0x10
-1
read-write
n
0x0
0x0
HCLK_S
HCLK Clock Source Select (Write-protection Bits)
Before clock switching, the related clock sources (both pre-select and new-select) must be turn on
The 3-bit default value is reloaded from the value of CFOSC (Config0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b.
These bits are protected bit. It means programming them needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
0
3
read-write
0
Clock source from external 4~24 MHz high speed crystal oscillator clock
#000
1
Clock source from external 32.768 kHz low speed crystal oscillator clock
#001
2
Clock source from PLL clock
#010
3
Clock source from internal 10 kHz low speed oscillator clock
#011
7
Clock source from internal 22.1184 MHz high speed oscillator clock
#111
STCLK_S
Cortex-M0 SysTick Clock Source Select (Write-protection Bits)\n
3
3
read-write
0
Clock source from external 4~24 MHz high speed crystal clock
#000
1
Clock source from external 32.768 kHz low speed crystal clock
#001
2
Clock source from external 4~24 MHz high speed crystal clock/2
#010
3
Clock source from HCLK/2
#011
7
Clock source from internal 22.1184 MHz high speed oscillator clock/2
#111
CLKSEL1
CLKSEL1
Clock Source Select Control Register 1
0x14
-1
read-write
n
0x0
0x0
ADC_S
ADC Clock Source Select\n
2
2
read-write
0
Clock source from external 4~24 MHz high speed crystal oscillator clock
#00
1
Clock source from PLL clock
#01
2
Clock source from HCLK
#10
3
Clock source from internal 22.1184 MHz high speed oscillator clock
#11
PWM01_S
PWM0 and PWM1 Clock Source Selection\nPWM0 and PWM1 use the same Peripheral clock source, both of them use the same prescaler. The Peripheral clock source of PWM0 and PWM1 is defined by PWM01_S[2:0] and this field is combined by CLKSEL2[8] and CLKSEL1[29:28].\n
28
2
read-write
PWM23_S
PWM2 and PWM3 Clock Source Selection
PWM2 and PWM3 use the same Peripheral clock source both of them use the same prescaler. The Peripheral clock source of PWM2 and PWM3 is defined by PWM23_S[2:0] and this field is combined by CLKSEL2[9] and CLKSEL1[31:30].
30
2
read-write
SPI0_S
SPI0 Clock Source Selection\n
4
1
read-write
0
Clock source from PLL clock
#0
1
Clock source from HCLK
#1
SPI1_S
SPI1 Clock Source Selection\n
5
1
read-write
0
Clock source from PLL clock
#0
1
Clock source from HCLK
#1
SPI2_S
SPI2 Clock Source Selection\n
6
1
read-write
0
Clock source from PLL clock
#0
1
Clock source from HCLK
#1
SPI3_S
SPI3 Clock Source Selection\n
7
1
read-write
0
Clock source from PLL clock
#0
1
Clock source from HCLK
#1
TMR0_S
TIMER0 Clock Source Selection\n
8
3
read-write
0
Clock source from external 4~24 MHz high speed crystal clock
#000
1
Clock source from external 32.768 kHz low speed crystal clock
#001
2
Clock source from HCLK
#010
3
Clock source from external trigger
#011
5
Clock source from internal 10 kHz low speed oscillator clock
#101
7
Clock source from internal 22.1184 MHz high speed oscillator clock
#111
TMR1_S
TIMER1 Clock Source Selection\n
12
3
read-write
0
Clock source from external 4~24 MHz high speed crystal clock
#000
1
Clock source from external 32.768 kHz low speed crystal clock
#001
2
Clock source from HCLK
#010
3
Clock source from external trigger
#011
5
Clock source from internal 10 kHz low speed oscillator clock
#101
7
Clock source from internal 22.1184 MHz high speed oscillator clock
#111
TMR2_S
TIMER2 Clock Source Selection\n
16
3
read-write
0
Clock source from external 4~24 MHz high speed crystal clock
#000
1
Clock source from external 32.768 kHz low speed crystal clock
#001
2
Clock source from HCLK
#010
3
Clock source from external trigger
#011
5
Clock source from internal 10 kHz low speed oscillator clock
#101
7
Clock source from internal 22.1184 MHz high speed oscillator clock
#111
TMR3_S
TIMER3 Clock Source Selection\n
20
3
read-write
0
Clock source from external 4~24 MHz high speed crystal clock
#000
1
Clock source from external 32.768 kHz low speed crystal clock
#001
2
Clock source from HCLK
#010
3
Clock source from external trigger
#011
5
Clock source from internal 10 kHz low speed oscillator clock
#101
7
Clock source from internal 22.1184 MHz high speed oscillator clock
#111
UART_S
UART Clock Source Selection\n
24
2
read-write
0
Clock source from external 4~24 MHz high speed crystal oscillator clock
#00
1
Clock source from PLL clock
#01
3
Clock source from internal 22.1184 MHz high speed oscillator clock
#11
WDT_S
Watchdog Timer Clock Source Select (Write-protection Bits)
These bits are protected bits, and programming this needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
0
2
read-write
0
Reserved
#00
1
Clock source from external 32.768 kHz low speed crystal oscillator clock
#01
2
Clock source from HCLK/2048 clock
#10
3
Clock source from internal 10 kHz low speed oscillator clock
#11
CLKSEL2
CLKSEL2
Clock Source Select Control Register 2
0x1C
-1
read-write
n
0x0
0x0
FRQDIV_S
Clock Divider Clock Source Selection\n
2
2
read-write
0
Clock source from external 4~24 MHz high speed crystal oscillator clock
#00
1
Clock source from external 32.768 kHz low speed crystal oscillator clock
#01
2
Clock source from HCLK
#10
3
Clock source from internal 22.1184 MHz high speed oscillator clock
#11
I2S_S
I2S Clock Source Selection\n
0
2
read-write
0
Clock source from external 4~24 MHz high speed crystal oscillator clock
#00
1
Clock source from PLL clock
#01
2
Clock source from HCLK
#10
3
Clock source from internal 22.1184 MHz high speed oscillator clock
#11
PWM01_S_E
PWM0 and PWM1 Clock Source Selection
PWM0 and PWM1 used the same Peripheral clock source both of them used the same prescaler. The Peripheral clock source of PWM0 and PWM1 is defined by PWM01_S[2:0] and this field is combined by CLKSEL2[8] and CLKSEL1[29:28].
8
1
read-write
PWM23_S_E
PWM2 and PWM3 Clock Source Selection
PWM2 and PWM3 used the same Peripheral clock source both of them used the same prescaler. The Peripheral clock source of PWM2 and PWM3 is defined by PWM23_S[2:0] and this field is combined by CLKSEL2[9] and CLKSEL1[31:30].
9
1
read-write
PWM45_S
PWM4 and PWM5 Clock Source Selection
PWM4 and PWM5 used the same Peripheral clock source both of them used the same prescaler. The Peripheral clock source of PWM4 and PWM5 is defined by PWM45_S[2:0] and this field is combined by CLKSEL2[10] and CLKSEL2[5:4].
4
2
read-write
PWM45_S_E
PWM4 and PWM5 Clock Source Selection
PWM4 and PWM5 used the same Peripheral clock source both of them used the same prescaler. The Peripheral clock source of PWM4 and PWM5 is defined by PWM45_S[2:0] and this field is combined by CLKSEL2[10] and CLKSEL2[5:4].
10
1
read-write
PWM67_S
PWM6 and PWM7 Clock Source Selection
PWM6 and PWM7 used the same Peripheral clock source both of them used the same prescaler. The Peripheral clock source of PWM6 and PWM7 is defined by PWM67_S (CLKSEL2[7:6]) and PWM67_S_E (CLKSEL2[11]). this field is combined by CLKSEL2[11] and CLKSEL2[7:6].
6
2
read-write
PWM67_S_E
PWM6 and PWM7 Clock Source Selection
PWM6 and PWM7 used the same Peripheral clock source both of them used the same prescaler. The Peripheral clock source of PWM6 and PWM7 is defined by PWM67_S[2:0] and this field is combined by CLKSEL2[11] and CLKSEL2[7:6].
11
1
read-write
WWDT_S
Window Watchdog Timer Clock Source Selection\n
16
2
read-write
2
Clock source from HCLK/2048 clock
#10
3
Clock source from internal 10 kHz low speed oscillator clock
#11
CLKSEL3
CLKSEL3
Clock Source Select Control Register 3
0x34
-1
read-write
n
0x0
0x0
SC0_S
SC0 Clock Source Selection\n
0
2
read-write
0
Clock source from external 4~24 MHz high speed crystal oscillator clock
#00
1
Clock source from PLL clock
#01
2
HCLK
#10
3
Clock source from internal 22.1184 MHz high speed oscillator clock
#11
SC1_S
SC1 Clock Source Selection\n
2
2
read-write
0
Clock source from external 4~24 MHz high speed crystal oscillator clock
#00
1
Clock source from PLL clock
#01
2
HCLK
#10
3
Clock source from internal 22.1184 MHz high speed oscillator clock
#11
SC2_S
SC2 Clock Source Selection\n
4
2
read-write
0
Clock source from external 4~24 MHz high speed crystal oscillator clock
#00
1
Clock source from PLL clock
#01
2
HCLK
#10
3
Clock source from internal 22.1184 MHz high speed oscillator clock
#11
CLKSTATUS
CLKSTATUS
Clock Status Monitor Register
0xC
read-write
n
0x0
0x0
CLK_SW_FAIL
Clock Switching Fail Flag\nThis bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nWrite 1 to clear the bit to 0.
7
1
read-write
0
Clock switching success
#0
1
Clock switching failed
#1
OSC10K_STB
Internal 10 KHz Low Speed Oscillator Clock Source Stable Flag\nThis bit is read only.
3
1
read-write
0
Internal 10 kHz low speed oscillator clock is not stable or disabled
#0
1
Internal 10 kHz low speed oscillator clock is stable
#1
OSC22M_STB
Internal 22.1184 MHz High Speed Oscillator Clock Source Stable Flag\nThis bit is read only.
4
1
read-write
0
Internal 22.1184 MHz high speed oscillator clock is not stable or disabled
#0
1
Internal 22.1184 MHz high speed oscillator clock is stable
#1
PLL_STB
Internal PLL Clock Source Stable Flag\nThis bit is read only.
2
1
read-write
0
Internal PLL clock is not stable or disabled
#0
1
Internal PLL clock is stable
#1
XTL12M_STB
External 4~24 MHz High Speed Crystal Clock Source Stable Flag\nThis bit is read only.
0
1
read-write
0
External 4~24 MHz high speed crystal clock is not stable or disabled
#0
1
External 4~24 MHz high speed crystal clock is stable
#1
XTL32K_STB
External 32.768 KHz Low Speed Crystal Clock Source Stable Flag\nThis bit is read only.
1
1
read-write
0
External 32.768 kHz low speed crystal clock is not stable or disabled
#0
1
External 32.768 kHz low speed crystal clock is stable
#1
FRQDIV
FRQDIV
Frequency Divider Control Register
0x24
read-write
n
0x0
0x0
DIVIDER_EN
Frequency Divider Enable Bit\n
4
1
read-write
0
Frequency Divider Disabled
#0
1
Frequency Divider Enabled
#1
FSEL
Divider Output Frequency Selection Bits\nThe formula of output frequency is:\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0].
0
4
read-write
PLLCON
PLLCON
PLL Control Register
0x20
-1
read-write
n
0x0
0x0
BP
PLL Bypass Control\n
17
1
read-write
0
PLL is in Normal mode (default)
#0
1
PLL clock output is same as PLL source clock input
#1
FB_DV
PLL Feedback Divider Control Bits\nRefer to the formulas below the table.
0
9
read-write
IN_DV
PLL Input Divider Control Bits\nRefer to the formulas below the table.
9
5
read-write
OE
PLL OE (FOUT Enable) Pin Control\n
18
1
read-write
0
PLL FOUT Enabled
#0
1
PLL FOUT is fixed low
#1
OUT_DV
PLL Output Divider Control Bits\nRefer to the formulas below the table.
14
2
read-write
PD
Power-down Mode\nIf the PWR_DOWN_EN bit is set to 1 in PWRCON register, the PLL will enter Power-down mode too.\n
16
1
read-write
0
PLL is in Normal mode
#0
1
PLL is in Power-down mode (default)
#1
PLL_SRC
PLL Source Clock Selection\n
19
1
read-write
0
PLL source clock from external 4~24 MHz high speed crystal
#0
1
PLL source clock from internal 22.1184 MHz high speed oscillator
#1
PWRCON
PWRCON
System Power-down Control Register
0x0
-1
read-write
n
0x0
0x0
OSC10K_EN
Internal 10 KHz Low Speed Oscillator Enable (Write Protected)\n
3
1
read-write
0
Internal 10 kHz low speed oscillator Disabled
#0
1
Internal 10 kHz low speed oscillator Enabled
#1
OSC22M_EN
Internal 22.1184 MHz High Speed Oscillator Enable (Write Protected)\n
2
1
read-write
0
Internal 22.1184 MHz high speed oscillator Disabled
#0
1
Internal 22.1184 MHz high speed oscillator Enabled
#1
PD_WAIT_CPU
This Bit Control the Power-down Entry Condition (Write Protected)\n
8
1
read-write
0
Chip enters Power-down mode when the PWR_DOWN_EN bit is set to 1
#0
1
Chip enters Power- down mode when the both PD_WAIT_CPU and PWR_DOWN_EN bits are set to 1 and CPU run WFI instruction
#1
PD_WU_DLY
Enable the Wake-up Delay Counter (Write Protected)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz high speed crystal, and 256 clock cycles when chip work at internal 22.1184 MHz high speed oscillator.\n
4
1
read-write
0
Clock cycles delay Disabled
#0
1
Clock cycles delay Enabled
#1
PD_WU_INT_EN
Power-down Mode Wake-up Interrupt Enable (Write Protected)\nThe interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.
5
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
PD_WU_STS
Power-down Mode Wake-up Interrupt Status
Set by power-down wake-up event , it indicates that resume from Power-down mode
The flag is set if the GPIO, USB, UART, WDT, CAN, I2C, TIMER, ACMP, BOD or RTC wake-up occurred.
Write 1 to clear the bit to 0.
Note: This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1.
6
1
read-write
PWR_DOWN_EN
System Power-down Enable Bit (Write Protected)\nWhen this bit is set to 1, Power-down mode is enabled and chip power-down behavior will depend on the PD_WAIT_CPU bit\n(a) If the PD_WAIT_CPU is 0, then the chip enters Power-down mode immediately after the PWR_DOWN_EN bit set.\n(b) if the PD_WAIT_CPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode\nWhen chip wakes up from Power-down mode, this bit is cleared by hardware. User needs to set this bit again for next power-down.\nIn Power-down mode, external 4~24 MHz high speed crystal oscillator and the internal 22.1184 MHz high speed oscillator will be disabled in this mode, but the external 32.768 kHz low speed crystal and internal 10 kHz low speed oscillator are not controlled by Power-down mode.\nIn Power- down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from external 32.768 kHz low speed crystal oscillator or the internal 10 kHz low speed oscillator.\n
7
1
read-write
0
Chip operating normally or chip in Idle mode because of WFI command
#0
1
Chip enters Power-down mode instantly or waits CPU sleep command WFI
#1
XTL12M_EN
External 4~24 MHz High Speed Crystal Enable (Write Protected)\nThe bit default value is set by flash controller user configuration register config0 [26:24]. When the default clock source is from external 4~24 MHz high speed crystal, this bit is set to 1 automatically.\n
0
1
read-write
0
External 4~24 MHz high speed crystal oscillator Disabled
#0
1
External 4~24 MHz high speed crystal oscillator Enabled
#1
XTL32K_EN
External 32.768 KHz Low Speed Crystal Enable (Write Protected)\n
1
1
read-write
0
External 32.768 kHz low speed crystal oscillator Disabled
#0
1
External 32.768 kHz low speed crystal oscillator Enabled (Normal operation)
#1
CRC
PDMA Register Map
PDMA
0x0
0x0
0x8
registers
n
0x14
0x4
registers
n
0x1C
0xC
registers
n
0x80
0xC
registers
n
0xC
0x4
registers
n
CHECKSUM
CRC_CHECKSUM
CRC Checksum Register
0x88
-1
read-only
n
0x0
0x0
CRC_CHECKSUM
CRC Checksum Register\nThis fields indicates the CRC checksum result
0
32
read-only
CTL
CRC_CTL
CRC Control Register
0x0
-1
read-write
n
0x0
0x0
CHECKSUM_COM
Checksum 1's Complement\nThis bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.\n
27
1
read-write
0
1's complement for CRC checksum Disabled
#0
1
1's complement for CRC checksum Enabled
#1
CHECKSUM_RVS
Checksum Reverse\nThis bit is used to enable the bit order reverse function for write data value in CRC_CHECKSUM register.\nNote: If the checksum result is 0XDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB
25
1
read-write
0
Bit order reverse for CRC checksum Disabled
#0
1
Bit order reverse for CRC checksum Enabled
#1
CPU_WDLEN
CPU Write Data Length
This field indicates the CPU write data length only when operating in CPU PIO mode.
Note1: This field is only valid when operating in CPU PIO mode.
Note2: When the write data length is 8-bit mode, the valid data in CRC_WDATA register is only CRC_WDATA [7:0] bits if the write data length is 16-bit mode, the valid data in CRC_WDATA register is only CRC_WDATA [15:0].
28
2
read-write
0
The write data length is 8-bit mode
#00
1
The write data length is 16-bit mode
#01
2
The write data length is 32-bit mode
#10
3
Reserved
#11
CRCCEN
CRC Channel Enable\nSetting this bit to 1 enables CRC operation.\n
0
1
read-write
CRC_MODE
CRC Polynomial Mode\nThis field indicates the CRC operation polynomial mode.\n
30
2
read-write
0
CRC-CCITT Polynomial Mode
#00
1
CRC-8 Polynomial Mode
#01
2
CRC-16 Polynomial Mode
#10
3
CRC-32 Polynomial Mode
#11
CRC_RST
CRC Engine Reset\nNote: When operated in CPU PIO mode, setting this bit will reload the initial seed value (CRC_SEED register).
1
1
read-write
0
No effect
#0
1
Reset the internal CRC state machine and internal buffer. The others contents of CRC_CTL register will not be cleared. This bit will be cleared automatically
#1
TRIG_EN
Trigger Enable\nThis bit is used to trigger the CRC DMA transfer.\nNote1: If this bit asserts which indicates the CRC engine operation in CRC DMA mode, do not fill in any data in CRC_WDATA register.\nNote2: When CRC DMA transfer completed, this bit will be cleared automatically.\nNote3: If the bus error occurs when CRC DMA transfer data, all CRC DMA transfer will be stopped. Software must reset all DMA channel before trigger DMA again.
23
1
read-write
0
No effect
#0
1
CRC DMA data read or write transfer Enabled
#1
WDATA_COM
Write Data 1's Complement\nThis bit is used to enable the 1's complement function for write data value in CRC_WDTAT register.\n
26
1
read-write
0
1's complement for CRC write data in Disabled
#0
1
1's complement for CRC write data in Enabled
#1
WDATA_RVS
Write Data Order Reverse\nThis bit is used to enable the bit order reverse function for write data value in CRC_WDTAT register.\nNote: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB
24
1
read-write
0
Bit order reverse for CRC write data in Disabled
#0
1
Bit order reverse for CRC write data in Enabled (per byte)
#1
DMABCR
CRC_DMABCR
CRC DMA Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
CRC_DMABCR
CRC DMA Transfer Byte Count Register\nThis field indicates a 16-bit total transfer byte count number of CRC DMA\n
0
16
read-write
DMACBCR
CRC_DMACBCR
CRC DMA Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
CRC_DMACBCR
CRC DMA Current Remained Byte Count Register (Read Only)\nThis field indicates the current remained byte count of CRC DMA.\nNote: Setting CRC_RST bit to 1 will clear this register value.
0
16
read-only
DMACSAR
CRC_DMACSAR
CRC DMA Current Source Address Register
0x14
read-only
n
0x0
0x0
CRC_DMACSAR
CRC DMA Current Source Address Register (Read Only)\nThis field indicates the current source address where the CRC DMA transfer just occurs.\n
0
32
read-only
DMAIER
CRC_DMAIER
CRC DMA Interrupt Enable Register
0x20
-1
read-write
n
0x0
0x0
CRC_BLKD_IE
CRC DMA Block Transfer Done Interrupt Enable
Enable this bit will generate the CRC DMA Transfer Done interrupt signal while CRC_BLKD_IF bit (CRCDMAISR [1] CRC DMA Block Transfer Done Interrupt Flag) is set to 1.
1
1
read-write
0
Interrupt generator Disabled when CRC DMA transfer done
#0
1
Interrupt generator Enabled when CRC DMA transfer done
#1
CRC_TABORT_IE
CRC DMA Read/Write Target Abort Interrupt Enable
Enable this bit will generate the CRC DMA Target Abort interrupt signal while CRC_TARBOT_IF bit (CRCDMAISR [0] CRC DMA Read/Write Target Abort Interrupt Flag) is set to 1.
0
1
read-write
0
Target abort interrupt generation Disabled during CRC DMA transfer
#0
1
Target abort interrupt generation Enabled during CRC DMA transfer
#1
DMAISR
CRC_DMAISR
CRC DMA Interrupt Status Register
0x24
read-write
n
0x0
0x0
CRC_BLKD_IF
CRC DMA Block Transfer Done Interrupt Flag\nThis bit indicates that CRC DMA transfer has finished or not.\nIt is cleared by writing 1 to it through software..\n(When CRC DMA transfer done, TRIG_EN bit will be cleared automatically)
1
1
read-write
0
Not finished if TRIG_EN bit has enabled
#0
1
CRC transfer done if TRIG_EN bit has enabled
#1
CRC_TABORT_IF
CRC DMA Read/Write Target Abort Interrupt Flag\nThis bit indicates that CRC bus has error or not during CRC DMA transfer.\nIt is cleared by writing 1 to it through software.
0
1
read-write
0
No bus error response received during CRC DMA transfer
#0
1
Bus error response received during CRC DMA transfer
#1
DMASAR
CRC_DMASAR
CRC DMA Source Address Register
0x4
read-write
n
0x0
0x0
CRC_DMASAR
CRC DMA Transfer Source Address Register\nThis field indicates a 32-bit source address of CRC DMA.\nNote: The source address must be word alignment
0
32
read-write
SEED
CRC_SEED
CRC Seed Register
0x84
-1
read-write
n
0x0
0x0
CRC_SEED
CRC Seed Register\nThis field indicates the CRC seed value.
0
32
read-write
WDATA
CRC_WDATA
CRC Write Data Register
0x80
read-write
n
0x0
0x0
CRC_WDATA
CRC Write Data Register
When operating in CPU PIO mode, software can write data to this field to perform CRC operation.
When operating in DMA mode, this field indicates the DMA read data from memory and cannot be written.
Note: When the write data length is 8-bit mode, the valid data in CRC_WDATA register is only CRC_WDATA [7:0] bits if the write data length is 16-bit mode, the valid data in CRC_WDATA register is only CRC_WDATA [15:0].
0
32
read-write
FMC
FMC Register Map
FMC
0x0
0x0
0x1C
registers
n
0x40
0x4
registers
n
DFBADR
DFBADR
Data Flash Base Address
0x14
read-only
n
0x0
0x0
DFBADR
Data Flash Base Address\nThis register indicates Data Flash start address. It is read only.\nFor 128 KB flash memory device, the Data Flash size is defined by user configuration, register content is loaded from Config1 when chip is powered on but for 64/32 KB device, it is fixed at 0x0001_F000.
0
32
read-only
FATCON
FATCON
Flash Access Time Control Register
0x18
read-write
n
0x0
0x0
LFOM
Low Frequency Optimization Mode (Write Protected)\nWhen chip operation frequency is lower than 25 MHz, chip can work more efficiently by setting this bit to 1\n
4
1
read-write
0
Low frequency optimization mode Disabled
#0
1
Low frequency optimization mode Enabled
#1
ISPADR
ISPADR
ISP Address Register
0x4
read-write
n
0x0
0x0
ISPADR
ISP Address\nThe NuMicro( NUC200 Series has a maximum 32Kx32 (128 KB) of embedded Flash, which supports word program only. ISPADR[1:0] must be kept 00b for ISP operation.
0
32
read-write
ISPCMD
ISPCMD
ISP Command Register
0xC
read-write
n
0x0
0x0
ISPCMD
ISP Command\n
0
6
read-write
ISPCON
ISPCON
ISP Control Register
0x0
read-write
n
0x0
0x0
APUEN
APROM Update Enable (Write Protected)\n
3
1
read-write
0
APROM cannot be updated when chip runs in APROM
#0
1
APROM can be updated when chip runs in APROM
#1
BS
Boot Select (Write Protected)\nSet/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in Config0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened\n
1
1
read-write
0
Boot from APROM
#0
1
Boot from LDROM
#1
CFGUEN
Enable Config-bits Update by ISP (Write Protected)\n
4
1
read-write
0
ISP update config-bits Disabled
#0
1
ISP update config-bits Enabled
#1
ISPEN
ISP Enable (Write Protected)\nISP function enable bit. Set this bit to enable ISP function.\n
0
1
read-write
0
ISP function Disabled
#0
1
ISP function Enabled
#1
ISPFF
ISP Fail Flag (Write Protected)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0\n(2) LDROM writes to itself if LDUEN is set to 0\n(3) CONFIG is erased/programmed if CFGUEN is set to 0\n(4) Destination address is illegal, such as over an available range\nWrite 1 to clear to this bit to 0.
6
1
read-write
LDUEN
LDROM Update Enable (Write Protected)\nLDROM update enable bit.\n
5
1
read-write
0
LDROM cannot be updated
#0
1
LDROM can be updated when chip runs in APROM
#1
ISPDAT
ISPDAT
ISP Data Register
0x8
read-write
n
0x0
0x0
ISPDAT
ISP Data\nWrite data to this register before ISP program operation\nRead data from this register after ISP read operation
0
32
read-write
ISPSTA
ISPSTA
ISP Status Register
0x40
read-write
n
0x0
0x0
CBS
Chip Boot Selection (Read Only)\nThis is a mirror of CBS in Config0.
1
2
read-only
ISPFF
ISP Fail Flag (Write Protected)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself\n(2) LDROM writes to itself\n(3) CONFIG is erased/programmed if CFGUEN is set to 0\n(4) Destination address is illegal, such as over an available range\nWrite 1 to clear this bit.\nNote: The function of this bit is the same as ISPCON bit6
6
1
read-write
ISPGO
ISP Start Trigger (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is the same as ISPTRG bit0
0
1
read-only
0
ISP operation finished
#0
1
ISP operation progressed
#1
VECMAP
Vector Page Mapping Address (Read Only)\nThe current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0], 9'h000} ~ {VECMAP[11:0], 9'h1FF}
9
12
read-only
ISPTRG
ISPTRG
ISP Trigger Control Register
0x10
read-write
n
0x0
0x0
ISPGO
ISP Start Trigger (Write Protected)
Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
This bit is the protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100
0
1
read-write
0
ISP operation finished
#0
1
ISP progressed
#1
GCR
GCR Register Map
GCR
0x0
0x0
0x14
registers
n
0x100
0x4
registers
n
0x18
0x8
registers
n
0x24
0x4
registers
n
0x30
0x18
registers
n
0x50
0x4
registers
n
0x58
0x4
registers
n
0x80
0xC
registers
n
ALT_MFP
ALT_MFP
Alternative Multiple Function Pin Control Register
0x50
read-write
n
0x0
0x0
PA15_I2SMCLK
Bits PA15_SC2PWR (ALT_MFP1[12]), PA15_I2SMCLK (ALT_MFP[9]) and GPA_MFP[15] Determine the PA.15 Function\n
9
1
read-write
PA7_S21
Bits PA7_SC1DAT (ALT_MFP1[6]), PA7_S21 (ALT_MFP[2]) and GPA_MFP[7] Determine the PA.7 Function\n
2
1
read-write
PB10_S01
Bits PB10_S01 and GPB_MFP[10] Determine the PB.10 Function\n
0
1
read-write
PB11_PWM4
Bits PB11_PWM4 and GPB_MFP[11] Determine the PB.11 Function\n
4
1
read-write
PB14_S31
Bits PB14_S31 and GPB_MFP[14] Determine the PB.14 Function\n
3
1
read-write
PB15_T0EX
Bits PB15_T0EX (ALT_MFP[24]) and GPB_MFP[15] Determine the PB.15 Function\n
24
1
read-write
PB2_CPO0
Bits PB2_CPO0 (ALT_MFP[30]), PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] Determine the PB.2 Function\n
30
1
read-write
PB2_T2EX
Bits PB2_CPO0 (ALT_MFP[30]), PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] Determine the PB.2 Function\n
26
1
read-write
PB3_T3EX
Bits PB3_SC2CD (ALT_MFP1[14]), PB3_T3EX (ALT_MFP[27]) and GPB_MFP[3] Determine the PB.3 Function\n
27
1
read-write
PB8_CLKO
Bits PB8_CLKO (ALT_MFP[29]) and GPB_MFP[8] Determine the PB.8 Function\n
29
1
read-write
PB9_S11
Bits PB9_S11 and GPB_MFP[9] Determine the PB.9 Function\n
1
1
read-write
PC0_I2SLRCLK
Bits PC0_I2SLRCLK and GPC_MFP[0] Determine the PC.0 Function\n
5
1
read-write
PC1_I2SBCLK
Bits PC1_I2SBCLK and GPC_MFP[1] Determine the PC.1 Function\n
6
1
read-write
PC2_I2SDI
Bits PC2_I2SDI and GPC_MFP[2] Determine the PC.2 Function\n
7
1
read-write
PC3_I2SDO
Bits PC3_I2SDO and GPC_MFP[3] Determine the PC.3 Function\n
8
1
read-write
PE5_T1EX
Bits GPE_MFP5 and PE5_T1EX (ALT_MFP[25]) Determine the PE.5 Function\n
25
1
read-write
ALT_MFP1
ALT_MFP1
Alternative Multiple Function Pin Control Register 1
0x58
read-write
n
0x0
0x0
PA0_SC0PWR
Bits PA0_SC0PWR (ALT_MFP1[2]) and GPA_MFP[0] Determine the PA.0 Function\n
2
1
read-write
PA12_SC2DAT
Bits PA12_SC2DAT (ALT_MFP1[11]) and GPA_MFP[12] Determine the PA.12 Function\n
11
1
read-write
PA13_SC2CLK
Bits PA13_SC2CLK (ALT_MFP1[10]) and GPA_MFP[13] Determine the PA.13 Function\n
10
1
read-write
PA14_SC2RST
Bits PA14_SC2RST (ALT_MFP1[13]) and GPA_MFP[14] Determine the PA.14 Function\n
13
1
read-write
PA15_SC2PWR
Bits PA15_SC2PWR (ALT_MFP1[12]), PA15_I2SMCLK (ALT_MFP[9]) and GPA_MFP[15] Determine the PA.15 Function\n
12
1
read-write
PA1_SC0RST
Bits PA1_SC0RST (ALT_MFP1[3]) and GPA_MFP[1] Determine the PA.1 Function\n
3
1
read-write
PA2_SC0CLK
Bits PA2_SC0CLK (ALT_MFP1[0]) and GPA_MFP[2] Determine the PA.2 Function\n
0
1
read-write
PA3_SC0DAT
Bits PA3_SC0DAT (ALT_MFP1[1]) and GPA_MFP[3] Determine the PA.3 Function\n
1
1
read-write
PA4_SC1PWR
Bits PA4_SC1PWR (ALT_MFP1[7]) and GPA_MFP[4] Determine the PA.4 Function\n
7
1
read-write
PA5_SC1RST
Bits PA5_SC1RST (ALT_MFP1[8]) and GPA_MFP[5] Determine the PA.5 Function\n
8
1
read-write
PA6_SC1CLK
Bits PA6_SC1CLK (ALT_MFP1[5]) and GPA_MFP[6] Determine the PA.6 Function\n
5
1
read-write
PA7_SC1DAT
Bits PA7_SC1DAT (ALT_MFP1[6]), PA7_S21 (ALT_MFP[2]) and GPA_MFP[7] Determine the PA.7 Function\n
6
1
read-write
PB3_SC2CD
Bits PB3_SC2CD (ALT_MFP1[14]), PB3_T3EX (ALT_MFP[27]) and GPB_MFP[3] Determine the PB.3 Function\n
14
1
read-write
PC6_SC0CD
Bits PC6_SC0CD (ALT_MFP1[4]) and GPC_MFP[6] Determine the PC.6 Function\n
4
1
read-write
PC7_SC1CD
Bits PC7_SC1CD (ALT_MFP1[9]) and GPC_MFP[7] Determine the PC.7 Function\n
9
1
read-write
BODCR
BODCR
Brown-out Detector Control Register
0x18
-1
read-write
n
0x0
0x0
BOD_EN
Brown-out Detector Enable (Write Protected)
The default value is set by flash controller user configuration register config0 bit[23]
This bit is the protected bit which means programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
0
1
read-write
0
Brown-out Detector function Disabled
#0
1
Brown-out Detector function Enabled
#1
BOD_INTF
Brown-out Detector Interrupt Flag\nWrite 1 to clear this bit to 0.
4
1
read-write
0
Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BOD_VL setting
#0
1
When Brown-out Detector detects the VDD is dropped down through the voltage of BOD_VL setting or the VDD is raised up through the voltage of BOD_VL setting, this bit is set to 1 and the Brown-out interrupt is requested if Brown-out interrupt is enabled
#1
BOD_LPM
Brown-out Detector Low Power Mode (Write Protected)
The BOD consumes about 100 uA in Normal mode, and the low power mode can reduce the current to about 1/10 but slow the BOD response.
This bit is the protected bit which means programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
5
1
read-write
0
BOD operated in Normal mode (default)
#0
1
BOD Low Power mode Enabled
#1
BOD_OUT
Brown-out Detector Output Status\n
6
1
read-write
0
Brown-out Detector output status is 0. It means the detected voltage is higher than BOD_VL setting or BOD_EN is 0
#0
1
Brown-out Detector output status is 1. It means the detected voltage is lower than BOD_VL setting. If the BOD_EN is 0, BOD function disabled , this bit always responds to 0
#1
BOD_RSTEN
Brown-out Reset Enable (Write Protected)
While the Brown-out Detector function is enabled (BOD_EN high) and BOD reset function is enabled (BOD_RSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BOD_OUT high).
The default value is set by flash controller user configuration register config0 bit[20].
This bit is the protected bit. It means programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
3
1
read-write
0
Brown-out INTERRUPT function Enabled
#0
1
Brown-out RESET function Enabled
#1
BOD_VL
Brown-out Detector Threshold Voltage Selection (Write Protected)\n
1
2
read-write
LVR_EN
Low Voltage Reset Enable (Write Protected)
The LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.
This bit is the protected bit. It means programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100
7
1
read-write
0
Low Voltage Reset function Disabled
#0
1
Low Voltage Reset function Enabled - After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default)
#1
GPA_MFP
GPA_MFP
GPIOA Multiple Function and Input Type Control Register
0x30
read-write
n
0x0
0x0
GPA_MFP0
PA.0 Pin Function Selection\n
0
1
read-write
GPA_MFP1
PA.1 Pin Function Selection\n
1
1
read-write
GPA_MFP10
PA.10 Pin Function Selection\n
10
1
read-write
GPA_MFP11
PA.11 Pin Function Selection\n
11
1
read-write
GPA_MFP12
PA.12 Pin Function Selection\n
12
1
read-write
GPA_MFP13
PA.13 Pin Function Selection\n
13
1
read-write
GPA_MFP14
PA.14 Pin Function Selection\n
14
1
read-write
GPA_MFP15
PA.15 Pin Function Selection\n
15
1
read-write
GPA_MFP2
PA.2 Pin Function Selection\n
2
1
read-write
GPA_MFP3
PA.3 Pin Function Selection\n
3
1
read-write
GPA_MFP4
PA.4 Pin Function Selection\n
4
1
read-write
GPA_MFP5
PA.5 Pin Function Selection\n
5
1
read-write
GPA_MFP6
PA.6 Pin Function Selection\n
6
1
read-write
GPA_MFP7
PA.7 Pin Function Selection\n
7
1
read-write
GPA_MFP8
PA.8 Pin Function Selection\n
8
1
read-write
GPA_MFP9
PA.9 Pin Function Selection\n
9
1
read-write
GPA_TYPEn
None
16
16
read-write
0
GPIOA[15:0] I/O input Schmitt Trigger function Disabled
0
1
GPIOA[15:0] I/O input Schmitt Trigger function Enabled
1
GPB_MFP
GPB_MFP
GPIOB Multiple Function and Input Type Control Register
0x34
read-write
n
0x0
0x0
GPB_MFP0
PB.0 Pin Function Selection\n
0
1
read-write
0
GPIOB[0] is selected to the pin PB.0
#0
1
UART0_RXD function is selected to the pin PB.0
#1
GPB_MFP1
PB.1 Pin Function Selection\n
1
1
read-write
0
GPIOB[1] is selected to the pin PB.1
#0
1
UART0_TXD function is selected to the pin PB.1
#1
GPB_MFP10
PB.10 Pin Function Selection\n
10
1
read-write
GPB_MFP11
PB.11 Pin Function Selection\n
11
1
read-write
GPB_MFP12
Reserved.
12
1
read-write
GPB_MFP13
PB.13 Pin Function Selection\n
13
1
read-write
GPB_MFP14
PB.14 Pin Function Selection\n
14
1
read-write
GPB_MFP15
PB.15 Pin Function Selection\n
15
1
read-write
GPB_MFP2
PB.2 Pin Function Selection\n
2
1
read-write
GPB_MFP3
PB.3 Pin Function Selection\n
3
1
read-write
GPB_MFP4
PB.4 Pin Function Selection\n
4
1
read-write
0
The GPIOB[4] is selected to the pin PB.4
#0
1
The UART1_RXD function is selected to the pin PB.4
#1
GPB_MFP5
PB 5 Pin Function Selection\n
5
1
read-write
0
The GPIOB[5] is selected to the pin PB.5
#0
1
The UART1_TXD function is selected to the pin PB.5
#1
GPB_MFP6
PB.6 Pin Function Selection\n
6
1
read-write
0
The GPIOB[6] is selected to the pin PB.6
#0
1
The UART1_nRST function is selected to the pin PB.6
#1
GPB_MFP7
PB.7 Pin Function Selection\n
7
1
read-write
0
The GPIOB[7] is selected to the pin PB.7
#0
1
The UART1_nCST function is selected to the pin PB.7
#1
GPB_MFP8
PB.8 Pin Function Selection\n
8
1
read-write
GPB_MFP9
PB.9 Pin Function Selection\n
9
1
read-write
GPB_TYPEn
None
16
16
read-write
0
GPIOB[15:0] I/O input Schmitt Trigger function Disabled
0
1
GPIOB[15:0] I/O input Schmitt Trigger function Enabled
1
GPC_MFP
GPC_MFP
GPIOC Multiple Function and Input Type Control Register
0x38
read-write
n
0x0
0x0
GPC_MFP0
PC.0 Pin Function Selection\n
0
1
read-write
GPC_MFP1
PC.1 Pin Function Selection\n
1
1
read-write
GPC_MFP10
PC.10 Pin Function Selection\n
10
1
read-write
0
GPIOC[10] is selected to the pin PC.10
#0
1
SPI1_MISO0 (master input, slave output pin-0) function selected to the pin PC.10
#1
GPC_MFP11
PC.11 Pin Function Selection\n
11
1
read-write
0
GPIOC[11] selected to the pin PC.11
#0
1
SPI1_MOSI0 (master output, slave input pin-0) function selected to the pin PC.11
#1
GPC_MFP12
PC.12 Pin Function Selection\n
12
1
read-write
0
GPIOC[12] is selected to the pin PC.12
#0
1
SPI1_MISO1 (master input, slave output pin-1) function is selected to the pin PC.12
#1
GPC_MFP13
PC.13 Pin Function Selection\n
13
1
read-write
0
GPIOC[13] is selected to the pin PC.13
#0
1
SPI1_MOSI1 (master output, slave input pin-1) function is selected to the pin PC.13
#1
GPC_MFP14
PC.14 Pin Function Selection\n
14
1
read-write
GPC_MFP15
PC.15 Pin Function Selection\n
15
1
read-write
GPC_MFP2
PC.2 Pin Function Selection\n
2
1
read-write
GPC_MFP3
PC.3 Pin Function Selection\n
3
1
read-write
GPC_MFP4
PC.4 Pin Function Selection\n
4
1
read-write
0
GPIOC[4] is selected to the pin PC.4
#0
1
SPI0_MISO1 (master input, slave output pin-1) function is selected to the pin PC.4
#1
GPC_MFP5
PC.5 Pin Function Selection\n
5
1
read-write
0
GPIOC[5] is selected to the pin PC.5
#0
1
SPI0_MOSI1 (master output, slave input pin-1) function is selected to the pin PC.5
#1
GPC_MFP6
PC.6 Pin Function Selection\n
6
1
read-write
GPC_MFP7
PC.7 Pin Function Selection\n
7
1
read-write
GPC_MFP8
PC.8 Pin Function Selection\n
8
1
read-write
0
GPIOC[8] selected to the pin PC.8
#0
1
SPI1_SS0 function selected to the pin PC.8
#1
GPC_MFP9
PC.9 Pin Function Selection\n
9
1
read-write
0
GPIOC[9] selected to the pin PC.9
#0
1
SPI1_CLK function selected to the pin PC.9
#1
GPC_TYPEn
None
16
16
read-write
0
GPIOC[15:0] I/O input Schmitt Trigger function Disabled
0
1
GPIOC[15:0] I/O input Schmitt Trigger function Enabled
1
GPD_MFP
GPD_MFP
GPIOD Multiple Function and Input Type Control Register
0x3C
read-write
n
0x0
0x0
GPD_MFP0
PD.0 Pin Function Selection\n
0
1
read-write
0
GPIOD[0] selected to the pin PD.0
#0
1
SPI2_SS0 function selected to the pin PD.0
#1
GPD_MFP1
PD.1 Pin Function Selection\n
1
1
read-write
0
GPIOD[1] selected to the pin PD.1
#0
1
SPI2_SPICLK function selected to the pin PD.1
#1
GPD_MFP10
PD.10 Pin Function Selection \n
10
1
read-write
0
GPIOD[10] is selected to the pin PD.10
#0
1
SPI3_MISO0 (master input, slave output pin-0) function is selected to the pin PD.10
#1
GPD_MFP11
PD.11 Pin Function Selection\n
11
1
read-write
0
GPIOD[11] is selected to the pin PD.11
#0
1
SPI3_MOSI0 (master output, slave input pin-0) function is selected to the pin PD.11
#1
GPD_MFP12
PD.12 Pin Function Selection \n
12
1
read-write
0
GPIOD[12] is selected to the pin PD.12
#0
1
SPI3_MISO1 (master input, slave output pin-1) function is selected to the pin PD.12
#1
GPD_MFP13
PD.13 Pin Function Selection \n
13
1
read-write
0
GPIOD[13] is selected to the pin PD.13
#0
1
SPI3_MOSI1 (master output, slave input pin-1) function is selected to the pin PD.13
#1
GPD_MFP14
PD.14 Pin Function Selection \n
14
1
read-write
0
GPIOD[14] selected to the pin PD.14
#0
1
UART2_RXD function is selected to the pin PD.14
#1
GPD_MFP15
PD.15 Pin Function Selection \n
15
1
read-write
0
GPIOD[15] selected to the pin PD.15
#0
1
UART2_TXD function is selected to the pin PD.15
#1
GPD_MFP2
PD.2 Pin Function Selection\n
2
1
read-write
0
GPIOD[2] selected to the pin PD.2
#0
1
SPI2_MISO0 (master input, slave output pin-0) function selected to the pin PD.2
#1
GPD_MFP3
PD.3 Pin Function Selection\n
3
1
read-write
0
GPIOD[3] selected to the pin PD.3
#0
1
SPI2_MOSI0 (master output, slave input pin-0) function selected to the pin PD.3
#1
GPD_MFP4
PD.4 Pin Function Selection \n
4
1
read-write
0
GPIOD[4]is selected to the pin PD.4
#0
1
SPI2_MISO1 (master input, slave output pin-1) function is selected to the pin PD.4
#1
GPD_MFP5
PD.5 Pin Function Selection \n
5
1
read-write
0
GPIOD[5] is selected to the pin PD.5
#0
1
SPI2_MOSI1 (master output, slave input pin-1) function is selected to the pin PD.5
#1
GPD_MFP6
PD.6 Pin Function Selection\nReserved
6
1
read-write
GPD_MFP7
PD.7 Pin Function Selection \nReserved
7
1
read-write
GPD_MFP8
PD.8 Pin Function Selection\n
8
1
read-write
0
GPIOD[8] is selected to the pin PD8
#0
1
SPI3_SS0 function is selected to the pin PD8
#1
GPD_MFP9
PD.9 Pin Function Selection\n
9
1
read-write
0
GPIOD[9] is selected to the pin PD.9
#0
1
SPI3_CLK function is selected to the pin PD.9
#1
GPD_TYPEn
None
16
16
read-write
0
GPIOD[15:0] I/O input Schmitt Trigger function Disabled
0
1
GPIOD[15:0] I/O input Schmitt Trigger function Enabled
1
GPE_MFP
GPE_MFP
GPIOE Multiple Function and Input Type Control Register
0x40
read-write
n
0x0
0x0
GPE_MFP0
PE.0 Pin Function Selection\n
0
1
read-write
0
GPIOE[0] is selected to the pin PE.0
#0
1
PWM6 function is selected to the pin PE.0
#1
GPE_MFP1
PE.1 Pin Function Selection \n
1
1
read-write
0
GPIOE[1] is selected to the pin PE.1
#0
1
PWM7 function is selected to the pin PE.1
#1
GPE_MFP5
PE.5 Pin Function Selection\n
5
1
read-write
GPE_TYPEn
None
16
16
read-write
0
GPIOE[15:0] I/O input Schmitt Trigger function Disabled
0
1
GPIOE[15:0] I/O input Schmitt Trigger function Enabled
1
GPF_MFP
GPF_MFP
GPIOF Multiple Function and Input Type Control Register
0x44
read-write
n
0x0
0x0
GPF_MFP0
PF.0 Pin Function Selection\nNote: This bit is read only and is decided by user configuration CGPFMFP (Config0[27]).
0
1
read-write
0
GPIOF[0] is selected to the pin PF.0
#0
1
XT1_OUT function is selected to the pin PF.0
#1
GPF_MFP1
PF.1 Pin Function Selection \nNote: This bit is read only and is decided by user configuration CGPFMFP (Config0[27]).
1
1
read-write
0
GPIOF[1] is selected to the pin PF.1
#0
1
XT1_IN function is selected to the pin PF.1
#1
GPF_MFP2
PF.2 Pin Function Selection\n
2
1
read-write
0
GPIOF[2] is selected to the pin PF.2
#0
1
PS2_DAT function is selected to the pin PF.2
#1
GPF_MFP3
PF.3 Pin Function Selection \n
3
1
read-write
0
GPIOF[3] is selected to the pin PF.3
#0
1
PS2_CLK function is selected to the pin PF.3
#1
GPF_TYPEn
None
16
4
read-write
0
GPIOF[3:0] I/O input Schmitt Trigger function Disabled
0
1
GPIOF[3:0] I/O input Schmitt Trigger function Enabled
1
IPRSTC1
IPRSTC1
IP Reset Control Register 1
0x8
read-write
n
0x0
0x0
CHIP_RST
CHIP One-shot Reset (Write Protected)
Setting this bit will reset the whole chip, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
The CHIP_RST is the same as the POR reset, all the chip controllers are reset and the chip setting from flash are also reload.
For the difference between CHIP_RST and SYSRESETREQ, please refer to section 5.2.2
This bit is the protected bit. It means programming this bit needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100
0
1
read-write
0
CHIP normal operation
#0
1
CHIP one-shot reset
#1
CPU_RST
CPU Kernel One-shot Reset (Write Protected)
Setting this bit will only reset the CPU kernel and Flash Memory Controller(FMC), and this bit will automatically return 0 after the two clock cycles
This bit is the protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100
1
1
read-write
0
CPU normal operation
#0
1
CPU one-shot reset
#1
PDMA_RST
PDMA Controller Reset (Write Protected)
Setting this bit to 1 will generate a reset signal to the PDMA. User need to set this bit to 0 to release from reset state.
This bit is the protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
2
1
read-write
0
PDMA controller normal operation
#0
1
PDMA controller reset
#1
IPRSTC2
IPRSTC2
IP Reset Control Register 2
0xC
read-write
n
0x0
0x0
ACMP_RST
Analog Comparator Controller Reset\n
22
1
read-write
0
Analog Comparator controller normal operation
#0
1
Analog Comparator controller reset
#1
ADC_RST
ADC Controller Reset\n
28
1
read-write
0
ADC controller normal operation
#0
1
ADC controller reset
#1
GPIO_RST
GPIO Controller Reset\n
1
1
read-write
0
GPIO controller normal operation
#0
1
GPIO controller reset
#1
I2C0_RST
I2C0 Controller Reset\n
8
1
read-write
0
I2C0 controller normal operation
#0
1
I2C0 controller reset
#1
I2C1_RST
I2C1 Controller Reset\n
9
1
read-write
0
I2C1 controller normal operation
#0
1
I2C1 controller reset
#1
I2S_RST
I2S Controller Reset\n
29
1
read-write
0
I2S controller normal operation
#0
1
I2S controller reset
#1
PS2_RST
PS/2 Controller Reset\n
23
1
read-write
0
PS/2 controller normal operation
#0
1
PS/2 controller reset
#1
PWM03_RST
PWM03 Controller Reset\n
20
1
read-write
0
PWM03 controller normal operation
#0
1
PWM03 controller reset
#1
PWM47_RST
PWM47 Controller Reset\n
21
1
read-write
0
PWM47 controller normal operation
#0
1
PWM47 controller reset
#1
SPI0_RST
SPI0 Controller Reset\n
12
1
read-write
0
SPI0 controller normal operation
#0
1
SPI0 controller reset
#1
SPI1_RST
SPI1 Controller Reset\n
13
1
read-write
0
SPI1 controller normal operation
#0
1
SPI1 controller reset
#1
SPI2_RST
SPI2 Controller Reset \n
14
1
read-write
0
SPI2 controller normal operation
#0
1
SPI2 controller reset
#1
SPI3_RST
SPI3 Controller Reset \n
15
1
read-write
0
SPI3 controller normal operation
#0
1
SPI3 controller reset
#1
TMR0_RST
Timer0 Controller Reset\n
2
1
read-write
0
Timer0 controller normal operation
#0
1
Timer0 controller reset
#1
TMR1_RST
Timer1 Controller Reset\n
3
1
read-write
0
Timer1 controller normal operation
#0
1
Timer1 controller reset
#1
TMR2_RST
Timer2 Controller Reset\n
4
1
read-write
0
Timer2 controller normal operation
#0
1
Timer2 controller reset
#1
TMR3_RST
Timer3 Controller Reset\n
5
1
read-write
0
Timer3 controller normal operation
#0
1
Timer3 controller reset
#1
UART0_RST
UART0 Controller Reset\n
16
1
read-write
0
UART0 controller normal operation
#0
1
UART0 controller reset
#1
UART1_RST
UART1 Controller Reset\n
17
1
read-write
0
UART1 controller normal operation
#0
1
UART1 controller reset
#1
UART2_RST
UART2 Controller Reset \n
18
1
read-write
0
UART2 controller normal operation
#0
1
UART2 controller reset
#1
USBD_RST
USB Device Controller Reset\n
27
1
read-write
0
USB device controller normal operation
#0
1
USB device controller reset
#1
IPRSTC3
IPRSTC3
IP Reset Control Register 3
0x10
read-write
n
0x0
0x0
SC0_RST
SC0 Controller Reset\n
0
1
read-write
0
SC0 controller normal operation
#0
1
SC0 controller reset
#1
SC1_RST
SC1 Controller Reset\n
1
1
read-write
0
SC1 controller normal operation
#0
1
SC1 controller reset
#1
SC2_RST
SC2 Controller Reset\n
2
1
read-write
0
SC2 controller normal operation
#0
1
SC2 controller reset
#1
IRCTRIMCTL
IRCTRIMCTL
IRC Trim Control Register
0x80
read-write
n
0x0
0x0
CLKERR_STOP_EN
Clock Error Stop Enable\nWhen this bit is set to 1, the trim operation is stopped if clock is inaccuracy.\nWhen this bit is set to 0, the trim operation is keep going if clock is inaccuracy.
8
1
read-write
TRIM_LOOP
Trim Calculation Loop\nThis field defines that trim value calculation is based on how many 32.768 kHz clocks in.\nFor example, if TRIM_LOOP is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.\n
4
2
read-write
0
Trim value calculation is based on average difference in 4 clocks
#00
1
Trim value calculation is based on average difference in 8 clocks
#01
2
Trim value calculation is based on average difference in 16 clocks
#10
3
Trim value calculation is based on average difference in 32 clocks
#11
TRIM_RETRY_CNT
Trim Value Update Limitation Count\nThe field defines that how many times of HIRC trim value is updated by auto trim circuit before the HIRC frequency locked..\nOnce the HIRC locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and TRIM_SEL will be cleared to 00.\n
6
2
read-write
0
Trim retry count limitation is 64
#00
1
Trim retry count limitation is 128
#01
2
Trim retry count limitation is 256
#10
3
Trim retry count limitation is 512
#11
TRIM_SEL
Trim Frequency Selection\nThis field indicates the target frequency of internal 22.1184 MHz high speed oscillator will trim to precise 22.1184MHz or 24MHz automatically.\nIf no any target frequency is selected (TRIM_SEL is 00), the HIRC auto trim function is disabled.\nDuring auto trim operation, if clock error detected because of CLKERR_STOP_EN is set to 1 or trim retry limitation counts reached, this field will be cleared to 00 automatically.\n
0
2
read-write
0
HIRC auto trim function Disabled
#00
1
HIRC auto trim function Enabled and HIRC trimmed to 22.1184 MHz
#01
2
HIRC auto trim function Enabled and HIRC trimmed to 24 MHz
#10
3
Reserved
#11
IRCTRIMIEN
IRCTRIMIEN
IRC Trim Interrupt Enable Register
0x84
read-write
n
0x0
0x0
CLKERR_IEN
Clock Error Interrupt Enable\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERR_INT is set during auto trim operation. An interrupt will be triggered to notify the clock frequency is inaccuracy.\n
2
1
read-write
0
CLKERR_INT status to trigger an interrupt to CPU Disabled
#0
1
CLKERR_INT status to trigger an interrupt to CPU Enabled
#1
TRIM_FAIL_IEN
Trim Failure Interrupt Enable\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by TRIM_SEL.\nIf this bit is high and TRIM_FAIL_INT is set during auto trim operation. An interrupt will be triggered to notify that HIRC trim value update limitation count was reached.\n
1
1
read-write
0
TRIM_FAIL_INT status to trigger an interrupt to CPU Disabled
#0
1
TRIM_FAIL_INT status to trigger an interrupt to CPU Enabled
#1
IRCTRIMINT
IRCTRIMINT
IRC Trim Interrupt Status Register
0x88
read-write
n
0x0
0x0
CLKERR_INT
Clock Error Interrupt Status\nWhen the frequency of external 32.768 kHz low speed crystal or internal 22.1184 MHz high speed oscillator is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and TRIM_SEL will be cleared to 00 by hardware automatically if CLKERR_STOP_EN is set to 1.\nIf this bit is set and CLKERR_IEN is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.\n
2
1
read-write
0
Clock frequency is accurate
#0
1
Clock frequency is inaccurate
#1
FREQ_LOCK
HIRC Frequency Lock Status\nThis bit indicates the internal 22.1184 MHz high speed oscillator frequency is locked.\nThis is a status bit and doesn't trigger any interrupt.
0
1
read-write
TRIM_FAIL_INT
Trim Failure Interrupt Status\nThis bit indicates that internal 22.1184 MHz high speed oscillator trim value update limitation count reached and the internal 22.1184 MHz high speed oscillator clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and TRIM_SEL will be cleared to 00 by hardware automatically.\nIf this bit is set and TRIM_FAIL_IEN is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0.\n
1
1
read-write
0
Trim value update limitation count did not reach
#0
1
Trim value update limitation count reached and internal 22.1184 MHz high speed oscillator frequency was still not locked
#1
PDID
PDID
Part Device Identification Number Register
0x0
-1
read-only
n
0x0
0x0
PDID
Part Device Identification Number\nThis register reflects the device part number code. Software can read this register to identify which device is used.
0
32
read-only
PORCR
PORCR
Power-on Reset Controller Register
0x24
read-write
n
0x0
0x0
POR_DIS_CODE
Power-on-reset Enable Control (Write Protected)
When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function
This bit is the protected bit which means programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
0
16
read-write
REGWRPROT
REGWRPROT
Register Write Protection Register
0x100
read-write
n
0x0
0x0
REGWRPROT
Register Write-protection Code (Write Only)
Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 59h , 16h , 88h to this field. After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protection registers can be normal write.
Register Write-protection Disable Index (Read Only)
The Protected registers are:
IPRSTC1: address 0x5000_0008
BODCR: address 0x5000_0018
PORCR: address 0x5000_0024
PWRCON: address 0x5000_0200 (bit[6] is not protected for power wake-up interrupt clear)
APBCLK bit[0]: address 0x5000_0208 (bit[0] is watchdog clock enable)
CLKSEL0: address 0x5000_0210 (for HCLK and CPU STCLK clock source selection)
CLKSEL1 bit[1:0]: address 0x5000_0214 (for watchdog clock source selection)
NMI_SEL bit[8]: address 0x5000_0380 (for NMI_EN interrupt enable)
ISPCON: address 0x5000_C000 (Flash ISP Control register)
ISPTRG: address 0x5000_C010 (ISP Trigger Control register)
WTCR: address 0x4000_4000
FATCON: address 0x5000_C018
0
8
read-write
0
Write-protection is enabled for writing protected registers. Any write to the protected register is ignored
0
1
Write-protection is disabled for writing protected registers
1
RSTSRC
RSTSRC
System Reset Source Register
0x4
read-write
n
0x0
0x0
RSTS_BOD
The RSTS_BOD Flag Is Set by the Reset Signal From the Brown-out Detector to Indicate the Previous Reset Source
Write 1 to clear this bit to 0.
4
1
read-write
0
No reset from BOD
#0
1
BOD had issued the reset signal to reset the system
#1
RSTS_CPU
The RSTS_CPU Flag Is Set by Hardware If Software Writes CPU_RST (IPRSTC1[1]) 1 to Reset Cortex-M0 CPU Kernel and Flash Memory Controller (FMC)\nWrite 1 to clear this bit to 0.
7
1
read-write
0
No reset from CPU
#0
1
Cortex-M0 CPU kernel and FMC are reset by software setting CPU_RST to 1
#1
RSTS_LVR
The RSTS_LVR Flag Is Set by the Reset Signal From the Low-voltage-reset Controller to Indicate the Previous Reset Source
Write 1 to clear this bit to 0.
3
1
read-write
0
No reset from LVR
#0
1
The LVR controller had issued the reset signal to reset the system
#1
RSTS_POR
The RSTS_POR Flag Is Set by the Reset Signal From the Power-on Reset (POR) Controller or Bit CHIP_RST (IPRSTC1[0]) to Indicate the Previous Reset Source
Write 1 to clear this bit to 0.
0
1
read-write
0
No reset from POR or CHIP_RST
#0
1
Power-On Reset (POR) or CHIP_RST had issued the reset signal to reset the system
#1
RSTS_RESET
The RSTS_RESET Flag Is Set by the Reset Signal From the NRESET Pin to Indicate the Previous Reset Source
Write 1 to clear this bit to 0.
1
1
read-write
0
No reset from the nRESET pin
#0
1
The nRESET pin had issued the reset signal to reset the system
#1
RSTS_SYS
The RSTS_SYS Flag Is Set by the Reset Signal From the Cortex-M0 Kernel to Indicate the Previous Reset Source
Write 1 to clear this bit to 0.
5
1
read-write
0
No reset from Cortex-M0
#0
1
The Cortex-M0 had issued the reset signal to reset the system by writing 1 to bit SYSRESETREQ (AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 kernel
#1
RSTS_WDT
The RSTS_WDT Flag Is Set by the Reset Signal From the Watchdog Timer to Indicate the Previous Reset Source
Write 1 to clear this bit to 0.
2
1
read-write
0
No reset from watchdog timer
#0
1
The watchdog timer had issued the reset signal to reset the system
#1
TEMPCR
TEMPCR
Temperature Sensor Control Register
0x1C
read-write
n
0x0
0x0
VTEMP_EN
Temperature Sensor Enable\nThis bit is used to enable/disable temperature sensor function.\nAfter this bit is set to 1, the value of temperature can be obtained from ADC conversion result by ADC channel selecting channel 7 and alternative multiplexer channel selecting temperature sensor. Please refer to the ADC function chapter for detail ADC conversion functional description.
0
1
read-write
0
Temperature sensor function Disabled (default)
#0
1
Temperature sensor function Enabled
#1
GPIO
GPIO Register Map
GPIO
0x0
0x0
0x24
registers
n
0x100
0x24
registers
n
0x140
0x24
registers
n
0x180
0x4
registers
n
0x200
0x150
registers
n
0x40
0x24
registers
n
0x80
0x24
registers
n
0xC0
0x24
registers
n
DBNCECON
DBNCECON
External Interrupt De-bounce Control
0x180
-1
read-write
n
0x0
0x0
DBCLKSEL
De-bounce Sampling Cycle Selection\n
0
4
read-write
DBCLKSRC
De-bounce Counter Clock Source Selection\n
4
1
read-write
0
De-bounce counter clock source is the HCLK
#0
1
De-bounce counter clock source is the internal 10 kHz low speed oscillator
#1
ICLK_ON
Interrupt Clock On Mode\nIt is recommended to turn off this bit to save system power if no special application concern.
5
1
read-write
0
Edge detection circuit is active only if I/O pin corresponding GPIOx_IEN bit is set to 1
#0
1
All I/O pins edge detection circuit is always active after reset
#1
GPIOA_DBEN
GPIOA_DBEN
GPIO Port A De-bounce Enable
0x14
read-write
n
0x0
0x0
DBEN0
Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
0
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN1
Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
1
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN10
Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
10
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN11
Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
11
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN12
Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
12
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN13
Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
13
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN14
Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
14
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN15
Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
15
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN2
Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
2
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN3
Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
3
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN4
Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
4
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN5
Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
5
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN6
Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
6
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN7
Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
7
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN8
Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
8
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
DBEN9
Port [A/B/C/D/E/F] Input Signal De-bounce Enable\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]\n
9
1
read-write
0
Bit[n] de-bounce function Disabled
#0
1
Bit[n] de-bounce function Enabled
#1
GPIOA_DMASK
GPIOA_DMASK
GPIO Port A Data Output Write Mask
0xC
read-write
n
0x0
0x0
DMASK0
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
0
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK1
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
1
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK10
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
10
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK11
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
11
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK12
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
12
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK13
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
13
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK14
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
14
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK15
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
15
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK2
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
2
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK3
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
3
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK4
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
4
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK5
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
5
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK6
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
6
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK7
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
7
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK8
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
8
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
DMASK9
Port [A/B/C/D/E/F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When the DMASK bit[n] is set to 1, the corresponding GPIOx_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored\n
9
1
read-write
0
Corresponding GPIOx_DOUT[n] bit can be updated
#0
1
Corresponding GPIOx_DOUT[n] bit protected
#1
GPIOA_DOUT
GPIOA_DOUT
GPIO Port A Data Output Value
0x8
-1
read-write
n
0x0
0x0
DOUT0
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
0
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT1
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
1
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT10
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
10
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT11
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
11
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT12
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
12
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT13
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
13
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT14
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
14
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT15
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
15
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT2
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
2
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT3
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
3
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT4
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
4
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT5
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
5
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT6
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
6
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT7
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
7
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT8
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
8
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT9
GPIOx Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO pin is configured as Push-pull output, open-drain output or Quasi-bidirectional mode.\n
9
1
read-write
0
GPIO port [A/B/C/D/E/F] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [A/B/C/D/E/F] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
GPIOA_IEN
GPIOA_IEN
GPIO Port A Interrupt Enable
0x1C
read-write
n
0x0
0x0
IF_EN0
Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
0
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN1
Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
1
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN10
Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
10
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN11
Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
11
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN12
Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
12
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN13
Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
13
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN14
Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
14
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN15
Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
15
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN2
Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
2
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN3
Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
3
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN4
Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
4
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN5
Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
5
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN6
Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
6
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN7
Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
7
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN8
Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
8
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IF_EN9
Port [A/B/C/D/E/F] Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
9
1
read-write
0
PIN[n] state low-level or high-to-low change interrupt Disabled
#0
1
PIN[n] state low-level or high-to-low change interrupt Enabled
#1
IR_EN0
Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
16
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN1
Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
17
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN10
Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
26
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN11
Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
27
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN12
Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
28
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN13
Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
29
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN14
Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
30
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN15
Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
31
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN2
Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
18
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN3
Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
19
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN4
Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
20
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN5
Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
21
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN6
Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
22
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN7
Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
23
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN8
Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
24
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
IR_EN9
Port [A/B/C/D/E/F] Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
25
1
read-write
0
PIN[n] level-high or low-to-high interrupt Disabled
#0
1
PIN[n] level-high or low-to-high interrupt Enabled
#1
GPIOA_IMD
GPIOA_IMD
GPIO Port A Interrupt Mode Control
0x18
read-write
n
0x0
0x0
IMD0
Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
0
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD1
Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
1
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD10
Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
10
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD11
Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
11
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD12
Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
12
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD13
Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
13
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD14
Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
14
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD15
Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
15
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD2
Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
2
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD3
Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
3
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD4
Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
4
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD5
Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
5
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD6
Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
6
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD7
Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
7
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD8
Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
8
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
IMD9
Port [A/B/C/D/E/F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
9
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
GPIOA_ISRC
GPIOA_ISRC
GPIO Port A Interrupt Source Flag
0x20
read-write
n
0x0
0x0
ISRC0
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
0
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC1
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
1
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC10
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
10
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC11
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
11
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC12
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
12
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC13
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
13
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC14
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
14
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC15
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
15
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC2
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
2
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC3
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
3
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC4
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
4
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC5
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
5
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC6
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
6
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC7
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
7
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC8
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
8
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
ISRC9
Port [A/B/C/D/E/F] Interrupt Source Flag\nRead :\n
9
1
read-write
0
No interrupt at GPIOx[n].\nNo action
#0
1
GPIOx[n] generates an interrupt.\nClear the corresponding pending interrupt
#1
GPIOA_OFFD
GPIOA_OFFD
GPIO Port A Pin Digital Input Path Disable Control
0x4
read-write
n
0x0
0x0
OFFD
GPIOx Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal, users can disable GPIO digital input path to avoid creepage\n
16
16
read-write
0
I/O digital input path Enabled
0
1
I/O digital input path Disabled (digital input tied to low)
1
GPIOA_PIN
GPIOA_PIN
GPIO Port A Pin Value
0x10
read-only
n
0x0
0x0
PIN0
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
0
1
read-only
PIN1
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
1
1
read-only
PIN10
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
10
1
read-only
PIN11
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
11
1
read-only
PIN12
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
12
1
read-only
PIN13
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
13
1
read-only
PIN14
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
14
1
read-only
PIN15
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
15
1
read-only
PIN2
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
2
1
read-only
PIN3
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
3
1
read-only
PIN4
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
4
1
read-only
PIN5
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
5
1
read-only
PIN6
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
6
1
read-only
PIN7
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
7
1
read-only
PIN8
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
8
1
read-only
PIN9
Port [A/B/C/D/E/F] Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low\n
9
1
read-only
GPIOA_PMD
GPIOA_PMD
GPIO Port A Pin I/O Mode Control
0x0
read-write
n
0x0
0x0
PMD0
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
0
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD1
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
2
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD10
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
20
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD11
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
22
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD12
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
24
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD13
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
26
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD14
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
28
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD15
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
30
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD2
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
4
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD3
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
6
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD4
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
8
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD5
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
10
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD6
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
12
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD7
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
14
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD8
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
16
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD9
GPIOx I/O Pin[N] Mode Control\nDetermine each I/O mode of GPIOx pins.\nThe initial value of this field is defined by CIOINI (CONFIG0[10]). If CIOINI is set to 1, the default value is 0xFFFF_FFFF and all pins will be Auasi-bidirectional mode after chip is powered on. If CIOINI is cleared to 0, the default value is 0x0000_0000 and all pins will be input only mode after chip is powered on.
18
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
GPIOB_DBEN
GPIOB_DBEN
GPIO Port B De-bounce Enable
0x54
read-write
n
0x0
0x0
GPIOB_DMASK
GPIOB_DMASK
GPIO Port B Data Output Write Mask
0x4C
read-write
n
0x0
0x0
GPIOB_DOUT
GPIOB_DOUT
GPIO Port B Data Output Value
0x48
read-write
n
0x0
0x0
GPIOB_IEN
GPIOB_IEN
GPIO Port B Interrupt Enable
0x5C
read-write
n
0x0
0x0
GPIOB_IMD
GPIOB_IMD
GPIO Port B Interrupt Mode Control
0x58
read-write
n
0x0
0x0
GPIOB_ISRC
GPIOB_ISRC
GPIO Port B Interrupt Source Flag
0x60
read-write
n
0x0
0x0
GPIOB_OFFD
GPIOB_OFFD
GPIO Port B Pin Digital Input Path Disable Control
0x44
read-write
n
0x0
0x0
GPIOB_PIN
GPIOB_PIN
GPIO Port B Pin Value
0x50
read-write
n
0x0
0x0
GPIOB_PMD
GPIOB_PMD
GPIO Port B Pin I/O Mode Control
0x40
read-write
n
0x0
0x0
GPIOC_DBEN
GPIOC_DBEN
GPIO Port C De-bounce Enable
0x94
read-write
n
0x0
0x0
GPIOC_DMASK
GPIOC_DMASK
GPIO Port C Data Output Write Mask
0x8C
read-write
n
0x0
0x0
GPIOC_DOUT
GPIOC_DOUT
GPIO Port C Data Output Value
0x88
read-write
n
0x0
0x0
GPIOC_IEN
GPIOC_IEN
GPIO Port C Interrupt Enable
0x9C
read-write
n
0x0
0x0
GPIOC_IMD
GPIOC_IMD
GPIO Port C Interrupt Mode Control
0x98
read-write
n
0x0
0x0
GPIOC_ISRC
GPIOC_ISRC
GPIO Port C Interrupt Source Flag
0xA0
read-write
n
0x0
0x0
GPIOC_OFFD
GPIOC_OFFD
GPIO Port C Pin Digital Input Path Disable Control
0x84
read-write
n
0x0
0x0
GPIOC_PIN
GPIOC_PIN
GPIO Port C Pin Value
0x90
read-write
n
0x0
0x0
GPIOC_PMD
GPIOC_PMD
GPIO Port C Pin I/O Mode Control
0x80
read-write
n
0x0
0x0
GPIOD_DBEN
GPIOD_DBEN
GPIO Port D De-bounce Enable
0xD4
read-write
n
0x0
0x0
GPIOD_DMASK
GPIOD_DMASK
GPIO Port D Data Output Write Mask
0xCC
read-write
n
0x0
0x0
GPIOD_DOUT
GPIOD_DOUT
GPIO Port D Data Output Value
0xC8
read-write
n
0x0
0x0
GPIOD_IEN
GPIOD_IEN
GPIO Port D Interrupt Enable
0xDC
read-write
n
0x0
0x0
GPIOD_IMD
GPIOD_IMD
GPIO Port D Interrupt Mode Control
0xD8
read-write
n
0x0
0x0
GPIOD_ISRC
GPIOD_ISRC
GPIO Port D Interrupt Source Flag
0xE0
read-write
n
0x0
0x0
GPIOD_OFFD
GPIOD_OFFD
GPIO Port D Pin Digital Input Path Disable Control
0xC4
read-write
n
0x0
0x0
GPIOD_PIN
GPIOD_PIN
GPIO Port D Pin Value
0xD0
read-write
n
0x0
0x0
GPIOD_PMD
GPIOD_PMD
GPIO Port D Pin I/O Mode Control
0xC0
read-write
n
0x0
0x0
GPIOE_DBEN
GPIOE_DBEN
GPIO Port E De-bounce Enable
0x114
read-write
n
0x0
0x0
GPIOE_DMASK
GPIOE_DMASK
GPIO Port E Data Output Write Mask
0x10C
read-write
n
0x0
0x0
GPIOE_DOUT
GPIOE_DOUT
GPIO Port E Data Output Value
0x108
read-write
n
0x0
0x0
GPIOE_IEN
GPIOE_IEN
GPIO Port E Interrupt Enable
0x11C
read-write
n
0x0
0x0
GPIOE_IMD
GPIOE_IMD
GPIO Port E Interrupt Mode Control
0x118
read-write
n
0x0
0x0
GPIOE_ISRC
GPIOE_ISRC
GPIO Port E Interrupt Source Flag
0x120
read-write
n
0x0
0x0
GPIOE_OFFD
GPIOE_OFFD
GPIO Port E Pin Digital Input Path Disable Control
0x104
read-write
n
0x0
0x0
GPIOE_PIN
GPIOE_PIN
GPIO Port E Pin Value
0x110
read-write
n
0x0
0x0
GPIOE_PMD
GPIOE_PMD
GPIO Port E Pin I/O Mode Control
0x100
read-write
n
0x0
0x0
GPIOF_DBEN
GPIOF_DBEN
GPIO Port F De-bounce Enable
0x154
read-write
n
0x0
0x0
GPIOF_DMASK
GPIOF_DMASK
GPIO Port F Data Output Write Mask
0x14C
read-write
n
0x0
0x0
GPIOF_DOUT
GPIOF_DOUT
GPIO Port F Data Output Value
0x148
read-write
n
0x0
0x0
GPIOF_IEN
GPIOF_IEN
GPIO Port F Interrupt Enable
0x15C
read-write
n
0x0
0x0
GPIOF_IMD
GPIOF_IMD
GPIO Port F Interrupt Mode Control
0x158
read-write
n
0x0
0x0
GPIOF_ISRC
GPIOF_ISRC
GPIO Port F Interrupt Source Flag
0x160
read-write
n
0x0
0x0
GPIOF_OFFD
GPIOF_OFFD
GPIO Port F Pin Digital Input Path Disable Control
0x144
read-write
n
0x0
0x0
GPIOF_PIN
GPIOF_PIN
GPIO Port F Pin Value
0x150
read-write
n
0x0
0x0
GPIOF_PMD
GPIOF_PMD
GPIO Port F Pin I/O Mode Control
0x140
read-write
n
0x0
0x0
PA0_PDIO
PA0_PDIO
GPIO PA.n Pin Data Input/Output
0x200
read-write
n
0x0
0x0
Pxn_PDIO
GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: writing PA0_PDIO will reflect the written value to bit GPIOA_DOUT[0], read PA0_PDIO will return the value of GPIOA_PIN[0]\nNote: The write operation will not be affected by register GPIOx_DMASK
0
1
read-write
0
Corresponding GPIO pin set to low
#0
1
Corresponding GPIO pin set to high
#1
PA10_PDIO
PA10_PDIO
GPIO PA.n Pin Data Input/Output
0x228
read-write
n
0x0
0x0
PA11_PDIO
PA11_PDIO
GPIO PA.n Pin Data Input/Output
0x22C
read-write
n
0x0
0x0
PA12_PDIO
PA12_PDIO
GPIO PA.n Pin Data Input/Output
0x230
read-write
n
0x0
0x0
PA13_PDIO
PA13_PDIO
GPIO PA.n Pin Data Input/Output
0x234
read-write
n
0x0
0x0
PA14_PDIO
PA14_PDIO
GPIO PA.n Pin Data Input/Output
0x238
read-write
n
0x0
0x0
PA15_PDIO
PA15_PDIO
GPIO PA.n Pin Data Input/Output
0x23C
read-write
n
0x0
0x0
PA1_PDIO
PA1_PDIO
GPIO PA.n Pin Data Input/Output
0x204
read-write
n
0x0
0x0
PA2_PDIO
PA2_PDIO
GPIO PA.n Pin Data Input/Output
0x208
read-write
n
0x0
0x0
PA3_PDIO
PA3_PDIO
GPIO PA.n Pin Data Input/Output
0x20C
read-write
n
0x0
0x0
PA4_PDIO
PA4_PDIO
GPIO PA.n Pin Data Input/Output
0x210
read-write
n
0x0
0x0
PA5_PDIO
PA5_PDIO
GPIO PA.n Pin Data Input/Output
0x214
read-write
n
0x0
0x0
PA6_PDIO
PA6_PDIO
GPIO PA.n Pin Data Input/Output
0x218
read-write
n
0x0
0x0
PA7_PDIO
PA7_PDIO
GPIO PA.n Pin Data Input/Output
0x21C
read-write
n
0x0
0x0
PA8_PDIO
PA8_PDIO
GPIO PA.n Pin Data Input/Output
0x220
read-write
n
0x0
0x0
PA9_PDIO
PA9_PDIO
GPIO PA.n Pin Data Input/Output
0x224
read-write
n
0x0
0x0
PB0_PDIO
PB0_PDIO
GPIO PB.n Pin Data Input/Output
0x240
read-write
n
0x0
0x0
PB10_PDIO
PB10_PDIO
GPIO PB.n Pin Data Input/Output
0x268
read-write
n
0x0
0x0
PB11_PDIO
PB11_PDIO
GPIO PB.n Pin Data Input/Output
0x26C
read-write
n
0x0
0x0
PB12_PDIO
PB12_PDIO
GPIO PB.n Pin Data Input/Output
0x270
read-write
n
0x0
0x0
PB13_PDIO
PB13_PDIO
GPIO PB.n Pin Data Input/Output
0x274
read-write
n
0x0
0x0
PB14_PDIO
PB14_PDIO
GPIO PB.n Pin Data Input/Output
0x278
read-write
n
0x0
0x0
PB15_PDIO
PB15_PDIO
GPIO PB.n Pin Data Input/Output
0x27C
read-write
n
0x0
0x0
PB1_PDIO
PB1_PDIO
GPIO PB.n Pin Data Input/Output
0x244
read-write
n
0x0
0x0
PB2_PDIO
PB2_PDIO
GPIO PB.n Pin Data Input/Output
0x248
read-write
n
0x0
0x0
PB3_PDIO
PB3_PDIO
GPIO PB.n Pin Data Input/Output
0x24C
read-write
n
0x0
0x0
PB4_PDIO
PB4_PDIO
GPIO PB.n Pin Data Input/Output
0x250
read-write
n
0x0
0x0
PB5_PDIO
PB5_PDIO
GPIO PB.n Pin Data Input/Output
0x254
read-write
n
0x0
0x0
PB6_PDIO
PB6_PDIO
GPIO PB.n Pin Data Input/Output
0x258
read-write
n
0x0
0x0
PB7_PDIO
PB7_PDIO
GPIO PB.n Pin Data Input/Output
0x25C
read-write
n
0x0
0x0
PB8_PDIO
PB8_PDIO
GPIO PB.n Pin Data Input/Output
0x260
read-write
n
0x0
0x0
PB9_PDIO
PB9_PDIO
GPIO PB.n Pin Data Input/Output
0x264
read-write
n
0x0
0x0
PC0_PDIO
PC0_PDIO
GPIO PC.n Pin Data Input/Output
0x280
read-write
n
0x0
0x0
PC10_PDIO
PC10_PDIO
GPIO PC.n Pin Data Input/Output
0x2A8
read-write
n
0x0
0x0
PC11_PDIO
PC11_PDIO
GPIO PC.n Pin Data Input/Output
0x2AC
read-write
n
0x0
0x0
PC12_PDIO
PC12_PDIO
GPIO PC.n Pin Data Input/Output
0x2B0
read-write
n
0x0
0x0
PC13_PDIO
PC13_PDIO
GPIO PC.n Pin Data Input/Output
0x2B4
read-write
n
0x0
0x0
PC14_PDIO
PC14_PDIO
GPIO PC.n Pin Data Input/Output
0x2B8
read-write
n
0x0
0x0
PC15_PDIO
PC15_PDIO
GPIO PC.n Pin Data Input/Output
0x2BC
read-write
n
0x0
0x0
PC1_PDIO
PC1_PDIO
GPIO PC.n Pin Data Input/Output
0x284
read-write
n
0x0
0x0
PC2_PDIO
PC2_PDIO
GPIO PC.n Pin Data Input/Output
0x288
read-write
n
0x0
0x0
PC3_PDIO
PC3_PDIO
GPIO PC.n Pin Data Input/Output
0x28C
read-write
n
0x0
0x0
PC4_PDIO
PC4_PDIO
GPIO PC.n Pin Data Input/Output
0x290
read-write
n
0x0
0x0
PC5_PDIO
PC5_PDIO
GPIO PC.n Pin Data Input/Output
0x294
read-write
n
0x0
0x0
PC6_PDIO
PC6_PDIO
GPIO PC.n Pin Data Input/Output
0x298
read-write
n
0x0
0x0
PC7_PDIO
PC7_PDIO
GPIO PC.n Pin Data Input/Output
0x29C
read-write
n
0x0
0x0
PC8_PDIO
PC8_PDIO
GPIO PC.n Pin Data Input/Output
0x2A0
read-write
n
0x0
0x0
PC9_PDIO
PC9_PDIO
GPIO PC.n Pin Data Input/Output
0x2A4
read-write
n
0x0
0x0
PD0_PDIO
PD0_PDIO
GPIO PD.n Pin Data Input/Output
0x2C0
read-write
n
0x0
0x0
PD10_PDIO
PD10_PDIO
GPIO PD.n Pin Data Input/Output
0x2E8
read-write
n
0x0
0x0
PD11_PDIO
PD11_PDIO
GPIO PD.n Pin Data Input/Output
0x2EC
read-write
n
0x0
0x0
PD12_PDIO
PD12_PDIO
GPIO PD.n Pin Data Input/Output
0x2F0
read-write
n
0x0
0x0
PD13_PDIO
PD13_PDIO
GPIO PD.n Pin Data Input/Output
0x2F4
read-write
n
0x0
0x0
PD14_PDIO
PD14_PDIO
GPIO PD.n Pin Data Input/Output
0x2F8
read-write
n
0x0
0x0
PD15_PDIO
PD15_PDIO
GPIO PD.n Pin Data Input/Output
0x2FC
read-write
n
0x0
0x0
PD1_PDIO
PD1_PDIO
GPIO PD.n Pin Data Input/Output
0x2C4
read-write
n
0x0
0x0
PD2_PDIO
PD2_PDIO
GPIO PD.n Pin Data Input/Output
0x2C8
read-write
n
0x0
0x0
PD3_PDIO
PD3_PDIO
GPIO PD.n Pin Data Input/Output
0x2CC
read-write
n
0x0
0x0
PD4_PDIO
PD4_PDIO
GPIO PD.n Pin Data Input/Output
0x2D0
read-write
n
0x0
0x0
PD5_PDIO
PD5_PDIO
GPIO PD.n Pin Data Input/Output
0x2D4
read-write
n
0x0
0x0
PD6_PDIO
PD6_PDIO
GPIO PD.n Pin Data Input/Output
0x2D8
read-write
n
0x0
0x0
PD7_PDIO
PD7_PDIO
GPIO PD.n Pin Data Input/Output
0x2DC
read-write
n
0x0
0x0
PD8_PDIO
PD8_PDIO
GPIO PD.n Pin Data Input/Output
0x2E0
read-write
n
0x0
0x0
PD9_PDIO
PD9_PDIO
GPIO PD.n Pin Data Input/Output
0x2E4
read-write
n
0x0
0x0
PE0_PDIO
PE0_PDIO
GPIO PE.n Pin Data Input/Output
0x300
read-write
n
0x0
0x0
PE10_PDIO
PE10_PDIO
GPIO PE.n Pin Data Input/Output
0x328
read-write
n
0x0
0x0
PE11_PDIO
PE11_PDIO
GPIO PE.n Pin Data Input/Output
0x32C
read-write
n
0x0
0x0
PE12_PDIO
PE12_PDIO
GPIO PE.n Pin Data Input/Output
0x330
read-write
n
0x0
0x0
PE13_PDIO
PE13_PDIO
GPIO PE.n Pin Data Input/Output
0x334
read-write
n
0x0
0x0
PE14_PDIO
PE14_PDIO
GPIO PE.n Pin Data Input/Output
0x338
read-write
n
0x0
0x0
PE15_PDIO
PE15_PDIO
GPIO PE.n Pin Data Input/Output
0x33C
read-write
n
0x0
0x0
PE1_PDIO
PE1_PDIO
GPIO PE.n Pin Data Input/Output
0x304
read-write
n
0x0
0x0
PE2_PDIO
PE2_PDIO
GPIO PE.n Pin Data Input/Output
0x308
read-write
n
0x0
0x0
PE3_PDIO
PE3_PDIO
GPIO PE.n Pin Data Input/Output
0x30C
read-write
n
0x0
0x0
PE4_PDIO
PE4_PDIO
GPIO PE.n Pin Data Input/Output
0x310
read-write
n
0x0
0x0
PE5_PDIO
PE5_PDIO
GPIO PE.n Pin Data Input/Output
0x314
read-write
n
0x0
0x0
PE6_PDIO
PE6_PDIO
GPIO PE.n Pin Data Input/Output
0x318
read-write
n
0x0
0x0
PE7_PDIO
PE7_PDIO
GPIO PE.n Pin Data Input/Output
0x31C
read-write
n
0x0
0x0
PE8_PDIO
PE8_PDIO
GPIO PE.n Pin Data Input/Output
0x320
read-write
n
0x0
0x0
PE9_PDIO
PE9_PDIO
GPIO PE.n Pin Data Input/Output
0x324
read-write
n
0x0
0x0
PF0_PDIO
PF0_PDIO
GPIO PF.n Pin Data Input/Output
0x340
read-write
n
0x0
0x0
PF1_PDIO
PF1_PDIO
GPIO PF.n Pin Data Input/Output
0x344
read-write
n
0x0
0x0
PF2_PDIO
PF2_PDIO
GPIO PF.n Pin Data Input/Output
0x348
read-write
n
0x0
0x0
PF3_PDIO
PF3_PDIO
GPIO PF.n Pin Data Input/Output
0x34C
read-write
n
0x0
0x0
I2C0
I2C Register Map
I2C
0x0
0x0
0x30
registers
n
0x3C
0x8
registers
n
I2CADDR0
I2CADDR0
I2C Slave Address Register0
0x4
read-write
n
0x0
0x0
GC
General Call Function\n
0
1
read-write
0
General Call function Disabled
#0
1
General Call function Enabled
#1
I2CADDR
I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if one of the addresses is matched.
1
7
read-write
I2CADDR1
I2CADDR1
I2C Slave Address Register1
0x18
read-write
n
0x0
0x0
I2CADDR2
I2CADDR2
I2C Slave Address Register2
0x1C
read-write
n
0x0
0x0
I2CADDR3
I2CADDR3
I2C Slave Address Register3
0x20
read-write
n
0x0
0x0
I2CADM0
I2CADM0
I2C Slave Address Mask Register0
0x24
read-write
n
0x0
0x0
I2CADM
I2C Address Mask Register\nI2C bus controller supports multiple address recognition with four address mask registers. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to 0, that means the received corresponding register bit should be exactly the same as address register.
1
7
read-write
0
Mask Disabled (the received corresponding register bit should be exactly the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
I2CADM1
I2CADM1
I2C Slave Address Mask Register1
0x28
read-write
n
0x0
0x0
I2CADM2
I2CADM2
I2C Slave Address Mask Register2
0x2C
read-write
n
0x0
0x0
I2CADM3
I2CADM3
I2C Slave Address Mask Register3
0x30
read-write
n
0x0
0x0
I2CDAT
I2CDAT
I2C Data Register
0x8
read-write
n
0x0
0x0
I2CDAT
I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of I2C serial port.
0
8
read-write
I2CLK
I2CLK
I2C Clock Divided Register
0x10
read-write
n
0x0
0x0
I2CLK
I2C Clock Divided Register\nNote: The minimum value of I2CLK is 4.
0
8
read-write
I2CON
I2CON
I2C Control Register
0x0
read-write
n
0x0
0x0
AA
Assert Acknowledge Control Bit\n
2
1
read-write
EI
Enable Interrupt\n
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
ENS1
I2C Controller Enable Bit\n
6
1
read-write
0
Disabled
#0
1
Enabled
#1
SI
I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing 1 to this bit.
3
1
read-write
STA
I2C START Control Bit\nSet STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control Bit
In Master mode, set STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode, setting STO resets I2C hardware to the defined not addressed Slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
4
1
read-write
I2CSTATUS
I2CSTATUS
I2C Status Register
0xC
-1
read-only
n
0x0
0x0
I2CSTATUS
I2C Status Register\nThe status register of I2C:\n
0
8
read-only
I2CTOC
I2CTOC
I2C Time-out Counter Register
0x14
read-write
n
0x0
0x0
DIV4
Time-out Counter Input Clock Is Divided by 4\nWhen Enabled, the time-out period is extended 4 times.
1
1
read-write
0
The time-out counter input clock divided by 4 Disabled
#0
1
The time-out counter input clock divided by 4 Enabled
#1
ENTI
Time-out Counter Enable\nWhen Enabled, the 14-bit time-out counter will start counting when SI is cleared. Writing 1 to the SI flag will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TIF
Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (EI) is set to 1.\nSoftware can write 1 to clear this bit.
0
1
read-write
I2CWKUPCON
I2CWKUPCON
I2C Wake-up Control Register
0x3C
read-write
n
0x0
0x0
WKUPEN
I2C Wake-up Function Enable\n
0
1
read-write
0
I2C wake-up function Disabled
#0
1
I2C wake-up function Enabled
#1
I2CWKUPSTS
I2CWKUPSTS
I2C Wake-up Status Register
0x40
read-write
n
0x0
0x0
WKUPIF
I2C Wake-up Interrupt Flag\nWhen chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
I2C1
I2C Register Map
I2C
0x0
0x0
0x30
registers
n
0x3C
0x8
registers
n
I2CADDR0
I2CADDR0
I2C Slave Address Register0
0x4
read-write
n
0x0
0x0
GC
General Call Function\n
0
1
read-write
0
General Call function Disabled
#0
1
General Call function Enabled
#1
I2CADDR
I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if one of the addresses is matched.
1
7
read-write
I2CADDR1
I2CADDR1
I2C Slave Address Register1
0x18
read-write
n
0x0
0x0
I2CADDR2
I2CADDR2
I2C Slave Address Register2
0x1C
read-write
n
0x0
0x0
I2CADDR3
I2CADDR3
I2C Slave Address Register3
0x20
read-write
n
0x0
0x0
I2CADM0
I2CADM0
I2C Slave Address Mask Register0
0x24
read-write
n
0x0
0x0
I2CADM
I2C Address Mask Register\nI2C bus controller supports multiple address recognition with four address mask registers. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to 0, that means the received corresponding register bit should be exactly the same as address register.
1
7
read-write
0
Mask Disabled (the received corresponding register bit should be exactly the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
I2CADM1
I2CADM1
I2C Slave Address Mask Register1
0x28
read-write
n
0x0
0x0
I2CADM2
I2CADM2
I2C Slave Address Mask Register2
0x2C
read-write
n
0x0
0x0
I2CADM3
I2CADM3
I2C Slave Address Mask Register3
0x30
read-write
n
0x0
0x0
I2CDAT
I2CDAT
I2C Data Register
0x8
read-write
n
0x0
0x0
I2CDAT
I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of I2C serial port.
0
8
read-write
I2CLK
I2CLK
I2C Clock Divided Register
0x10
read-write
n
0x0
0x0
I2CLK
I2C Clock Divided Register\nNote: The minimum value of I2CLK is 4.
0
8
read-write
I2CON
I2CON
I2C Control Register
0x0
read-write
n
0x0
0x0
AA
Assert Acknowledge Control Bit\n
2
1
read-write
EI
Enable Interrupt\n
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
ENS1
I2C Controller Enable Bit\n
6
1
read-write
0
Disabled
#0
1
Enabled
#1
SI
I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing 1 to this bit.
3
1
read-write
STA
I2C START Control Bit\nSet STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control Bit
In Master mode, set STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode, setting STO resets I2C hardware to the defined not addressed Slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
4
1
read-write
I2CSTATUS
I2CSTATUS
I2C Status Register
0xC
-1
read-only
n
0x0
0x0
I2CSTATUS
I2C Status Register\nThe status register of I2C:\n
0
8
read-only
I2CTOC
I2CTOC
I2C Time-out Counter Register
0x14
read-write
n
0x0
0x0
DIV4
Time-out Counter Input Clock Is Divided by 4\nWhen Enabled, the time-out period is extended 4 times.
1
1
read-write
0
The time-out counter input clock divided by 4 Disabled
#0
1
The time-out counter input clock divided by 4 Enabled
#1
ENTI
Time-out Counter Enable\nWhen Enabled, the 14-bit time-out counter will start counting when SI is cleared. Writing 1 to the SI flag will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TIF
Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (EI) is set to 1.\nSoftware can write 1 to clear this bit.
0
1
read-write
I2CWKUPCON
I2CWKUPCON
I2C Wake-up Control Register
0x3C
read-write
n
0x0
0x0
WKUPEN
I2C Wake-up Function Enable\n
0
1
read-write
0
I2C wake-up function Disabled
#0
1
I2C wake-up function Enabled
#1
I2CWKUPSTS
I2CWKUPSTS
I2C Wake-up Status Register
0x40
read-write
n
0x0
0x0
WKUPIF
I2C Wake-up Interrupt Flag\nWhen chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
I2S
I2S Register Map
I2S
0x0
0x0
0x18
registers
n
I2SCLKDIV
I2SCLKDIV
I2S Clock Divider Control Register
0x4
read-write
n
0x0
0x0
BCLK_DIV
Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode. The bit clock rate, F_BCLK, is determined by the following expression.\n
8
8
read-write
MCLK_DIV
Master Clock Divider\nIf MCLKEN is set to 1, I2S controller will generate master clock for external audio devices. The master clock rate, F_MCLK, is determined by the following expressions.\nF_I2SCLK is the frequency of I2S clock.\nIn general, the master clock rate is 256 times sampling clock rate.
0
3
read-write
I2SCON
I2SCON
I2S Control Register
0x0
read-write
n
0x0
0x0
CLR_RXFIFO
Clear Receive FIFO\nWrite 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXFIFO_LEVEL[3:0] returns 0 and receive FIFO becomes empty.\nThis bit is cleared by hardware automatically. Returns 0 on read.
19
1
read-write
CLR_TXFIFO
Clear Transmit FIFO\nWrite 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXFIFO_LEVEL[3:0] returns to 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed. \nThis bit is cleared by hardware automatically. Returns 0 on read.
18
1
read-write
FORMAT
Data Format\n
7
1
read-write
0
I2S data format
#0
1
MSB justified data format
#1
I2SEN
I2S Controller Enable \n
0
1
read-write
0
Disabled
#0
1
Enabled
#1
LCHZCEN
Left Channel Zero Cross Detect Enable\nIf this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCF flag in I2SSTATUS register is set to 1. This function is only available in transmit operation.\n
17
1
read-write
0
Left channel zero cross detect Disabled
#0
1
Left channel zero cross detect Enabled
#1
MCLKEN
Master Clock Enable\nIf MCLKEN is set to 1, I2S controller will generate master clock on I2SMCLK pin for external audio devices.\n
15
1
read-write
0
Master clock Disabled
#0
1
Master clock Enabled
#1
MONO
Monaural Data\n
6
1
read-write
0
Data is stereo format
#0
1
Data is monaural format
#1
MUTE
Transmit Mute Enable\n
3
1
read-write
0
Transmit data is shifted from buffer
#0
1
Transmit channel zero
#1
RCHZCEN
Right Channel Zero Cross Detect Enable\nIf this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCF flag in I2SSTATUS register is set to 1. This function is only available in transmit operation.\n
16
1
read-write
0
Right channel zero cross detect Disabled
#0
1
Right channel zero cross detect Enabled
#1
RXDMA
Enable Receive DMA\nWhen RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty.\n
21
1
read-write
0
RX DMA Disabled
#0
1
RX DMA Enabled
#1
RXEN
Receive Enable\n
2
1
read-write
0
Data receiving Disabled
#0
1
Data receiving Enabled
#1
RXLCH
Receive Left Channel Enable\n
23
1
read-write
0
Receive right channel data in Mono mode
#0
1
Receive left channel data in Mono mode
#1
RXTH
Receive FIFO Threshold Level\nWhen received data word(s) in buffer is equal to or higher than threshold level then RXTHF flag is set.\n
12
3
read-write
0
1 word data in receive FIFO
#000
1
2 word data in receive FIFO
#001
2
3 word data in receive FIFO
#010
3
4 word data in receive FIFO
#011
4
5 word data in receive FIFO
#100
5
6 word data in receive FIFO
#101
6
7 word data in receive FIFO
#110
7
8 word data in receive FIFO
#111
SLAVE
Slave Mode\nI2S can operate as master or slave. For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send bit clock from NuMicro( NUC200 series to Audio CODEC chip. In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip.\n
8
1
read-write
0
Master mode
#0
1
Slave mode
#1
TXDMA
Enable Transmit DMA\nWhen TX DMA is enables, I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full.\n
20
1
read-write
0
TX DMA Disabled
#0
1
TX DMA Enabled
#1
TXEN
Transmit Enable\n
1
1
read-write
0
Data transmit Disabled
#0
1
Data transmit Enabled
#1
TXTH
Transmit FIFO Threshold Level\nIf remaining data word (32 bits) in transmit FIFO is the same or less than threshold level then TXTHF flag is set.\n
9
3
read-write
0
0 word data in transmit FIFO
#000
1
1 word data in transmit FIFO
#001
2
2 words data in transmit FIFO
#010
3
3 words data in transmit FIFO
#011
4
4 words data in transmit FIFO
#100
5
5 words data in transmit FIFO
#101
6
6 words data in transmit FIFO
#110
7
7 words data in transmit FIFO
#111
WORDWIDTH
Word Width\n
4
2
read-write
0
data is 8-bit
#00
1
data is 16-bit
#01
2
data is 24-bit
#10
3
data is 32-bit
#11
I2SIE
I2SIE
I2S Interrupt Enable Register
0x8
read-write
n
0x0
0x0
LZCIE
Left Channel Zero-cross Interrupt Enable\nInterrupt occurs if this bit is set to 1 and left channel zero-cross.\n
12
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RXOVFIE
Receive FIFO Overflow Interrupt Enable\n
1
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RXTHIE
Receive FIFO Threshold Level Interrupt Enable\nWhen data word in receive FIFO is equal to or higher then RXTH[2:0] and the RXTHF bit is set to 1. If RXTHIE bit is enabled, interrupt occurs.\n
2
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RXUDFIE
Receive FIFO Underflow Interrupt Enable\nIf software read receive FIFO when it is empty then RXUDF flag in I2SSTATUS register is set to 1.\n
0
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RZCIE
Right Channel Zero-cross Interrupt Enable\nInterrupt occurs if this bit is set to 1 and right channel zero-cross.\n
11
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TXOVFIE
Transmit FIFO Overflow Interrupt Enable\nInterrupt occurs if this bit is set to 1 and the transmit FIFO overflow flag is set to 1\n
9
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TXTHIE
Transmit FIFO Threshold Level Interrupt Enable\nInterrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH[2:0].\n
10
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TXUDFIE
Transmit FIFO Underflow Interrupt Enable\nInterrupt occurs if this bit is set to 1 and the transmit FIFO underflow flag is set to 1.\n
8
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
I2SRXFIFO
I2SRXFIFO
I2S Receive FIFO Register
0x14
read-only
n
0x0
0x0
RXFIFO
Receive FIFO Register\nI2S contains 8 words (8x32 bits) data buffer for data receive. Read this register to get data in FIFO. The remaining data word number is indicated by RX_LEVEL[3:0] in I2SSTATUS register.
0
32
read-only
I2SSTATUS
I2SSTATUS
I2S Status Register
0xC
-1
read-write
n
0x0
0x0
I2SINT
I2S Interrupt Flag\nIt is wire-OR of I2STXINT and I2SRXINT bits.\nThis bit is read only.
0
1
read-write
0
No I2S interrupt
#0
1
I2S interrupt
#1
I2SRXINT
I2S Receive Interrupt\nThis bit is read only
1
1
read-write
0
No receive interrupt
#0
1
Receive interrupt
#1
I2STXINT
I2S Transmit Interrupt\nThis bit is read only
2
1
read-write
0
No transmit interrupt
#0
1
Transmit interrupt
#1
LZCF
Left Channel Zero-cross Flag\nIt indicates left channel next sample data sign bit is changed or all data bits are 0.\nWrite 1 to clear this bit to 0.
23
1
read-write
0
No zero-cross
#0
1
Left channel zero-cross is detected
#1
RIGHT
Right Channel\nThis bit indicates current transmit data is belong to right channel\nThis bit is read only
3
1
read-write
0
Left channel
#0
1
Right channel
#1
RXEMPTY
Receive FIFO Empty\nThis bit reflects data words number in receive FIFO is 0\nThis bit is read only.
12
1
read-write
0
Not empty
#0
1
Empty
#1
RXFULL
Receive FIFO Full\nThis bit reflects data words number in receive FIFO is 8\nThis bit is read only.
11
1
read-write
0
Not full
#0
1
Full
#1
RXOVF
Receive FIFO Overflow Flag\nWhen receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote.\nWrite 1 to clear this bit to 0.
9
1
read-write
0
No overflow
#0
1
Overflow
#1
RXTHF
Receive FIFO Threshold Flag\nWhen data word(s) in receive FIFO is equal to or higher than threshold value set in RXTH[2:0] the RXTHF bit becomes to 1. It keeps at 1 till RXFIFO_LEVEL[3:0] is less than RXTH[1:0] after software read RXFIFO register.\nThis bit is read only
10
1
read-write
0
Data word(s) in FIFO is lower than threshold level
#0
1
Data word(s) in FIFO is equal to or higher than threshold level
#1
RXUDF
Receive FIFO Underflow Flag\nRead receive FIFO when it is empty, this bit set to 1 indicate underflow occurs.\nWrite 1 to clear this bit to 0.
8
1
read-write
0
No underflow
#0
1
Underflow
#1
RX_LEVEL
Receive FIFO Level\nThese bits indicate word number in receive FIFO\n
24
4
read-write
0
No data
#0000
1
1 word in receive FIFO
#0001
8
8 words in receive FIFO
#1000
RZCF
Right Channel Zero-cross Flag\nIt indicates right channel next sample data sign bit is changed or all data bits are 0.\nWrite 1 to clear this bit to 0
22
1
read-write
0
No zero-cross
#0
1
Right channel zero-cross is detected
#1
TXBUSY
Transmit Busy\nThis bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out. And set to 1 when 1st data is load to shift buffer. \nThis bit is read only.
21
1
read-write
0
Transmit shift buffer is empty
#0
1
Transmit shift buffer is busy
#1
TXEMPTY
Transmit FIFO Empty\nThis bit reflects data word number in transmit FIFO is 0\nThis bit is read only.
20
1
read-write
0
Not empty
#0
1
Empty
#1
TXFULL
Transmit FIFO Full\nThis bit reflects data word number in transmit FIFO is 8\nThis bit is read only
19
1
read-write
0
Not full
#0
1
Full
#1
TXOVF
Transmit FIFO Overflow Flag\nThis bit will be set to 1 if writes data to transmit FIFO when transmit FIFO is full.\nWrite 1 to clear this bit to 0
17
1
read-write
0
No overflow
#0
1
Overflow
#1
TXTHF
Transmit FIFO Threshold Flag\nWhen data word(s) in transmit FIFO is equal to or lower than threshold value set in TXTH[2:0] the TXTHF bit becomes to 1. It keeps at 1 till TXFIFO_LEVEL[3:0] is higher than TXTH[1:0] after software writes TXFIFO register.\nThis bit is read only
18
1
read-write
0
Data word(s) in FIFO is higher than threshold level
#0
1
Data word(s) in FIFO is equal to or lower than threshold level
#1
TXUDF
Transmit FIFO Underflow Flag\nWhen transmit FIFO is empty and shift logic hardware read data from transmit FIFO causes this set to 1.\nSoftware can write 1 to clear this bit to 0
16
1
read-write
0
No underflow
#0
1
Underflow
#1
TX_LEVEL
Transmit FIFO Level\nThese bits indicate word number in transmit FIFO\n
28
4
read-write
0
No data
#0000
1
1 word in transmit FIFO
#0001
8
8 words in transmit FIFO
#1000
I2STXFIFO
I2STXFIFO
I2S Transmit FIFO Register
0x10
write-only
n
0x0
0x0
TXFIFO
Transmit FIFO Register\nI2S contains 8 words (8x32 bits) data buffer for data transmit. Write data to this register to prepare data for transmit. The remaining word number is indicated by TX_LEVEL[3:0] in I2SSTATUS register
0
32
write-only
INT
INT Register Map
INT
0x0
0x0
0x88
registers
n
IRQ0_SRC
IRQ0_SRC
IRQ0 (BOD) Interrupt Source Identity
0x0
read-only
n
0x0
0x0
INT_SRC
Bit2: 0\nBit1: 0\nBit0: BOD_INT
0
3
read-only
IRQ10_SRC
IRQ10_SRC
IRQ10 (TMR2) Interrupt Source Identity
0x28
read-only
n
0x0
0x0
INT_SRC
Bit2: 0\nBit1: 0\nBit0: TMR2_INT
0
3
read-only
IRQ11_SRC
IRQ11_SRC
IRQ11 (TMR3) Interrupt Source Identity
0x2C
read-only
n
0x0
0x0
INT_SRC
Bit2: 0\nBit1: 0\nBit0: TMR3_INT
0
3
read-only
IRQ12_SRC
IRQ12_SRC
IRQ12 (UART0/UART2) Interrupt Source Identity
0x30
read-only
n
0x0
0x0
INT_SRC
Bit2: 0 \nBit1: UART2_INT\nBit0: UART0_INT
0
3
read-only
IRQ13_SRC
IRQ13_SRC
IRQ13 (UART1) Interrupt Source Identity
0x34
read-only
n
0x0
0x0
INT_SRC
Bit2: 0\nBit1: 0\nBit0: UART1_INT
0
3
read-only
IRQ14_SRC
IRQ14_SRC
IRQ14 (SPI0) Interrupt Source Identity
0x38
read-only
n
0x0
0x0
INT_SRC
Bit2: 0\nBit1: 0\nBit0: SPI0_INT
0
3
read-only
IRQ15_SRC
IRQ15_SRC
IRQ15 (SPI1) Interrupt Source Identity
0x3C
read-only
n
0x0
0x0
INT_SRC
Bit2: 0\nBit1: 0\nBit0: SPI1_INT
0
3
read-only
IRQ16_SRC
IRQ16_SRC
IRQ16 (SPI2) Interrupt Source Identity
0x40
read-only
n
0x0
0x0
INT_SRC
Bit2: 0\nBit1: 0\nBit0: SPI2_INT
0
3
read-only
IRQ17_SRC
IRQ17_SRC
IRQ17 (SPI3) Interrupt Source Identity
0x44
read-only
n
0x0
0x0
INT_SRC
Bit2: 0\nBit1: 0\nBit0: SPI3_INT
0
3
read-only
IRQ18_SRC
IRQ18_SRC
IRQ18 (I2C0) Interrupt Source Identity
0x48
read-only
n
0x0
0x0
INT_SRC
Bit2: 0 \nBit1: 0\nBit0: I2C0_INT
0
3
read-only
IRQ19_SRC
IRQ19_SRC
IRQ19 (I2C1) Interrupt Source Identity
0x4C
read-only
n
0x0
0x0
INT_SRC
Bit2: 0 \nBit1: 0\nBit0: I2C1_INT
0
3
read-only
IRQ1_SRC
IRQ1_SRC
IRQ1 (WDT) Interrupt Source Identity
0x4
read-only
n
0x0
0x0
INT_SRC
Bit2: 0\nBit1: WWDT_INT\nBit0: WDT_INT
0
3
read-only
IRQ20_SRC
IRQ20_SRC
Reserved
0x50
read-only
n
0x0
0x0
IRQ21_SRC
IRQ21_SRC
Reserved
0x54
read-only
n
0x0
0x0
IRQ22_SRC
IRQ22_SRC
IRQ22 (SC0/SC1/SC2) Interrupt Source Identity
0x58
read-only
n
0x0
0x0
INT_SRC
Bit2: SC2_INT \nBit1: SC1_INT\nBit0: SC0_INT
0
3
read-only
IRQ23_SRC
IRQ23_SRC
IRQ23 (USB) Interrupt Source Identity
0x5C
read-only
n
0x0
0x0
INT_SRC
Bit2: 0\nBit1: 0\nBit0: USB_INT
0
3
read-only
IRQ24_SRC
IRQ24_SRC
IRQ24 (PS/2) Interrupt Source Identity
0x60
read-only
n
0x0
0x0
INT_SRC
Bit2: 0\nBit1: 0\nBit0: PS2_INT
0
3
read-only
IRQ25_SRC
IRQ25_SRC
IRQ25 (ACMP) Interrupt Source Identity
0x64
read-only
n
0x0
0x0
INT_SRC
Bit2: 0\nBit1: 0\nBit0: ACMP_INT
0
3
read-only
IRQ26_SRC
IRQ26_SRC
IRQ26 (PDMA) Interrupt Source Identity
0x68
read-only
n
0x0
0x0
INT_SRC
Bit2: 0\nBit1: 0\nBit0: PDMA_INT
0
3
read-only
IRQ27_SRC
IRQ27_SRC
IRQ27 (I2S) Interrupt Source Identity
0x6C
read-only
n
0x0
0x0
INT_SRC
Bit2: 0\nBit1: 0\nBit0: I2S_INT
0
3
read-only
IRQ28_SRC
IRQ28_SRC
IRQ28 (PWRWU) Interrupt Source Identity
0x70
read-only
n
0x0
0x0
INT_SRC
Bit2: 0\nBit1: 0\nBit0: PWRWU_INT
0
3
read-only
IRQ29_SRC
IRQ29_SRC
IRQ29 (ADC) Interrupt Source Identity
0x74
read-only
n
0x0
0x0
INT_SRC
Bit2: 0\nBit1: 0\nBit0: ADC_INT
0
3
read-only
IRQ2_SRC
IRQ2_SRC
IRQ2 (EINT0) Interrupt Source Identity
0x8
read-only
n
0x0
0x0
INT_SRC
Bit2: 0\nBit1: 0\nBit0: EINT0 - external interrupt 0
0
3
read-only
IRQ30_SRC
IRQ30_SRC
IRQ30 (IRCT) Interrupt Source Identity
0x78
read-only
n
0x0
0x0
INT_SRC
Bit2: 0\nBit1: 0\nBit0: IRCT_INT
0
3
read-only
IRQ31_SRC
IRQ31_SRC
IRQ31 (RTC) Interrupt Source Identity
0x7C
read-only
n
0x0
0x0
INT_SRC
Bit2: 0\nBit1: 0\nBit0: RTC_INT
0
3
read-only
IRQ3_SRC
IRQ3_SRC
IRQ3 (EINT1) Interrupt Source Identity
0xC
read-only
n
0x0
0x0
INT_SRC
Bit2: 0\nBit1: 0\nBit0: EINT1 - external interrupt 1
0
3
read-only
IRQ4_SRC
IRQ4_SRC
IRQ4 (GPA/GPB) Interrupt Source Identity
0x10
read-only
n
0x0
0x0
INT_SRC
Bit2: 0\nBit1: GPB_INT\nBit0: GPA_INT
0
3
read-only
IRQ5_SRC
IRQ5_SRC
IRQ5 (GPC/GPD/GPE/GPF) Interrupt Source Identity
0x14
read-only
n
0x0
0x0
INT_SRC
Bit3: GPF_INT\nBit2: GPE_INT\nBit1: GPD_INT\nBit0: GPC_INT
0
3
read-only
IRQ6_SRC
IRQ6_SRC
IRQ6 (PWMA) Interrupt Source Identity
0x18
read-only
n
0x0
0x0
INT_SRC
Bit3: PWM3_INT\nBit2: PWM2_INT\nBit1: PWM1_INT\nBit0: PWM0_INT
0
4
read-only
IRQ7_SRC
IRQ7_SRC
IRQ7 (PWMB) Interrupt Source Identity
0x1C
read-only
n
0x0
0x0
INT_SRC
Bit3: PWM7_INT\nBit2: PWM6_INT\nBit1: PWM5_INT\nBit0: PWM4_INT
0
4
read-only
IRQ8_SRC
IRQ8_SRC
IRQ8 (TMR0) Interrupt Source Identity
0x20
read-only
n
0x0
0x0
INT_SRC
Bit2: 0\nBit1: 0 \nBit0: TMR0_INT
0
3
read-only
IRQ9_SRC
IRQ9_SRC
IRQ9 (TMR1) Interrupt Source Identity
0x24
read-only
n
0x0
0x0
INT_SRC
Bit2: 0\nBit1: 0\nBit0: TMR1_INT
0
3
read-only
MCU_IRQ
MCU_IRQ
MCU Interrupt Request Source Register
0x84
read-write
n
0x0
0x0
MCU_IRQ
MCU IRQ Source Register\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0. There are two modes to generate interrupt to Cortex-M0, the normal mode and test mode.\nThe MCU_IRQ collects all interrupts from each peripheral and synchronizes them and interrupts the Cortex-M0.\nWhen the MCU_IRQ[n] is 0: Set MCU_IRQ[n] 1 will generate an interrupt to Cortex-M0 NVIC[n].\nWhen the MCU_IRQ[n] is 1 (mean an interrupt is assert), setting 1 to the MCU_IRQ[n] 1 will clear the interrupt and setting MCU_IRQ[n] 0: has no effect
0
32
read-write
NMI_SEL
NMI_SEL
NMI Source Interrupt Select Control Register
0x80
read-write
n
0x0
0x0
NMI_EN
NMI Interrupt Enable Bit (Write Protect)
Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
8
1
read-write
0
NMI interrupt Disabled
#0
1
NMI interrupt Enabled
#1
NMI_SEL
NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL.
0
5
read-write
NVIC
NVIC Register Map
NVIC
0x0
0x100
0x4
registers
n
0x180
0x4
registers
n
0x200
0x4
registers
n
0x280
0x4
registers
n
0x400
0x20
registers
n
ICER
NVIC_ICER
IRQ0 ~ IRQ31 Clear-enable Control Register
0x180
read-write
n
0x0
0x0
CLRENA
Disable one or more interrupts within a group of 32. Each Bit Represents an Interrupt Number From IRQ0 ~ IRQ31 (Vector Number From 16 ~ 47)\nThe register reads back with the current enable state.
0
32
read-write
0
No effect
0
1
Associated interrupt Enabled
1
ICPR
NVIC_ICPR
IRQ0 ~ IRQ31 Clear-pending Control Register
0x280
read-write
n
0x0
0x0
CLRPEND
The register reads back with the current pending state.
0
32
read-write
0
No effect
0
1
Remove the pending state of associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47)
1
IPR0
NVIC_IPR0
IRQ0 ~ IRQ3 Priority Control Register
0x400
read-write
n
0x0
0x0
PRI_0
Priority of IRQ0
0 denotes the highest priority and 3 denotes the lowest priority
6
2
read-write
PRI_1
Priority of IRQ1
0 denotes the highest priority and 3 denotes the lowest priority
14
2
read-write
PRI_2
Priority of IRQ2
0 denotes the highest priority and 3 denotes the lowest priority
22
2
read-write
PRI_3
Priority of IRQ3
0 denotes the highest priority and 3 denotes the lowest priority
30
2
read-write
IPR1
NVIC_IPR1
IRQ4 ~ IRQ7 Priority Control Register
0x404
read-write
n
0x0
0x0
PRI_4
Priority of IRQ4
0 denotes the highest priority and 3 denotes the lowest priority
6
2
read-write
PRI_5
Priority of IRQ5
0 denotes the highest priority and 3 denotes the lowest priority
14
2
read-write
PRI_6
Priority of IRQ6
0 denotes the highest priority and 3 denotes the lowest priority
22
2
read-write
PRI_7
Priority of IRQ7
0 denotes the highest priority and 3 denotes the lowest priority
30
2
read-write
IPR2
NVIC_IPR2
IRQ8 ~ IRQ11 Priority Control Register
0x408
read-write
n
0x0
0x0
PRI_10
Priority of IRQ10
0 denotes the highest priority and 3 denotes the lowest priority
22
2
read-write
PRI_11
Priority of IRQ11
0 denotes the highest priority and 3 denotes the lowest priority
30
2
read-write
PRI_8
Priority of IRQ8
0 denotes the highest priority and 3 denotes the lowest priority
6
2
read-write
PRI_9
Priority of IRQ9
0 denotes the highest priority and 3 denotes the lowest priority
14
2
read-write
IPR3
NVIC_IPR3
IRQ12 ~ IRQ15 Priority Control Register
0x40C
read-write
n
0x0
0x0
PRI_12
Priority of IRQ12
0 denotes the highest priority and 3 denotes the lowest priority
6
2
read-write
PRI_13
Priority of IRQ13
0 denotes the highest priority and 3 denotes the lowest priority
14
2
read-write
PRI_14
Priority of IRQ14
0 denotes the highest priority and 3 denotes the lowest priority
22
2
read-write
PRI_15
Priority of IRQ15
0 denotes the highest priority and 3 denotes the lowest priority
30
2
read-write
IPR4
NVIC_IPR4
IRQ16 ~ IRQ19 Priority Control Register
0x410
read-write
n
0x0
0x0
PRI_16
Priority of IRQ16
0 denotes the highest priority and 3 denotes the lowest priority
6
2
read-write
PRI_17
Priority of IRQ17
0 denotes the highest priority and 3 denotes the lowest priority
14
2
read-write
PRI_18
Priority of IRQ18
0 denotes the highest priority and 3 denotes the lowest priority
22
2
read-write
PRI_19
Priority of IRQ19
0 denotes the highest priority and 3 denotes the lowest priority
30
2
read-write
IPR5
NVIC_IPR5
IRQ20 ~ IRQ23 Priority Control Register
0x414
read-write
n
0x0
0x0
PRI_20
Priority of IRQ20
0 denotes the highest priority and 3 denotes the lowest priority
6
2
read-write
PRI_21
Priority of IRQ21
0 denotes the highest priority and 3 denotes the lowest priority
14
2
read-write
PRI_22
Priority of IRQ22
0 denotes the highest priority and 3 denotes the lowest priority
22
2
read-write
PRI_23
Priority of IRQ23
0 denotes the highest priority and 3 denotes the lowest priority
30
2
read-write
IPR6
NVIC_IPR6
IRQ24 ~ IRQ27 Priority Control Register
0x418
read-write
n
0x0
0x0
PRI_24
Priority of IRQ24
0 denotes the highest priority and 3 denotes the lowest priority
6
2
read-write
PRI_25
Priority of IRQ25
0 denotes the highest priority and 3 denotes the lowest priority
14
2
read-write
PRI_26
Priority of IRQ26
0 denotes the highest priority and 3 denotes the lowest priority
22
2
read-write
PRI_27
Priority of IRQ27
0 denotes the highest priority and 3 denotes the lowest priority
30
2
read-write
IPR7
NVIC_IPR7
IRQ28 ~ IRQ31 Priority Control Register
0x41C
read-write
n
0x0
0x0
PRI_28
Priority of IRQ28
0 denotes the highest priority and 3 denotes the lowest priority
6
2
read-write
PRI_29
Priority of IRQ29
0 denotes the highest priority and 3 denotes the lowest priority
14
2
read-write
PRI_30
Priority of IRQ30
0 denotes the highest priority and 3 denotes the lowest priority
22
2
read-write
PRI_31
Priority of IRQ31
0 denotes the highest priority and 3 denotes the lowest priority
30
2
read-write
ISER
NVIC_ISER
IRQ0 ~ IRQ31 Set-enable Control Register
0x100
read-write
n
0x0
0x0
SETENA
Enable one or more interrupts within a group of 32. Each Bit Represents an Interrupt Number From IRQ0 ~ IRQ31 (Vector Number From 16 ~ 47)\nThe register reads back with the current enable state.
0
32
read-write
0
No effect
0
1
Associated interrupt Enabled
1
ISPR
NVIC_ISPR
IRQ0 ~ IRQ31 Set-pending Control Register
0x200
read-write
n
0x0
0x0
SETPEND
The register reads back with the current pending state.
0
32
read-write
0
No effect
0
1
Set pending state of the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47)
1
PDMA_CH0
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x80
0x4
registers
n
PDMA_BCRx
PDMA_BCRx
PDMA Channel x Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
PDMA_BCR
PDMA Transfer Byte Count Register
This field indicates a 16-bit transfer byte count number of PDMA it must be word alignment.
0
16
read-write
PDMA_CBCRx
PDMA_CBCRx
PDMA Channel x Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
PDMA_CBCR
PDMA Current Byte Count Register (Read Only)
This field indicates the current remained byte count of PDMA.
Note: This field value will be cleared to 0, when software set PDMA_CSRx[SW_RST] to 1 .
0
16
read-only
PDMA_CDARx
PDMA_CDARx
PDMA Channel x Current Destination Address Register
0x18
read-only
n
0x0
0x0
PDMA_CDAR
PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSARx
PDMA_CSARx
PDMA Channel x Current Source Address Register
0x14
read-only
n
0x0
0x0
PDMA_CSAR
PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSRx
PDMA_CSRx
PDMA Channel x Control Register
0x0
read-write
n
0x0
0x0
APB_TWS
Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
19
2
read-write
0
One word (32-bit) is transferred for every PDMA operation
#00
1
One byte (8-bit) is transferred for every PDMA operation
#01
2
One half-word (16-bit) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Transfer Destination Address Direction Selection\n
6
2
read-write
0
Transfer destination address is increasing successively
#00
1
Reserved
#01
2
Transfer destination address is fixed. (This feature can be used when data where transferred from multiple sources to a single destination)
#10
3
Reserved
#11
MODE_SEL
PDMA Mode Selection\n
2
2
read-write
0
Memory to Memory mode (Memory-to-Memory)
#00
1
Peripheral to Memory mode (Peripheral-to-Memory)
#01
2
Memory to Peripheral mode (Memory-to-Peripheral)
#10
PDMACEN
PDMA Channel Enable\nSetting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n
0
1
read-write
SAD_SEL
Transfer Source Address Direction Selection\n
4
2
read-write
0
Transfer source address is increasing successively
#00
1
Reserved
#01
2
Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#10
3
Reserved
#11
SW_RST
Software Engine Reset\n
1
1
read-write
0
No effect
#0
1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles
#1
TRIG_EN
Trigger Enable\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
PDMA data read or write transfer Enabled
#1
PDMA_DARx
PDMA_DARx
PDMA Channel x Destination Address Register
0x8
read-write
n
0x0
0x0
PDMA_DAR
PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment.
0
32
read-write
PDMA_IERx
PDMA_IERx
PDMA Channel x Interrupt Enable Register
0x20
-1
read-write
n
0x0
0x0
BLKD_IE
PDMA Block Transfer Done Interrupt Enable\n
1
1
read-write
0
Interrupt generator Disabled when PDMA transfer is done
#0
1
Interrupt generator Enabled when PDMA transfer is done
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable\n
0
1
read-write
0
Target abort interrupt generation Disabled during PDMA transfer
#0
1
Target abort interrupt generation Enabled during PDMA transfer
#1
PDMA_ISRx
PDMA_ISRx
PDMA Channel x Interrupt Status Register
0x24
read-write
n
0x0
0x0
BLKD_IF
PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
Not finished
#0
1
Done
#1
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
PDMA_POINTx
PDMA_POINTx
PDMA Channel x Internal Buffer Pointer Register
0x10
read-only
n
0x0
0x0
PDMA_POINT
PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
0
4
read-only
PDMA_SARx
PDMA_SARx
PDMA Channel x Source Address Register
0x4
read-write
n
0x0
0x0
PDMA_SAR
PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.
0
32
read-write
PDMA_SBUF0_Cx
PDMA_SBUF0_Cx
PDMA Channel x Shared Buffer FIFO 0 Register
0x80
read-only
n
0x0
0x0
PDMA_SBUF0
PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer.
0
32
read-only
PDMA_CH1
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x80
0x4
registers
n
PDMA_BCRx
PDMA_BCRx
PDMA Channel x Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
PDMA_BCR
PDMA Transfer Byte Count Register
This field indicates a 16-bit transfer byte count number of PDMA it must be word alignment.
0
16
read-write
PDMA_CBCRx
PDMA_CBCRx
PDMA Channel x Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
PDMA_CBCR
PDMA Current Byte Count Register (Read Only)
This field indicates the current remained byte count of PDMA.
Note: This field value will be cleared to 0, when software set PDMA_CSRx[SW_RST] to 1 .
0
16
read-only
PDMA_CDARx
PDMA_CDARx
PDMA Channel x Current Destination Address Register
0x18
read-only
n
0x0
0x0
PDMA_CDAR
PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSARx
PDMA_CSARx
PDMA Channel x Current Source Address Register
0x14
read-only
n
0x0
0x0
PDMA_CSAR
PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSRx
PDMA_CSRx
PDMA Channel x Control Register
0x0
read-write
n
0x0
0x0
APB_TWS
Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
19
2
read-write
0
One word (32-bit) is transferred for every PDMA operation
#00
1
One byte (8-bit) is transferred for every PDMA operation
#01
2
One half-word (16-bit) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Transfer Destination Address Direction Selection\n
6
2
read-write
0
Transfer destination address is increasing successively
#00
1
Reserved
#01
2
Transfer destination address is fixed. (This feature can be used when data where transferred from multiple sources to a single destination)
#10
3
Reserved
#11
MODE_SEL
PDMA Mode Selection\n
2
2
read-write
0
Memory to Memory mode (Memory-to-Memory)
#00
1
Peripheral to Memory mode (Peripheral-to-Memory)
#01
2
Memory to Peripheral mode (Memory-to-Peripheral)
#10
PDMACEN
PDMA Channel Enable\nSetting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n
0
1
read-write
SAD_SEL
Transfer Source Address Direction Selection\n
4
2
read-write
0
Transfer source address is increasing successively
#00
1
Reserved
#01
2
Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#10
3
Reserved
#11
SW_RST
Software Engine Reset\n
1
1
read-write
0
No effect
#0
1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles
#1
TRIG_EN
Trigger Enable\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
PDMA data read or write transfer Enabled
#1
PDMA_DARx
PDMA_DARx
PDMA Channel x Destination Address Register
0x8
read-write
n
0x0
0x0
PDMA_DAR
PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment.
0
32
read-write
PDMA_IERx
PDMA_IERx
PDMA Channel x Interrupt Enable Register
0x20
-1
read-write
n
0x0
0x0
BLKD_IE
PDMA Block Transfer Done Interrupt Enable\n
1
1
read-write
0
Interrupt generator Disabled when PDMA transfer is done
#0
1
Interrupt generator Enabled when PDMA transfer is done
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable\n
0
1
read-write
0
Target abort interrupt generation Disabled during PDMA transfer
#0
1
Target abort interrupt generation Enabled during PDMA transfer
#1
PDMA_ISRx
PDMA_ISRx
PDMA Channel x Interrupt Status Register
0x24
read-write
n
0x0
0x0
BLKD_IF
PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
Not finished
#0
1
Done
#1
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
PDMA_POINTx
PDMA_POINTx
PDMA Channel x Internal Buffer Pointer Register
0x10
read-only
n
0x0
0x0
PDMA_POINT
PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
0
4
read-only
PDMA_SARx
PDMA_SARx
PDMA Channel x Source Address Register
0x4
read-write
n
0x0
0x0
PDMA_SAR
PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.
0
32
read-write
PDMA_SBUF0_Cx
PDMA_SBUF0_Cx
PDMA Channel x Shared Buffer FIFO 0 Register
0x80
read-only
n
0x0
0x0
PDMA_SBUF0
PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer.
0
32
read-only
PDMA_CH2
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x80
0x4
registers
n
PDMA_BCRx
PDMA_BCRx
PDMA Channel x Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
PDMA_BCR
PDMA Transfer Byte Count Register
This field indicates a 16-bit transfer byte count number of PDMA it must be word alignment.
0
16
read-write
PDMA_CBCRx
PDMA_CBCRx
PDMA Channel x Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
PDMA_CBCR
PDMA Current Byte Count Register (Read Only)
This field indicates the current remained byte count of PDMA.
Note: This field value will be cleared to 0, when software set PDMA_CSRx[SW_RST] to 1 .
0
16
read-only
PDMA_CDARx
PDMA_CDARx
PDMA Channel x Current Destination Address Register
0x18
read-only
n
0x0
0x0
PDMA_CDAR
PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSARx
PDMA_CSARx
PDMA Channel x Current Source Address Register
0x14
read-only
n
0x0
0x0
PDMA_CSAR
PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSRx
PDMA_CSRx
PDMA Channel x Control Register
0x0
read-write
n
0x0
0x0
APB_TWS
Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
19
2
read-write
0
One word (32-bit) is transferred for every PDMA operation
#00
1
One byte (8-bit) is transferred for every PDMA operation
#01
2
One half-word (16-bit) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Transfer Destination Address Direction Selection\n
6
2
read-write
0
Transfer destination address is increasing successively
#00
1
Reserved
#01
2
Transfer destination address is fixed. (This feature can be used when data where transferred from multiple sources to a single destination)
#10
3
Reserved
#11
MODE_SEL
PDMA Mode Selection\n
2
2
read-write
0
Memory to Memory mode (Memory-to-Memory)
#00
1
Peripheral to Memory mode (Peripheral-to-Memory)
#01
2
Memory to Peripheral mode (Memory-to-Peripheral)
#10
PDMACEN
PDMA Channel Enable\nSetting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n
0
1
read-write
SAD_SEL
Transfer Source Address Direction Selection\n
4
2
read-write
0
Transfer source address is increasing successively
#00
1
Reserved
#01
2
Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#10
3
Reserved
#11
SW_RST
Software Engine Reset\n
1
1
read-write
0
No effect
#0
1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles
#1
TRIG_EN
Trigger Enable\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
PDMA data read or write transfer Enabled
#1
PDMA_DARx
PDMA_DARx
PDMA Channel x Destination Address Register
0x8
read-write
n
0x0
0x0
PDMA_DAR
PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment.
0
32
read-write
PDMA_IERx
PDMA_IERx
PDMA Channel x Interrupt Enable Register
0x20
-1
read-write
n
0x0
0x0
BLKD_IE
PDMA Block Transfer Done Interrupt Enable\n
1
1
read-write
0
Interrupt generator Disabled when PDMA transfer is done
#0
1
Interrupt generator Enabled when PDMA transfer is done
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable\n
0
1
read-write
0
Target abort interrupt generation Disabled during PDMA transfer
#0
1
Target abort interrupt generation Enabled during PDMA transfer
#1
PDMA_ISRx
PDMA_ISRx
PDMA Channel x Interrupt Status Register
0x24
read-write
n
0x0
0x0
BLKD_IF
PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
Not finished
#0
1
Done
#1
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
PDMA_POINTx
PDMA_POINTx
PDMA Channel x Internal Buffer Pointer Register
0x10
read-only
n
0x0
0x0
PDMA_POINT
PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
0
4
read-only
PDMA_SARx
PDMA_SARx
PDMA Channel x Source Address Register
0x4
read-write
n
0x0
0x0
PDMA_SAR
PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.
0
32
read-write
PDMA_SBUF0_Cx
PDMA_SBUF0_Cx
PDMA Channel x Shared Buffer FIFO 0 Register
0x80
read-only
n
0x0
0x0
PDMA_SBUF0
PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer.
0
32
read-only
PDMA_CH3
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x80
0x4
registers
n
PDMA_BCRx
PDMA_BCRx
PDMA Channel x Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
PDMA_BCR
PDMA Transfer Byte Count Register
This field indicates a 16-bit transfer byte count number of PDMA it must be word alignment.
0
16
read-write
PDMA_CBCRx
PDMA_CBCRx
PDMA Channel x Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
PDMA_CBCR
PDMA Current Byte Count Register (Read Only)
This field indicates the current remained byte count of PDMA.
Note: This field value will be cleared to 0, when software set PDMA_CSRx[SW_RST] to 1 .
0
16
read-only
PDMA_CDARx
PDMA_CDARx
PDMA Channel x Current Destination Address Register
0x18
read-only
n
0x0
0x0
PDMA_CDAR
PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSARx
PDMA_CSARx
PDMA Channel x Current Source Address Register
0x14
read-only
n
0x0
0x0
PDMA_CSAR
PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSRx
PDMA_CSRx
PDMA Channel x Control Register
0x0
read-write
n
0x0
0x0
APB_TWS
Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
19
2
read-write
0
One word (32-bit) is transferred for every PDMA operation
#00
1
One byte (8-bit) is transferred for every PDMA operation
#01
2
One half-word (16-bit) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Transfer Destination Address Direction Selection\n
6
2
read-write
0
Transfer destination address is increasing successively
#00
1
Reserved
#01
2
Transfer destination address is fixed. (This feature can be used when data where transferred from multiple sources to a single destination)
#10
3
Reserved
#11
MODE_SEL
PDMA Mode Selection\n
2
2
read-write
0
Memory to Memory mode (Memory-to-Memory)
#00
1
Peripheral to Memory mode (Peripheral-to-Memory)
#01
2
Memory to Peripheral mode (Memory-to-Peripheral)
#10
PDMACEN
PDMA Channel Enable\nSetting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n
0
1
read-write
SAD_SEL
Transfer Source Address Direction Selection\n
4
2
read-write
0
Transfer source address is increasing successively
#00
1
Reserved
#01
2
Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#10
3
Reserved
#11
SW_RST
Software Engine Reset\n
1
1
read-write
0
No effect
#0
1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles
#1
TRIG_EN
Trigger Enable\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
PDMA data read or write transfer Enabled
#1
PDMA_DARx
PDMA_DARx
PDMA Channel x Destination Address Register
0x8
read-write
n
0x0
0x0
PDMA_DAR
PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment.
0
32
read-write
PDMA_IERx
PDMA_IERx
PDMA Channel x Interrupt Enable Register
0x20
-1
read-write
n
0x0
0x0
BLKD_IE
PDMA Block Transfer Done Interrupt Enable\n
1
1
read-write
0
Interrupt generator Disabled when PDMA transfer is done
#0
1
Interrupt generator Enabled when PDMA transfer is done
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable\n
0
1
read-write
0
Target abort interrupt generation Disabled during PDMA transfer
#0
1
Target abort interrupt generation Enabled during PDMA transfer
#1
PDMA_ISRx
PDMA_ISRx
PDMA Channel x Interrupt Status Register
0x24
read-write
n
0x0
0x0
BLKD_IF
PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
Not finished
#0
1
Done
#1
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
PDMA_POINTx
PDMA_POINTx
PDMA Channel x Internal Buffer Pointer Register
0x10
read-only
n
0x0
0x0
PDMA_POINT
PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
0
4
read-only
PDMA_SARx
PDMA_SARx
PDMA Channel x Source Address Register
0x4
read-write
n
0x0
0x0
PDMA_SAR
PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.
0
32
read-write
PDMA_SBUF0_Cx
PDMA_SBUF0_Cx
PDMA Channel x Shared Buffer FIFO 0 Register
0x80
read-only
n
0x0
0x0
PDMA_SBUF0
PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer.
0
32
read-only
PDMA_CH4
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x80
0x4
registers
n
PDMA_BCRx
PDMA_BCRx
PDMA Channel x Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
PDMA_BCR
PDMA Transfer Byte Count Register
This field indicates a 16-bit transfer byte count number of PDMA it must be word alignment.
0
16
read-write
PDMA_CBCRx
PDMA_CBCRx
PDMA Channel x Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
PDMA_CBCR
PDMA Current Byte Count Register (Read Only)
This field indicates the current remained byte count of PDMA.
Note: This field value will be cleared to 0, when software set PDMA_CSRx[SW_RST] to 1 .
0
16
read-only
PDMA_CDARx
PDMA_CDARx
PDMA Channel x Current Destination Address Register
0x18
read-only
n
0x0
0x0
PDMA_CDAR
PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSARx
PDMA_CSARx
PDMA Channel x Current Source Address Register
0x14
read-only
n
0x0
0x0
PDMA_CSAR
PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSRx
PDMA_CSRx
PDMA Channel x Control Register
0x0
read-write
n
0x0
0x0
APB_TWS
Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
19
2
read-write
0
One word (32-bit) is transferred for every PDMA operation
#00
1
One byte (8-bit) is transferred for every PDMA operation
#01
2
One half-word (16-bit) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Transfer Destination Address Direction Selection\n
6
2
read-write
0
Transfer destination address is increasing successively
#00
1
Reserved
#01
2
Transfer destination address is fixed. (This feature can be used when data where transferred from multiple sources to a single destination)
#10
3
Reserved
#11
MODE_SEL
PDMA Mode Selection\n
2
2
read-write
0
Memory to Memory mode (Memory-to-Memory)
#00
1
Peripheral to Memory mode (Peripheral-to-Memory)
#01
2
Memory to Peripheral mode (Memory-to-Peripheral)
#10
PDMACEN
PDMA Channel Enable\nSetting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n
0
1
read-write
SAD_SEL
Transfer Source Address Direction Selection\n
4
2
read-write
0
Transfer source address is increasing successively
#00
1
Reserved
#01
2
Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#10
3
Reserved
#11
SW_RST
Software Engine Reset\n
1
1
read-write
0
No effect
#0
1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles
#1
TRIG_EN
Trigger Enable\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
PDMA data read or write transfer Enabled
#1
PDMA_DARx
PDMA_DARx
PDMA Channel x Destination Address Register
0x8
read-write
n
0x0
0x0
PDMA_DAR
PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment.
0
32
read-write
PDMA_IERx
PDMA_IERx
PDMA Channel x Interrupt Enable Register
0x20
-1
read-write
n
0x0
0x0
BLKD_IE
PDMA Block Transfer Done Interrupt Enable\n
1
1
read-write
0
Interrupt generator Disabled when PDMA transfer is done
#0
1
Interrupt generator Enabled when PDMA transfer is done
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable\n
0
1
read-write
0
Target abort interrupt generation Disabled during PDMA transfer
#0
1
Target abort interrupt generation Enabled during PDMA transfer
#1
PDMA_ISRx
PDMA_ISRx
PDMA Channel x Interrupt Status Register
0x24
read-write
n
0x0
0x0
BLKD_IF
PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
Not finished
#0
1
Done
#1
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
PDMA_POINTx
PDMA_POINTx
PDMA Channel x Internal Buffer Pointer Register
0x10
read-only
n
0x0
0x0
PDMA_POINT
PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
0
4
read-only
PDMA_SARx
PDMA_SARx
PDMA Channel x Source Address Register
0x4
read-write
n
0x0
0x0
PDMA_SAR
PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.
0
32
read-write
PDMA_SBUF0_Cx
PDMA_SBUF0_Cx
PDMA Channel x Shared Buffer FIFO 0 Register
0x80
read-only
n
0x0
0x0
PDMA_SBUF0
PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer.
0
32
read-only
PDMA_CH5
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x80
0x4
registers
n
PDMA_BCRx
PDMA_BCRx
PDMA Channel x Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
PDMA_BCR
PDMA Transfer Byte Count Register
This field indicates a 16-bit transfer byte count number of PDMA it must be word alignment.
0
16
read-write
PDMA_CBCRx
PDMA_CBCRx
PDMA Channel x Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
PDMA_CBCR
PDMA Current Byte Count Register (Read Only)
This field indicates the current remained byte count of PDMA.
Note: This field value will be cleared to 0, when software set PDMA_CSRx[SW_RST] to 1 .
0
16
read-only
PDMA_CDARx
PDMA_CDARx
PDMA Channel x Current Destination Address Register
0x18
read-only
n
0x0
0x0
PDMA_CDAR
PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSARx
PDMA_CSARx
PDMA Channel x Current Source Address Register
0x14
read-only
n
0x0
0x0
PDMA_CSAR
PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSRx
PDMA_CSRx
PDMA Channel x Control Register
0x0
read-write
n
0x0
0x0
APB_TWS
Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
19
2
read-write
0
One word (32-bit) is transferred for every PDMA operation
#00
1
One byte (8-bit) is transferred for every PDMA operation
#01
2
One half-word (16-bit) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Transfer Destination Address Direction Selection\n
6
2
read-write
0
Transfer destination address is increasing successively
#00
1
Reserved
#01
2
Transfer destination address is fixed. (This feature can be used when data where transferred from multiple sources to a single destination)
#10
3
Reserved
#11
MODE_SEL
PDMA Mode Selection\n
2
2
read-write
0
Memory to Memory mode (Memory-to-Memory)
#00
1
Peripheral to Memory mode (Peripheral-to-Memory)
#01
2
Memory to Peripheral mode (Memory-to-Peripheral)
#10
PDMACEN
PDMA Channel Enable\nSetting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n
0
1
read-write
SAD_SEL
Transfer Source Address Direction Selection\n
4
2
read-write
0
Transfer source address is increasing successively
#00
1
Reserved
#01
2
Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#10
3
Reserved
#11
SW_RST
Software Engine Reset\n
1
1
read-write
0
No effect
#0
1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles
#1
TRIG_EN
Trigger Enable\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
PDMA data read or write transfer Enabled
#1
PDMA_DARx
PDMA_DARx
PDMA Channel x Destination Address Register
0x8
read-write
n
0x0
0x0
PDMA_DAR
PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment.
0
32
read-write
PDMA_IERx
PDMA_IERx
PDMA Channel x Interrupt Enable Register
0x20
-1
read-write
n
0x0
0x0
BLKD_IE
PDMA Block Transfer Done Interrupt Enable\n
1
1
read-write
0
Interrupt generator Disabled when PDMA transfer is done
#0
1
Interrupt generator Enabled when PDMA transfer is done
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable\n
0
1
read-write
0
Target abort interrupt generation Disabled during PDMA transfer
#0
1
Target abort interrupt generation Enabled during PDMA transfer
#1
PDMA_ISRx
PDMA_ISRx
PDMA Channel x Interrupt Status Register
0x24
read-write
n
0x0
0x0
BLKD_IF
PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
Not finished
#0
1
Done
#1
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
PDMA_POINTx
PDMA_POINTx
PDMA Channel x Internal Buffer Pointer Register
0x10
read-only
n
0x0
0x0
PDMA_POINT
PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
0
4
read-only
PDMA_SARx
PDMA_SARx
PDMA Channel x Source Address Register
0x4
read-write
n
0x0
0x0
PDMA_SAR
PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.
0
32
read-write
PDMA_SBUF0_Cx
PDMA_SBUF0_Cx
PDMA Channel x Shared Buffer FIFO 0 Register
0x80
read-only
n
0x0
0x0
PDMA_SBUF0
PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer.
0
32
read-only
PDMA_CH6
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x80
0x4
registers
n
PDMA_BCRx
PDMA_BCRx
PDMA Channel x Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
PDMA_BCR
PDMA Transfer Byte Count Register
This field indicates a 16-bit transfer byte count number of PDMA it must be word alignment.
0
16
read-write
PDMA_CBCRx
PDMA_CBCRx
PDMA Channel x Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
PDMA_CBCR
PDMA Current Byte Count Register (Read Only)
This field indicates the current remained byte count of PDMA.
Note: This field value will be cleared to 0, when software set PDMA_CSRx[SW_RST] to 1 .
0
16
read-only
PDMA_CDARx
PDMA_CDARx
PDMA Channel x Current Destination Address Register
0x18
read-only
n
0x0
0x0
PDMA_CDAR
PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSARx
PDMA_CSARx
PDMA Channel x Current Source Address Register
0x14
read-only
n
0x0
0x0
PDMA_CSAR
PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSRx
PDMA_CSRx
PDMA Channel x Control Register
0x0
read-write
n
0x0
0x0
APB_TWS
Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
19
2
read-write
0
One word (32-bit) is transferred for every PDMA operation
#00
1
One byte (8-bit) is transferred for every PDMA operation
#01
2
One half-word (16-bit) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Transfer Destination Address Direction Selection\n
6
2
read-write
0
Transfer destination address is increasing successively
#00
1
Reserved
#01
2
Transfer destination address is fixed. (This feature can be used when data where transferred from multiple sources to a single destination)
#10
3
Reserved
#11
MODE_SEL
PDMA Mode Selection\n
2
2
read-write
0
Memory to Memory mode (Memory-to-Memory)
#00
1
Peripheral to Memory mode (Peripheral-to-Memory)
#01
2
Memory to Peripheral mode (Memory-to-Peripheral)
#10
PDMACEN
PDMA Channel Enable\nSetting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n
0
1
read-write
SAD_SEL
Transfer Source Address Direction Selection\n
4
2
read-write
0
Transfer source address is increasing successively
#00
1
Reserved
#01
2
Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#10
3
Reserved
#11
SW_RST
Software Engine Reset\n
1
1
read-write
0
No effect
#0
1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles
#1
TRIG_EN
Trigger Enable\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
PDMA data read or write transfer Enabled
#1
PDMA_DARx
PDMA_DARx
PDMA Channel x Destination Address Register
0x8
read-write
n
0x0
0x0
PDMA_DAR
PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment.
0
32
read-write
PDMA_IERx
PDMA_IERx
PDMA Channel x Interrupt Enable Register
0x20
-1
read-write
n
0x0
0x0
BLKD_IE
PDMA Block Transfer Done Interrupt Enable\n
1
1
read-write
0
Interrupt generator Disabled when PDMA transfer is done
#0
1
Interrupt generator Enabled when PDMA transfer is done
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable\n
0
1
read-write
0
Target abort interrupt generation Disabled during PDMA transfer
#0
1
Target abort interrupt generation Enabled during PDMA transfer
#1
PDMA_ISRx
PDMA_ISRx
PDMA Channel x Interrupt Status Register
0x24
read-write
n
0x0
0x0
BLKD_IF
PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
Not finished
#0
1
Done
#1
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
PDMA_POINTx
PDMA_POINTx
PDMA Channel x Internal Buffer Pointer Register
0x10
read-only
n
0x0
0x0
PDMA_POINT
PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
0
4
read-only
PDMA_SARx
PDMA_SARx
PDMA Channel x Source Address Register
0x4
read-write
n
0x0
0x0
PDMA_SAR
PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.
0
32
read-write
PDMA_SBUF0_Cx
PDMA_SBUF0_Cx
PDMA Channel x Shared Buffer FIFO 0 Register
0x80
read-only
n
0x0
0x0
PDMA_SBUF0
PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer.
0
32
read-only
PDMA_CH7
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x80
0x4
registers
n
PDMA_BCRx
PDMA_BCRx
PDMA Channel x Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
PDMA_BCR
PDMA Transfer Byte Count Register
This field indicates a 16-bit transfer byte count number of PDMA it must be word alignment.
0
16
read-write
PDMA_CBCRx
PDMA_CBCRx
PDMA Channel x Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
PDMA_CBCR
PDMA Current Byte Count Register (Read Only)
This field indicates the current remained byte count of PDMA.
Note: This field value will be cleared to 0, when software set PDMA_CSRx[SW_RST] to 1 .
0
16
read-only
PDMA_CDARx
PDMA_CDARx
PDMA Channel x Current Destination Address Register
0x18
read-only
n
0x0
0x0
PDMA_CDAR
PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSARx
PDMA_CSARx
PDMA Channel x Current Source Address Register
0x14
read-only
n
0x0
0x0
PDMA_CSAR
PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSRx
PDMA_CSRx
PDMA Channel x Control Register
0x0
read-write
n
0x0
0x0
APB_TWS
Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
19
2
read-write
0
One word (32-bit) is transferred for every PDMA operation
#00
1
One byte (8-bit) is transferred for every PDMA operation
#01
2
One half-word (16-bit) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Transfer Destination Address Direction Selection\n
6
2
read-write
0
Transfer destination address is increasing successively
#00
1
Reserved
#01
2
Transfer destination address is fixed. (This feature can be used when data where transferred from multiple sources to a single destination)
#10
3
Reserved
#11
MODE_SEL
PDMA Mode Selection\n
2
2
read-write
0
Memory to Memory mode (Memory-to-Memory)
#00
1
Peripheral to Memory mode (Peripheral-to-Memory)
#01
2
Memory to Peripheral mode (Memory-to-Peripheral)
#10
PDMACEN
PDMA Channel Enable\nSetting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n
0
1
read-write
SAD_SEL
Transfer Source Address Direction Selection\n
4
2
read-write
0
Transfer source address is increasing successively
#00
1
Reserved
#01
2
Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#10
3
Reserved
#11
SW_RST
Software Engine Reset\n
1
1
read-write
0
No effect
#0
1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles
#1
TRIG_EN
Trigger Enable\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
PDMA data read or write transfer Enabled
#1
PDMA_DARx
PDMA_DARx
PDMA Channel x Destination Address Register
0x8
read-write
n
0x0
0x0
PDMA_DAR
PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment.
0
32
read-write
PDMA_IERx
PDMA_IERx
PDMA Channel x Interrupt Enable Register
0x20
-1
read-write
n
0x0
0x0
BLKD_IE
PDMA Block Transfer Done Interrupt Enable\n
1
1
read-write
0
Interrupt generator Disabled when PDMA transfer is done
#0
1
Interrupt generator Enabled when PDMA transfer is done
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable\n
0
1
read-write
0
Target abort interrupt generation Disabled during PDMA transfer
#0
1
Target abort interrupt generation Enabled during PDMA transfer
#1
PDMA_ISRx
PDMA_ISRx
PDMA Channel x Interrupt Status Register
0x24
read-write
n
0x0
0x0
BLKD_IF
PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
Not finished
#0
1
Done
#1
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
PDMA_POINTx
PDMA_POINTx
PDMA Channel x Internal Buffer Pointer Register
0x10
read-only
n
0x0
0x0
PDMA_POINT
PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
0
4
read-only
PDMA_SARx
PDMA_SARx
PDMA Channel x Source Address Register
0x4
read-write
n
0x0
0x0
PDMA_SAR
PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.
0
32
read-write
PDMA_SBUF0_Cx
PDMA_SBUF0_Cx
PDMA Channel x Shared Buffer FIFO 0 Register
0x80
read-only
n
0x0
0x0
PDMA_SBUF0
PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer.
0
32
read-only
PDMA_CH8
PDMA Register Map
PDMA
0x0
0x0
0x28
registers
n
0x80
0x4
registers
n
PDMA_BCRx
PDMA_BCRx
PDMA Channel x Transfer Byte Count Register
0xC
read-write
n
0x0
0x0
PDMA_BCR
PDMA Transfer Byte Count Register
This field indicates a 16-bit transfer byte count number of PDMA it must be word alignment.
0
16
read-write
PDMA_CBCRx
PDMA_CBCRx
PDMA Channel x Current Transfer Byte Count Register
0x1C
read-only
n
0x0
0x0
PDMA_CBCR
PDMA Current Byte Count Register (Read Only)
This field indicates the current remained byte count of PDMA.
Note: This field value will be cleared to 0, when software set PDMA_CSRx[SW_RST] to 1 .
0
16
read-only
PDMA_CDARx
PDMA_CDARx
PDMA Channel x Current Destination Address Register
0x18
read-only
n
0x0
0x0
PDMA_CDAR
PDMA Current Destination Address Register (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSARx
PDMA_CSARx
PDMA Channel x Current Source Address Register
0x14
read-only
n
0x0
0x0
PDMA_CSAR
PDMA Current Source Address Register (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
0
32
read-only
PDMA_CSRx
PDMA_CSRx
PDMA Channel x Control Register
0x0
read-write
n
0x0
0x0
APB_TWS
Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
19
2
read-write
0
One word (32-bit) is transferred for every PDMA operation
#00
1
One byte (8-bit) is transferred for every PDMA operation
#01
2
One half-word (16-bit) is transferred for every PDMA operation
#10
3
Reserved
#11
DAD_SEL
Transfer Destination Address Direction Selection\n
6
2
read-write
0
Transfer destination address is increasing successively
#00
1
Reserved
#01
2
Transfer destination address is fixed. (This feature can be used when data where transferred from multiple sources to a single destination)
#10
3
Reserved
#11
MODE_SEL
PDMA Mode Selection\n
2
2
read-write
0
Memory to Memory mode (Memory-to-Memory)
#00
1
Peripheral to Memory mode (Peripheral-to-Memory)
#01
2
Memory to Peripheral mode (Memory-to-Peripheral)
#10
PDMACEN
PDMA Channel Enable\nSetting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.\n
0
1
read-write
SAD_SEL
Transfer Source Address Direction Selection\n
4
2
read-write
0
Transfer source address is increasing successively
#00
1
Reserved
#01
2
Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#10
3
Reserved
#11
SW_RST
Software Engine Reset\n
1
1
read-write
0
No effect
#0
1
Reset the internal state machine, pointers and internal buffer. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles
#1
TRIG_EN
Trigger Enable\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. Software must reset all PDMA channel, and then trigger again.
23
1
read-write
0
No effect
#0
1
PDMA data read or write transfer Enabled
#1
PDMA_DARx
PDMA_DARx
PDMA Channel x Destination Address Register
0x8
read-write
n
0x0
0x0
PDMA_DAR
PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA.\nNote: The destination address must be word alignment.
0
32
read-write
PDMA_IERx
PDMA_IERx
PDMA Channel x Interrupt Enable Register
0x20
-1
read-write
n
0x0
0x0
BLKD_IE
PDMA Block Transfer Done Interrupt Enable\n
1
1
read-write
0
Interrupt generator Disabled when PDMA transfer is done
#0
1
Interrupt generator Enabled when PDMA transfer is done
#1
TABORT_IE
PDMA Read/Write Target Abort Interrupt Enable\n
0
1
read-write
0
Target abort interrupt generation Disabled during PDMA transfer
#0
1
Target abort interrupt generation Enabled during PDMA transfer
#1
PDMA_ISRx
PDMA_ISRx
PDMA Channel x Interrupt Status Register
0x24
read-write
n
0x0
0x0
BLKD_IF
PDMA Block Transfer Done Interrupt Flag\nThis bit indicates that PDMA has finished all transfers.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
Not finished
#0
1
Done
#1
TABORT_IF
PDMA Read/Write Target Abort Interrupt Flag\nWrite 1 to clear this bit to 0.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
PDMA_POINTx
PDMA_POINTx
PDMA Channel x Internal Buffer Pointer Register
0x10
read-only
n
0x0
0x0
PDMA_POINT
PDMA Internal Buffer Pointer Register (Read Only)\nThis field indicates the internal buffer pointer.
0
4
read-only
PDMA_SARx
PDMA_SARx
PDMA Channel x Source Address Register
0x4
read-write
n
0x0
0x0
PDMA_SAR
PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.
0
32
read-write
PDMA_SBUF0_Cx
PDMA_SBUF0_Cx
PDMA Channel x Shared Buffer FIFO 0 Register
0x80
read-only
n
0x0
0x0
PDMA_SBUF0
PDMA Shared Buffer FIFO 0 (Read Only)\nEach channel has its own 1 word internal buffer.
0
32
read-only
PDMA_GCR
PDMA Register Map
PDMA
0x0
0x0
0x14
registers
n
PDMA_GCRCSR
PDMA_GCRCSR
PDMA Global Control Register
0x0
read-write
n
0x0
0x0
CLK0_EN
PDMA Controller Channel 0 Clock Enable Control\n
8
1
read-write
0
Disabled
#0
1
Enabled
#1
CLK1_EN
PDMA Controller Channel 1 Clock Enable Control\n
9
1
read-write
0
Disabled
#0
1
Enabled
#1
CLK2_EN
PDMA Controller Channel 2 Clock Enable Control \n
10
1
read-write
0
Disabled
#0
1
Enabled
#1
CLK3_EN
PDMA Controller Channel 3 Clock Enable Control\n
11
1
read-write
0
Disabled
#0
1
Enabled
#1
CLK4_EN
PDMA Controller Channel 4 Clock Enable Control\n
12
1
read-write
0
Disabled
#0
1
Enabled
#1
CLK5_EN
PDMA Controller Channel 5 Clock Enable Control\n
13
1
read-write
0
Disabled
#0
1
Enabled
#1
CLK6_EN
PDMA Controller Channel 6 Clock Enable Control\n
14
1
read-write
0
Disabled
#0
1
Enabled
#1
CLK7_EN
PDMA Controller Channel 7 Clock Enable Control\n
15
1
read-write
0
Disabled
#0
1
Enabled
#1
CLK8_EN
PDMA Controller Channel 8 Clock Enable Control \n
16
1
read-write
0
Disabled
#0
1
Enabled
#1
CRC_CLK_EN
CRC Controller Clock Enable Control\n
24
1
read-write
0
Disabled
#0
1
Enabled
#1
PDMA_GCRISR
PDMA_GCRISR
PDMA Global Interrupt Status Register
0xC
read-only
n
0x0
0x0
INTR
Interrupt Status\nThis bit is the interrupt status of PDMA controller.\nNote: This bit is read only
31
1
read-only
INTR0
Interrupt Status of Channel 0\nThis bit is the interrupt status of PDMA channel0.\nNote: This bit is read only
0
1
read-only
INTR1
Interrupt Status of Channel 1\nThis bit is the interrupt status of PDMA channel1.\nNote: This bit is read only
1
1
read-only
INTR2
Interrupt Status of Channel 2\nThis bit is the interrupt status of PDMA channel2.\nNote: This bit is read only
2
1
read-only
INTR3
Interrupt Status of Channel 3\nThis bit is the interrupt status of PDMA channel3.\nNote: This bit is read only
3
1
read-only
INTR4
Interrupt Status of Channel 4\nThis bit is the interrupt status of PDMA channel4.\nNote: This bit is read only
4
1
read-only
INTR5
Interrupt Status of Channel 5 \nThis bit is the interrupt status of PDMA channel5.\nNote: This bit is read only
5
1
read-only
INTR6
Interrupt Status of Channel 6 \nThis bit is the interrupt status of PDMA channel6.\nNote: This bit is read only
6
1
read-only
INTR7
Interrupt Status of Channel 7 \nThis bit is the interrupt status of PDMA channel7.\nNote: This bit is read only
7
1
read-only
INTR8
Interrupt Status of Channel 8 \nThis bit is the interrupt status of PDMA channel8.\nNote: This bit is read only
8
1
read-only
INTRCRC
Interrupt Status of CRC Controller\nThis bit is the interrupt status of CRC controller\nNote: This bit is read only
16
1
read-only
PDMA_PDSSR0
PDMA_PDSSR0
PDMA Service Selection Control Register 0
0x4
-1
read-write
n
0x0
0x0
SPI0_RXSEL
PDMA SPI0 RX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI0 RX. Software can change the channel RX setting by SPI0_RXSEL\n4'b0000: CH0\n4'b0001: CH1\n4'b0010: CH2\n4'b0011: CH3 \n4'b0100: CH4 \n4'b0101: CH5\n4'b0110: CH6\n4'b0111: CH7\n4'b1000: CH8\nOthers : Reserved\n
0
4
read-write
SPI0_TXSEL
PDMA SPI0 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI0 TX. Software can configure the TX channel setting by SPI0_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.
4
4
read-write
SPI1_RXSEL
PDMA SPI1 RX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI1 RX. Software can configure the RX channel setting by SPI1_RXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.
8
4
read-write
SPI1_TXSEL
PDMA SPI1 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI1 TX. Software can configure the TX channel setting by SPI1_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.
12
4
read-write
SPI2_RXSEL
PDMA SPI2 RX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI2 RX. Software can configure the RX channel setting by SPI2_RXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.
16
4
read-write
SPI2_TXSEL
PDMA SPI2 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI2 TX. Software can configure the TX channel setting by SPI2_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.
20
4
read-write
SPI3_RXSEL
PDMA SPI3 RX Selection \nThis field defines which PDMA channel is connected to the on-chip peripheral SPI3 RX. Software can configure the RX channel setting by SPI3_RXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.
24
4
read-write
SPI3_TXSEL
PDMA SPI3 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral SPI3 TX. Software can configure the TX channel setting by SPI3_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.
28
4
read-write
PDMA_PDSSR1
PDMA_PDSSR1
PDMA Service Selection Control Register 1
0x8
-1
read-write
n
0x0
0x0
ADC_RXSEL
PDMA ADC RX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral ADC RX. Software can configure the RX channel setting by ADC_RXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL
24
4
read-write
UART0_RXSEL
PDMA UART0 RX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral UART0 RX. Software can change the channel RX setting by UART0_RXSEL\n4'b0000: CH0\n4'b0001: CH1\n4'b0010: CH2\n4'b0011: CH3 \n4'b0100: CH4 \n4'b0101: CH5\n4'b0110: CH6\n4'b0111: CH7\n4'b1000: CH8\nOthers : Reserved\n
0
4
read-write
UART0_TXSEL
PDMA UART0 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral UART0 TX. Software can configure the TX channel setting by UART0_TXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL
4
4
read-write
UART1_RXSEL
PDMA UART1 RX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral UART1 RX. Software can configure the RX channel setting by UART1_RXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL
8
4
read-write
UART1_TXSEL
PDMA UART1 TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral UART1 TX. Software can configure the TX channel setting by UART1_TXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL
12
4
read-write
PDMA_PDSSR2
PDMA_PDSSR2
PDMA Service Selection Control Register 2
0x10
-1
read-write
n
0x0
0x0
I2S_RXSEL
PDMA I2S RX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral I2S RX. Software can change the channel RX setting by I2S_RXSEL\n4'b0000: CH0\n4'b0001: CH1\n4'b0010: CH2\n4'b0011: CH3\n4'b0100: CH4\n4'b0101: CH5\n4'b0110: CH6\n4'b0111: CH7\n4'b1000: CH8\nOthers : Reserved\n
0
4
read-write
I2S_TXSEL
PDMA I2S TX Selection\nThis field defines which PDMA channel is connected to the on-chip peripheral I2S TX. Software can configure the TX channel setting by I2S_TXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL.
4
4
read-write
PS2
PS2 Register Map
PS2
0x0
0x0
0x20
registers
n
PS2CON
PS2CON
PS/2 Control Register
0x0
read-write
n
0x0
0x0
ACK
Acknowledge Enable\n
7
1
read-write
0
Always send acknowledge to host at 12th clock for host to device communication
#0
1
If parity bit error or stop bit is not received correctly, acknowledge bit will not be sent to host at 12th clock
#1
CLRFIFO
Clear TX FIFO\nWrite 1 to this bit to terminate device to host transmission. The TXEMPTY bit in PS2STATUS bit will be set to 1 and pointer BYTEIDEX is reset to 0 regardless there is residue data in buffer or not. The buffer content is not been cleared.\n
8
1
read-write
0
Not active
#0
1
Clear FIFO
#1
FPS2CLK
Force PS2_CLK Line\nIt forces PS2_CLK line high or low regardless of the internal state of the device controller if OVERRIDE is set to 1.\n
10
1
read-write
0
Force PS2_CLK line low
#0
1
Force PS2_CLK line high
#1
FPS2DAT
Force PS2_DAT Line\nIt forces PS2_DAT high or low regardless of the internal state of the device controller if OVERRIDE is set to 1.\n
11
1
read-write
0
Force PS2_DAT low
#0
1
Force PS2_DAT high
#1
OVERRIDE
Software Override PS2 CLK/DAT Pin State\n
9
1
read-write
0
PS2_CLK and PS2_DAT pins are controlled by internal state machine
#0
1
PS2_CLK and PS2_DAT pins are controlled by software
#1
PS2EN
Enable PS/2 Device\nEnable PS/2 device controller\n
0
1
read-write
0
Disabled
#0
1
Enabled
#1
RXINTEN
Enable Receive Interrupt\n
2
1
read-write
0
Data receive complete interrupt Disabled
#0
1
Data receive complete interrupt Enabled
#1
TXFIFO_DEPTH
Transmit Data FIFO Depth\nThere are 16 bytes buffer for data transmit. Software can define the FIFO depth from 1 to 16 bytes depends on application needs.\n
3
4
read-write
0
1 byte
0
1
2 bytes
1
14
15 bytes
14
15
16 bytes
15
TXINTEN
Enable Transmit Interrupt\n
1
1
read-write
0
Data transmit complete interrupt Disabled
#0
1
Data transmit complete interrupt Enabled
#1
PS2INTID
PS2INTID
PS/2 Interrupt Identification Register
0x1C
read-write
n
0x0
0x0
RXINT
Receive Interrupt\nThis bit is set to 1 when acknowledge bit is sent for Host to device communication. Interrupt occurs if RXINTEN bit is set to 1.\nWrite 1 to clear this bit to 0.
0
1
read-write
0
No interrupt
#0
1
Receive interrupt occurs
#1
TXINT
Transmit Interrupt\nThis bit is set to 1 after STOP bit is transmitted. Interrupt occur if TXINTEN bit is set to 1.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
No interrupt
#0
1
Transmit interrupt occurs
#1
PS2RXDATA
PS2RXDATA
PS/2 Receive Data Register
0x14
read-only
n
0x0
0x0
RXDATA
Received Data
For host to device communication, after acknowledge bit is sent, the received data is copied from receive shift register to PS2RXDATA register. CPU must read this register before next byte reception complete otherwise the data will be overwritten and RXOVF bit in PS2STATUS[6] will be set to 1.
0
8
read-only
PS2STATUS
PS2STATUS
PS/2 Status Register
0x18
-1
read-write
n
0x0
0x0
BYTEIDX
Byte Index\n
8
4
read-write
FRAMERR
Frame Error
For host to device communication, this bit sets to 1 if STOP bit (logic 1) is not received. If frame error occurs, the DATA line may keep at low state after 12th clock. At this moment, software overrides PS2_CLK to send clock till PS2_DAT release to high state. After that, device sends a Resend command to host.
Write 1 to clear this bit.
2
1
read-write
0
No frame error
#0
1
Frame error occur
#1
PS2CLK
CLK Pin State\nThis bit reflects the status of the PS2_CLK line after synchronizing.
0
1
read-write
PS2DATA
DATA Pin State\nThis bit reflects the status of the PS2_DAT line after synchronizing and sampling.
1
1
read-write
RXBUSY
Receive Busy\nThis bit indicates that the PS/2 device is currently receiving data.\nThis bit is read only.
4
1
read-write
0
Idle
#0
1
Currently receiving data
#1
RXOVF
RX Buffer Overwrite\nWrite 1 to clear this bit.
6
1
read-write
0
No overwrite
#0
1
Data in PS2RXDATA register is overwritten by new received data
#1
RXPARITY
Received Parity\nThis bit reflects the parity bit for the last received data byte (odd parity).\nThis bit is read only.
3
1
read-write
TXBUSY
Transmit Busy\nThis bit indicates that the PS/2 device is currently sending data.\nThis bit is read only.
5
1
read-write
0
Idle
#0
1
Currently sending data
#1
TXEMPTY
TX FIFO Empty\nWhen software writes data to PS2TXDATA0-3, the TXEMPTY bit is cleared to 0 immediately if PS2EN is enabled. When transmitted data byte number is equal to FIFODEPTH then TXEMPTY bit is set to 1.\nThis bit is read only.
7
1
read-write
0
There is data to be transmitted
#0
1
FIFO is empty
#1
PS2TXDATA0
PS2TXDATA0
PS/2 Transmit Data Register 0
0x4
read-write
n
0x0
0x0
PS2TXDATAx
Transmit Data\nWriting data to this register starts in device to host communication if bus is in IDLE state. Software must enable PS2EN before writing data to TX buffer.
0
32
read-write
PS2TXDATA1
PS2TXDATA1
PS/2 Transmit Data Register 1
0x8
read-write
n
0x0
0x0
PS2TXDATA2
PS2TXDATA2
PS/2 Transmit Data Register 2
0xC
read-write
n
0x0
0x0
PS2TXDATA3
PS2TXDATA3
PS/2 Transmit Data Register 3
0x10
read-write
n
0x0
0x0
PWMA
PWM Register Map
PWM
0x0
0x0
0x48
registers
n
0x50
0x48
registers
n
CAPENR
CAPENR
PWM Capture Input 0~3 Enable Register
0x78
read-write
n
0x0
0x0
CINEN0
Channel 0 Capture Input Enable\n
0
1
read-write
0
PWM Channel 0 capture input path Disabled. The input of PWM channel 0 capture function is always regarded as 0
#0
1
PWM Channel 0 capture input path Enabled. The input of PWM channel 0 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM0
#1
CINEN1
Channel 1 Capture Input Enable\n
1
1
read-write
0
PWM Channel 1 capture input path Disabled. The input of PWM channel 1 capture function is always regarded as 0
#0
1
PWM Channel 1 capture input path Enabled. The input of PWM channel 1 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM1
#1
CINEN2
Channel 2 Capture Input Enable\n
2
1
read-write
0
PWM Channel 2 capture input path Disabled. The input of PWM channel 2 capture function is always regarded as 0
#0
1
PWM Channel 2 capture input path Enabled. The input of PWM channel 2 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM2
#1
CINEN3
Channel 3 Capture Input Enable\n
3
1
read-write
0
PWM Channel 3 capture input path Disabled. The input of PWM channel 3 capture function is always regarded as 0
#0
1
PWM Channel 3 capture input path Enabled. The input of PWM channel 3 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM3
#1
CCR0
CCR0
PWM Capture Control Register 0
0x50
read-write
n
0x0
0x0
CAPCH0EN
Channel 0 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 0 Interrupt.
3
1
read-write
0
Capture function on PWM group channel 0 Disabled
#0
1
Capture function on PWM group channel 0 Enabled
#1
CAPCH1EN
Channel 1 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 1 Interrupt.
19
1
read-write
0
Capture function on PWM group channel 1 Disabled
#0
1
Capture function on PWM group channel 1 Enabled
#1
CAPIF0
Channel 0 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0.
4
1
read-write
CAPIF1
Channel 1 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0.
20
1
read-write
CFLRI0
CFLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a falling transition, CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear this bit to0 if BCn bit is 1.
7
1
read-write
CFLRI1
CFLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a falling transition, CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0, and can write 1 to clear this bit to 0 if BCn bit is 1.
23
1
read-write
CFL_IE0
Channel 0 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 0 has falling transition, Capture will issue an Interrupt.
2
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CFL_IE1
Channel 1 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 1 has falling transition, Capture will issue an Interrupt.
18
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CRLRI0
CRLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a rising transition, CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear this bit to 0 if the BCn bit is 1.
6
1
read-write
CRLRI1
CRLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a rising transition, CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0, and can write 1 to clear this bit to0 if BCn bit is 1.
22
1
read-write
CRL_IE0
Channel 0 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 0 has rising transition, Capture will issue an Interrupt.
1
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
CRL_IE1
Channel 1 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 1 has rising transition, Capture will issue an Interrupt.
17
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
INV0
Channel 0 Inverter Enable\n
0
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
INV1
Channel 1 Inverter Enable\n
16
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
CCR2
CCR2
PWM Capture Control Register 2
0x54
read-write
n
0x0
0x0
CAPCH2EN
Channel 2 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 2 Interrupt.
3
1
read-write
0
Capture function on PWM group channel 2 Disabled
#0
1
Capture function on PWM group channel 2 Enabled
#1
CAPCH3EN
Channel 3 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 3 Interrupt.
19
1
read-write
0
Capture function on PWM group channel 3 Disabled
#0
1
Capture function on PWM group channel 3 Enabled
#1
CAPIF2
Channel 2 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0
4
1
read-write
CAPIF3
Channel 3 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0
20
1
read-write
CFLRI2
CFLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a falling transition, CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0, and can write 1 to clear this bit to 0 if the BCn bit is 1.
7
1
read-write
CFLRI3
CFLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a falling transition, CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear this bit to 0 if the BCn bit is 1.
23
1
read-write
CFL_IE2
Channel 2 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 2 has falling transition, Capture will issue an Interrupt.
2
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CFL_IE3
Channel 3 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 3 has falling transition, Capture will issue an Interrupt.
18
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CRLRI2
CRLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a rising transition, CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear this bit to 0 if the BCn bit is 1.
6
1
read-write
CRLRI3
CRLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a rising transition, CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear this bit to 0 if the BCn bit is 1.
22
1
read-write
CRL_IE2
Channel 2 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 2 has rising transition, Capture will issue an Interrupt.
1
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
CRL_IE3
Channel 3 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 3 has rising transition, Capture will issue an Interrupt.
17
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
INV2
Channel 2 Inverter Enable\n
0
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
INV3
Channel 3 Inverter Enable\n
16
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
CFLR0
CFLR0
PWM Capture Falling Latch Register (Channel 0)
0x5C
read-only
n
0x0
0x0
CFLRx
Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition.
0
16
read-only
CFLR1
CFLR1
PWM Capture Falling Latch Register (Channel 1)
0x64
read-write
n
0x0
0x0
CFLR2
CFLR2
PWM Capture Falling Latch Register (Channel 2)
0x6C
read-write
n
0x0
0x0
CFLR3
CFLR3
PWM Capture Falling Latch Register (Channel 3)
0x74
read-write
n
0x0
0x0
CMR0
CMR0
PWM Comparator Register 0
0x10
read-write
n
0x0
0x0
CMRx
PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in next PWM cycle.
0
16
read-write
CMR1
CMR1
PWM Comparator Register 1
0x1C
read-write
n
0x0
0x0
CMR2
CMR2
PWM Comparator Register 2
0x28
read-write
n
0x0
0x0
CMR3
CMR3
PWM Comparator Register 3
0x34
read-write
n
0x0
0x0
CNR0
CNR0
PWM Counter Register 0
0xC
read-write
n
0x0
0x0
CNRx
PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle.\nNote: When PWM operating at Center-aligned type, CNR value should be set between 0x0000 to 0xFFFE. If CNR equal to 0xFFFF, the PWM will work unpredictable.\nNote: When CNR value is set to 0, PWM output is always high.
0
16
read-write
CNR1
CNR1
PWM Counter Register 1
0x18
read-write
n
0x0
0x0
CNR2
CNR2
PWM Counter Register 2
0x24
read-write
n
0x0
0x0
CNR3
CNR3
PWM Counter Register 3
0x30
read-write
n
0x0
0x0
CRLR0
CRLR0
PWM Capture Rising Latch Register (Channel 0)
0x58
read-only
n
0x0
0x0
CRLRx
Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition.
0
16
read-only
CRLR1
CRLR1
PWM Capture Rising Latch Register (Channel 1)
0x60
read-write
n
0x0
0x0
CRLR2
CRLR2
PWM Capture Rising Latch Register (Channel 2)
0x68
read-write
n
0x0
0x0
CRLR3
CRLR3
PWM Capture Rising Latch Register (Channel 3)
0x70
read-write
n
0x0
0x0
CSR
CSR
PWM Clock Source Divider Select Register
0x4
read-write
n
0x0
0x0
CSR0
PWM Timer 0 Clock Source Divider Selection (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\nSelect clock source divider for PWM timer 0.\n(Table is the same as CSR3)
0
3
read-write
CSR1
PWM Timer 1 Clock Source Divider Selection (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\nSelect clock source divider for PWM timer 1.\n(Table is the same as CSR3)
4
3
read-write
CSR2
PWM Timer 2 Clock Source Divider Selection (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\nSelect clock source divider for PWM timer 2.\n(Table is the same as CSR3)
8
3
read-write
CSR3
PWM Timer 3 Clock Source Divider Selection (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n
12
3
read-write
PBCR
PBCR
PWM Backward Compatible Register
0x3C
read-write
n
0x0
0x0
BCn
PWM Backward Compatible Register\nRefer to the CCR0/CCR2 register bit 6, 7, 22, 23 description\nNote: It is recommended that this bit be set to 1 to prevent CFLRIx and CRLRIx from being cleared when writing CCR0/CCR2.
0
1
read-write
0
Configure write 0 to clear CFLRI0~3 and CRLRI0~3
#0
1
Configure write 1 to clear CFLRI0~3 and CRLRI0~3
#1
PCR
PCR
PWM Control Register
0x8
read-write
n
0x0
0x0
CH0EN
PWM-timer 0 Enable (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\n
0
1
read-write
0
The corresponding PWM-Timer stops running
#0
1
The corresponding PWM-Timer starts running
#1
CH0INV
PWM-timer 0 Output Inverter Enable (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\n
2
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH0MOD
PWM-timer 0 Auto-reload/One-shot Mode (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\nNote: If there is a transition at this bit, it will cause CNR0 and CMR0 be cleared.
3
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH0PINV
PWM-timer 0 Output Polar Inverse Enable (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\n
1
1
read-write
0
PWM0 output polar inverse Disabled
#0
1
PWM0 output polar inverse Enabled
#1
CH1EN
PWM-timer 1 Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n
8
1
read-write
0
Corresponding PWM-Timer Stopped
#0
1
Corresponding PWM-Timer Start Running
#1
CH1INV
PWM-timer 1 Output Inverter Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n
10
1
read-write
0
Inverter Disable
#0
1
Inverter Enable
#1
CH1MOD
PWM-timer 1 Auto-reload/One-shot Mode (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\nNote: If there is a transition at this bit, it will cause CNR1 and CMR1 be cleared.
11
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH1PINV
PWM-timer 1 Output Polar Inverse Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n
9
1
read-write
0
PWM1 output polar inverse Disabled
#0
1
PWM1 output polar inverse Enabled
#1
CH2EN
PWM-timer 2 Enable (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\n
16
1
read-write
0
Corresponding PWM-Timer Stopped
#0
1
Corresponding PWM-Timer Start Running
#1
CH2INV
PWM-timer 2 Output Inverter Enable (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\n
18
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH2MOD
PWM-timer 2 Auto-reload/One-shot Mode (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\nNote: If there is a transition at this bit, it will cause CNR2 and CMR2 be cleared.
19
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH2PINV
PWM-timer 2 Output Polar Inverse Enable (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\n
17
1
read-write
0
PWM2 output polar inverse Disabled
#0
1
PWM2 output polar inverse Enabled
#1
CH3EN
PWM-timer 3 Enable (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n
24
1
read-write
0
Corresponding PWM-Timer Stopped
#0
1
Corresponding PWM-Timer Start Running
#1
CH3INV
PWM-timer 3 Output Inverter Enable (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n
26
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH3MOD
PWM-timer 3 Auto-reload/One-shot Mode (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\nNote: If there is a transition at this bit, it will cause CNR3 and CMR3 be cleared.
27
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH3PINV
PWM-timer 3 Output Polar Inverse Enable (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n
25
1
read-write
0
PWM3 output polar inverse Disable
#0
1
PWM3 output polar inverse Enable
#1
DZEN01
Dead-zone 0 Generator Enable (PWM0 and PWM1 Pair for PWM Group A, PWM4 and PWM5 Pair for PWM Group B)\nNote: When Dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4 and PWM5 becomes a complementary pair for PWM group B.
4
1
read-write
0
Disabled
#0
1
Enabled
#1
DZEN23
Dead-zone 2 Generator Enable (PWM2 and PWM3 Pair for PWM Group A, PWM6 and PWM7 Pair for PWM Group B)\nNote: When Dead-zone generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6 and PWM7 becomes a complementary pair for PWM group B.
5
1
read-write
0
Disabled
#0
1
Enabled
#1
PWM01TYPE
PWM01 Aligned Type Selection Bit (PWM0 and PWM1 Pair for PWM Group A, PWM4 and PWM5 Pair for PWM Group B)\n
30
1
read-write
0
Edge-aligned type
#0
1
Center-aligned type
#1
PWM23TYPE
PWM23 Aligned Type Selection Bit (PWM2 and PWM3 Pair for PWM Group A, PWM6 and PWM7 Pair for PWM Group B)\n
31
1
read-write
0
Edge-aligned type
#0
1
Center-aligned type
#1
PDR0
PDR0
PWM Data Register 0
0x14
read-only
n
0x0
0x0
PDRx
PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter.
0
16
read-only
PDR1
PDR1
PWM Data Register 1
0x20
read-write
n
0x0
0x0
PDR2
PDR2
PWM Data Register 2
0x2C
read-write
n
0x0
0x0
PDR3
PDR3
PWM Data Register 3
0x38
read-write
n
0x0
0x0
PIER
PIER
PWM Interrupt Enable Register
0x40
read-write
n
0x0
0x0
INT01TYPE
PWM01 Interrupt Period Type Selection Bit (PWM0 and PWM1 Pair for PWM Group A, PWM4 and PWM5 Pair for PWM Group B)\nNote: This bit is effective when PWM in Center-aligned type only.
16
1
read-write
0
PWMIFn will be set if PWM counter underflow
#0
1
PWMIFn will be set if PWM counter matches CNRn register
#1
INT23TYPE
PWM23 Interrupt Period Type Selection Bit (PWM2 and PWM3 Pair for PWM Group A, PWM6 and PWM7 Pair for PWM Group B)\nNote: This bit is effective when PWM in Center-aligned type only.
17
1
read-write
0
PWMIFn will be set if PWM counter underflow
#0
1
PWMIFn will be set if PWM counter matches CNRn register
#1
PWMDIE0
PWM Channel 0 Duty Interrupt Enable\n
8
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
PWMDIE1
PWM Channel 1 Duty Interrupt Enable\n
9
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
PWMDIE2
PWM Channel 2 Duty Interrupt Enable\n
10
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
PWMDIE3
PWM Channel 3 Duty Interrupt Enable\n
11
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
PWMIE0
PWM Channel 0 Period Interrupt Enable\n
0
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
PWMIE1
PWM Channel 1 Period Interrupt Enable\n
1
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
PWMIE2
PWM Channel 2 Period Interrupt Enable\n
2
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
PWMIE3
PWM Channel 3 Period Interrupt Enable\n
3
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
PIIR
PIIR
PWM Interrupt Indication Register
0x44
read-write
n
0x0
0x0
PWMDIF0
PWM Channel 0 Duty Interrupt Flag\nFlag is set by hardware when channel 0 PWM counter down count and reaches CMR0, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in Edge-aligned type selection
8
1
read-write
PWMDIF1
PWM Channel 1 Duty Interrupt Flag\nFlag is set by hardware when channel 1 PWM counter down count and reaches CMR1, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in Edge-aligned type selection
9
1
read-write
PWMDIF2
PWM Channel 2 Duty Interrupt Flag\nFlag is set by hardware when channel 2 PWM counter down count and reaches CMR2, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in Edge-aligned type selection
10
1
read-write
PWMDIF3
PWM Channel 3 Duty Interrupt Flag\nFlag is set by hardware when channel 3 PWM counter down count and reaches CMR3, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in Edge-aligned type selection
11
1
read-write
PWMIF0
PWM Channel 0 Period Interrupt Status\nThis bit is set by hardware when PWM0 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register), software can write 1 to clear this bit to 0.
0
1
read-write
PWMIF1
PWM Channel 1 Period Interrupt Status\nThis bit is set by hardware when PWM1 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register), software can write 1 to clear this bit to 0.
1
1
read-write
PWMIF2
PWM Channel 2 Period Interrupt Status\nThis bit is set by hardware when PWM2 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register), software can write 1 to clear this bit to 0.
2
1
read-write
PWMIF3
PWM Channel 3 Period Interrupt Status\nThis bit is set by hardware when PWM3 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register), software can write 1 to clear this bit to 0.
3
1
read-write
POE
POE
PWM Output Enable for Channel 0~3
0x7C
read-write
n
0x0
0x0
POE0
Channel 0 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function
0
1
read-write
0
PWM channel 0 output to pin Disabled
#0
1
PWM channel 0 output to pin Enabled
#1
POE1
Channel 1 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function
1
1
read-write
0
PWM channel 1 output to pin Disabled
#0
1
PWM channel 1 output to pin Enabled
#1
POE2
Channel 2 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function
2
1
read-write
0
PWM channel 2 output to pin Disabled
#0
1
PWM channel 2 output to pin Enabled
#1
POE3
Channel 3 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function
3
1
read-write
0
PWM channel 3 output to pin Disabled
#0
1
PWM channel 3 output to pin Enabled
#1
PPR
PPR
PWM Prescaler Register
0x0
read-write
n
0x0
0x0
CP01
Clock Prescaler 0 (PWM-timer 0 / 1 for Group A and PWM-timer 4 / 5 for Group B)\nClock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-timer\n
0
8
read-write
CP23
Clock Prescaler 2 (PWM-timer2 / 3 for Group A and PWM-timer 6 / 7 for Group B)\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM-timer\n
8
8
read-write
DZI01
Dead-zone Interval for Pair of Channel 0 and Channel 1 (PWM0 and PWM1 Pair for PWM Group A, PWM4 and PWM5 Pair for PWM Group B)\nThese 8-bit determine the Dead-zone length.\n
16
8
read-write
DZI23
Dead-zone Interval for Pair of Channel2 and Channel3 (PWM2 and PWM3 Pair for PWM Group A, PWM6 and PWM7 Pair for PWM Group B)\nThese 8-bit determine the Dead-zone length.\n
24
8
read-write
SYNCBUSY0
SYNCBUSY0
PWM0 Synchronous Busy Status Register
0x88
read-only
n
0x0
0x0
S_BUSY
PWM Synchronous Busy\nWhen software writes CNR0/CMR0/PPR or switches PWM0 operation mode (PCR[3]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writing CNR0/CMR0/PPR or switching PWM0 operation mode (PCR[3]) to make sure previous setting has been updated completely.\nThis bit will be set when software writes CNR0/CMR0/PPR or switches PWM0 operation mode (PCR[3]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
SYNCBUSY1
SYNCBUSY1
PWM1 Synchronous Busy Status Register
0x8C
read-only
n
0x0
0x0
S_BUSY
PWM Synchronous Busy\nWhen software writes CNR1/CMR1/PPR or switches PWM1 operation mode (PCR[11]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writing CNR1/CMR1/PPR or switch PWM1 operation mode (PCR[11]) to make sure previous setting has been update completely.\nThis bit will be set when software writes CNR1/CMR1/PPR or switches PWM1 operation mode (PCR[11]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
SYNCBUSY2
SYNCBUSY2
PWM2 Synchronous Busy Status Register
0x90
read-only
n
0x0
0x0
S_BUSY
PWM Synchronous Busy\nWhen software writes CNR2/CMR2/PPR or switches PWM2 operation mode (PCR[19]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software need to check this busy status before writing CNR2/CMR2/PPR or switching PWM2 operation mode (PCR[19]) to make sure previous setting has been update completely.\nThis bit will be set when software writes CNR2/CMR2/PPR or switches PWM2 operation mode (PCR[19]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
SYNCBUSY3
SYNCBUSY3
PWM3 Synchronous Busy Status Register
0x94
read-only
n
0x0
0x0
S_BUSY
PWM Synchronous Busy\nWhen software writes CNR3/CMR3/PPR or switches PWM3 operation mode (PCR[27]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writing CNR3/CMR3/PPR or switching PWM3 operation mode (PCR[27]) to make sure previous setting has been update completely.\nThis bit will be set when software writes CNR3/CMR3/PPR or switches PWM3 operation mode (PCR[27]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
TCON
TCON
PWM Trigger Control for Channel 0~3
0x80
read-write
n
0x0
0x0
PWM0TEN
Channel 0 Center-aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type
0
1
read-write
0
PWM channel 0 trigger ADC function Disabled
#0
1
PWM channel 0 trigger ADC function Enabled
#1
PWM1TEN
Channel 1 Center-aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type
1
1
read-write
0
PWM channel 1 trigger ADC function Disabled
#0
1
PWM channel 1 trigger ADC function Enabled
#1
PWM2TEN
Channel 2 Center-aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type
2
1
read-write
0
PWM channel 2 trigger ADC function Disabled
#0
1
PWM channel 2 trigger ADC function Enabled
#1
PWM3TEN
Channel 3 Center-aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type
3
1
read-write
0
PWM channel 3 trigger ADC function Disabled
#0
1
PWM channel 3 trigger ADC function Enabled
#1
TSTATUS
TSTATUS
PWM Trigger Status Register
0x84
read-write
n
0x0
0x0
PWM0TF
Channel 0 Center-aligned Trigger Flag\nFor Center-aligned Operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM0TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
0
1
read-write
PWM1TF
Channel 1 Center-aligned Trigger Flag\nFor Center-aligned Operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM1TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
1
1
read-write
PWM2TF
Channel 2 Center-aligned Trigger Flag\nFor Center-aligned Operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM2TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
2
1
read-write
PWM3TF
Channel 3 Center-aligned Trigger Flag\nFor Center-aligned Operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM3TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
3
1
read-write
PWMB
PWM Register Map
PWM
0x0
0x0
0x48
registers
n
0x50
0x48
registers
n
CAPENR
CAPENR
PWM Capture Input 0~3 Enable Register
0x78
read-write
n
0x0
0x0
CINEN0
Channel 0 Capture Input Enable\n
0
1
read-write
0
PWM Channel 0 capture input path Disabled. The input of PWM channel 0 capture function is always regarded as 0
#0
1
PWM Channel 0 capture input path Enabled. The input of PWM channel 0 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM0
#1
CINEN1
Channel 1 Capture Input Enable\n
1
1
read-write
0
PWM Channel 1 capture input path Disabled. The input of PWM channel 1 capture function is always regarded as 0
#0
1
PWM Channel 1 capture input path Enabled. The input of PWM channel 1 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM1
#1
CINEN2
Channel 2 Capture Input Enable\n
2
1
read-write
0
PWM Channel 2 capture input path Disabled. The input of PWM channel 2 capture function is always regarded as 0
#0
1
PWM Channel 2 capture input path Enabled. The input of PWM channel 2 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM2
#1
CINEN3
Channel 3 Capture Input Enable\n
3
1
read-write
0
PWM Channel 3 capture input path Disabled. The input of PWM channel 3 capture function is always regarded as 0
#0
1
PWM Channel 3 capture input path Enabled. The input of PWM channel 3 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM3
#1
CCR0
CCR0
PWM Capture Control Register 0
0x50
read-write
n
0x0
0x0
CAPCH0EN
Channel 0 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 0 Interrupt.
3
1
read-write
0
Capture function on PWM group channel 0 Disabled
#0
1
Capture function on PWM group channel 0 Enabled
#1
CAPCH1EN
Channel 1 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 1 Interrupt.
19
1
read-write
0
Capture function on PWM group channel 1 Disabled
#0
1
Capture function on PWM group channel 1 Enabled
#1
CAPIF0
Channel 0 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0.
4
1
read-write
CAPIF1
Channel 1 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0.
20
1
read-write
CFLRI0
CFLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a falling transition, CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear this bit to0 if BCn bit is 1.
7
1
read-write
CFLRI1
CFLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a falling transition, CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0, and can write 1 to clear this bit to 0 if BCn bit is 1.
23
1
read-write
CFL_IE0
Channel 0 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 0 has falling transition, Capture will issue an Interrupt.
2
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CFL_IE1
Channel 1 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 1 has falling transition, Capture will issue an Interrupt.
18
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CRLRI0
CRLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a rising transition, CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear this bit to 0 if the BCn bit is 1.
6
1
read-write
CRLRI1
CRLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a rising transition, CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0, and can write 1 to clear this bit to0 if BCn bit is 1.
22
1
read-write
CRL_IE0
Channel 0 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 0 has rising transition, Capture will issue an Interrupt.
1
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
CRL_IE1
Channel 1 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 1 has rising transition, Capture will issue an Interrupt.
17
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
INV0
Channel 0 Inverter Enable\n
0
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
INV1
Channel 1 Inverter Enable\n
16
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
CCR2
CCR2
PWM Capture Control Register 2
0x54
read-write
n
0x0
0x0
CAPCH2EN
Channel 2 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 2 Interrupt.
3
1
read-write
0
Capture function on PWM group channel 2 Disabled
#0
1
Capture function on PWM group channel 2 Enabled
#1
CAPCH3EN
Channel 3 Capture Function Enable\nWhen Enabled, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 3 Interrupt.
19
1
read-write
0
Capture function on PWM group channel 3 Disabled
#0
1
Capture function on PWM group channel 3 Enabled
#1
CAPIF2
Channel 2 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0
4
1
read-write
CAPIF3
Channel 3 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0
20
1
read-write
CFLRI2
CFLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a falling transition, CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if BCn bit is 0, and can write 1 to clear this bit to 0 if the BCn bit is 1.
7
1
read-write
CFLRI3
CFLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a falling transition, CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear this bit to 0 if the BCn bit is 1.
23
1
read-write
CFL_IE2
Channel 2 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 2 has falling transition, Capture will issue an Interrupt.
2
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CFL_IE3
Channel 3 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 3 has falling transition, Capture will issue an Interrupt.
18
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CRLRI2
CRLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a rising transition, CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear this bit to 0 if the BCn bit is 1.
6
1
read-write
CRLRI3
CRLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a rising transition, CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nSoftware can write 0 to clear this bit to 0 if the BCn bit is 0, and can write 1 to clear this bit to 0 if the BCn bit is 1.
22
1
read-write
CRL_IE2
Channel 2 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 2 has rising transition, Capture will issue an Interrupt.
1
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
CRL_IE3
Channel 3 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects PWM group channel 3 has rising transition, Capture will issue an Interrupt.
17
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
INV2
Channel 2 Inverter Enable\n
0
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
INV3
Channel 3 Inverter Enable\n
16
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
CFLR0
CFLR0
PWM Capture Falling Latch Register (Channel 0)
0x5C
read-only
n
0x0
0x0
CFLRx
Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition.
0
16
read-only
CFLR1
CFLR1
PWM Capture Falling Latch Register (Channel 1)
0x64
read-write
n
0x0
0x0
CFLR2
CFLR2
PWM Capture Falling Latch Register (Channel 2)
0x6C
read-write
n
0x0
0x0
CFLR3
CFLR3
PWM Capture Falling Latch Register (Channel 3)
0x74
read-write
n
0x0
0x0
CMR0
CMR0
PWM Comparator Register 0
0x10
read-write
n
0x0
0x0
CMRx
PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in next PWM cycle.
0
16
read-write
CMR1
CMR1
PWM Comparator Register 1
0x1C
read-write
n
0x0
0x0
CMR2
CMR2
PWM Comparator Register 2
0x28
read-write
n
0x0
0x0
CMR3
CMR3
PWM Comparator Register 3
0x34
read-write
n
0x0
0x0
CNR0
CNR0
PWM Counter Register 0
0xC
read-write
n
0x0
0x0
CNRx
PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle.\nNote: When PWM operating at Center-aligned type, CNR value should be set between 0x0000 to 0xFFFE. If CNR equal to 0xFFFF, the PWM will work unpredictable.\nNote: When CNR value is set to 0, PWM output is always high.
0
16
read-write
CNR1
CNR1
PWM Counter Register 1
0x18
read-write
n
0x0
0x0
CNR2
CNR2
PWM Counter Register 2
0x24
read-write
n
0x0
0x0
CNR3
CNR3
PWM Counter Register 3
0x30
read-write
n
0x0
0x0
CRLR0
CRLR0
PWM Capture Rising Latch Register (Channel 0)
0x58
read-only
n
0x0
0x0
CRLRx
Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition.
0
16
read-only
CRLR1
CRLR1
PWM Capture Rising Latch Register (Channel 1)
0x60
read-write
n
0x0
0x0
CRLR2
CRLR2
PWM Capture Rising Latch Register (Channel 2)
0x68
read-write
n
0x0
0x0
CRLR3
CRLR3
PWM Capture Rising Latch Register (Channel 3)
0x70
read-write
n
0x0
0x0
CSR
CSR
PWM Clock Source Divider Select Register
0x4
read-write
n
0x0
0x0
CSR0
PWM Timer 0 Clock Source Divider Selection (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\nSelect clock source divider for PWM timer 0.\n(Table is the same as CSR3)
0
3
read-write
CSR1
PWM Timer 1 Clock Source Divider Selection (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\nSelect clock source divider for PWM timer 1.\n(Table is the same as CSR3)
4
3
read-write
CSR2
PWM Timer 2 Clock Source Divider Selection (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\nSelect clock source divider for PWM timer 2.\n(Table is the same as CSR3)
8
3
read-write
CSR3
PWM Timer 3 Clock Source Divider Selection (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n
12
3
read-write
PBCR
PBCR
PWM Backward Compatible Register
0x3C
read-write
n
0x0
0x0
BCn
PWM Backward Compatible Register\nRefer to the CCR0/CCR2 register bit 6, 7, 22, 23 description\nNote: It is recommended that this bit be set to 1 to prevent CFLRIx and CRLRIx from being cleared when writing CCR0/CCR2.
0
1
read-write
0
Configure write 0 to clear CFLRI0~3 and CRLRI0~3
#0
1
Configure write 1 to clear CFLRI0~3 and CRLRI0~3
#1
PCR
PCR
PWM Control Register
0x8
read-write
n
0x0
0x0
CH0EN
PWM-timer 0 Enable (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\n
0
1
read-write
0
The corresponding PWM-Timer stops running
#0
1
The corresponding PWM-Timer starts running
#1
CH0INV
PWM-timer 0 Output Inverter Enable (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\n
2
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH0MOD
PWM-timer 0 Auto-reload/One-shot Mode (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\nNote: If there is a transition at this bit, it will cause CNR0 and CMR0 be cleared.
3
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH0PINV
PWM-timer 0 Output Polar Inverse Enable (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\n
1
1
read-write
0
PWM0 output polar inverse Disabled
#0
1
PWM0 output polar inverse Enabled
#1
CH1EN
PWM-timer 1 Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n
8
1
read-write
0
Corresponding PWM-Timer Stopped
#0
1
Corresponding PWM-Timer Start Running
#1
CH1INV
PWM-timer 1 Output Inverter Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n
10
1
read-write
0
Inverter Disable
#0
1
Inverter Enable
#1
CH1MOD
PWM-timer 1 Auto-reload/One-shot Mode (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\nNote: If there is a transition at this bit, it will cause CNR1 and CMR1 be cleared.
11
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH1PINV
PWM-timer 1 Output Polar Inverse Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n
9
1
read-write
0
PWM1 output polar inverse Disabled
#0
1
PWM1 output polar inverse Enabled
#1
CH2EN
PWM-timer 2 Enable (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\n
16
1
read-write
0
Corresponding PWM-Timer Stopped
#0
1
Corresponding PWM-Timer Start Running
#1
CH2INV
PWM-timer 2 Output Inverter Enable (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\n
18
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH2MOD
PWM-timer 2 Auto-reload/One-shot Mode (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\nNote: If there is a transition at this bit, it will cause CNR2 and CMR2 be cleared.
19
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH2PINV
PWM-timer 2 Output Polar Inverse Enable (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\n
17
1
read-write
0
PWM2 output polar inverse Disabled
#0
1
PWM2 output polar inverse Enabled
#1
CH3EN
PWM-timer 3 Enable (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n
24
1
read-write
0
Corresponding PWM-Timer Stopped
#0
1
Corresponding PWM-Timer Start Running
#1
CH3INV
PWM-timer 3 Output Inverter Enable (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n
26
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH3MOD
PWM-timer 3 Auto-reload/One-shot Mode (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\nNote: If there is a transition at this bit, it will cause CNR3 and CMR3 be cleared.
27
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH3PINV
PWM-timer 3 Output Polar Inverse Enable (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n
25
1
read-write
0
PWM3 output polar inverse Disable
#0
1
PWM3 output polar inverse Enable
#1
DZEN01
Dead-zone 0 Generator Enable (PWM0 and PWM1 Pair for PWM Group A, PWM4 and PWM5 Pair for PWM Group B)\nNote: When Dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4 and PWM5 becomes a complementary pair for PWM group B.
4
1
read-write
0
Disabled
#0
1
Enabled
#1
DZEN23
Dead-zone 2 Generator Enable (PWM2 and PWM3 Pair for PWM Group A, PWM6 and PWM7 Pair for PWM Group B)\nNote: When Dead-zone generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6 and PWM7 becomes a complementary pair for PWM group B.
5
1
read-write
0
Disabled
#0
1
Enabled
#1
PWM01TYPE
PWM01 Aligned Type Selection Bit (PWM0 and PWM1 Pair for PWM Group A, PWM4 and PWM5 Pair for PWM Group B)\n
30
1
read-write
0
Edge-aligned type
#0
1
Center-aligned type
#1
PWM23TYPE
PWM23 Aligned Type Selection Bit (PWM2 and PWM3 Pair for PWM Group A, PWM6 and PWM7 Pair for PWM Group B)\n
31
1
read-write
0
Edge-aligned type
#0
1
Center-aligned type
#1
PDR0
PDR0
PWM Data Register 0
0x14
read-only
n
0x0
0x0
PDRx
PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter.
0
16
read-only
PDR1
PDR1
PWM Data Register 1
0x20
read-write
n
0x0
0x0
PDR2
PDR2
PWM Data Register 2
0x2C
read-write
n
0x0
0x0
PDR3
PDR3
PWM Data Register 3
0x38
read-write
n
0x0
0x0
PIER
PIER
PWM Interrupt Enable Register
0x40
read-write
n
0x0
0x0
INT01TYPE
PWM01 Interrupt Period Type Selection Bit (PWM0 and PWM1 Pair for PWM Group A, PWM4 and PWM5 Pair for PWM Group B)\nNote: This bit is effective when PWM in Center-aligned type only.
16
1
read-write
0
PWMIFn will be set if PWM counter underflow
#0
1
PWMIFn will be set if PWM counter matches CNRn register
#1
INT23TYPE
PWM23 Interrupt Period Type Selection Bit (PWM2 and PWM3 Pair for PWM Group A, PWM6 and PWM7 Pair for PWM Group B)\nNote: This bit is effective when PWM in Center-aligned type only.
17
1
read-write
0
PWMIFn will be set if PWM counter underflow
#0
1
PWMIFn will be set if PWM counter matches CNRn register
#1
PWMDIE0
PWM Channel 0 Duty Interrupt Enable\n
8
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
PWMDIE1
PWM Channel 1 Duty Interrupt Enable\n
9
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
PWMDIE2
PWM Channel 2 Duty Interrupt Enable\n
10
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
PWMDIE3
PWM Channel 3 Duty Interrupt Enable\n
11
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
PWMIE0
PWM Channel 0 Period Interrupt Enable\n
0
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
PWMIE1
PWM Channel 1 Period Interrupt Enable\n
1
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
PWMIE2
PWM Channel 2 Period Interrupt Enable\n
2
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
PWMIE3
PWM Channel 3 Period Interrupt Enable\n
3
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
PIIR
PIIR
PWM Interrupt Indication Register
0x44
read-write
n
0x0
0x0
PWMDIF0
PWM Channel 0 Duty Interrupt Flag\nFlag is set by hardware when channel 0 PWM counter down count and reaches CMR0, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in Edge-aligned type selection
8
1
read-write
PWMDIF1
PWM Channel 1 Duty Interrupt Flag\nFlag is set by hardware when channel 1 PWM counter down count and reaches CMR1, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in Edge-aligned type selection
9
1
read-write
PWMDIF2
PWM Channel 2 Duty Interrupt Flag\nFlag is set by hardware when channel 2 PWM counter down count and reaches CMR2, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in Edge-aligned type selection
10
1
read-write
PWMDIF3
PWM Channel 3 Duty Interrupt Flag\nFlag is set by hardware when channel 3 PWM counter down count and reaches CMR3, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in Edge-aligned type selection
11
1
read-write
PWMIF0
PWM Channel 0 Period Interrupt Status\nThis bit is set by hardware when PWM0 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register), software can write 1 to clear this bit to 0.
0
1
read-write
PWMIF1
PWM Channel 1 Period Interrupt Status\nThis bit is set by hardware when PWM1 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register), software can write 1 to clear this bit to 0.
1
1
read-write
PWMIF2
PWM Channel 2 Period Interrupt Status\nThis bit is set by hardware when PWM2 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register), software can write 1 to clear this bit to 0.
2
1
read-write
PWMIF3
PWM Channel 3 Period Interrupt Status\nThis bit is set by hardware when PWM3 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register), software can write 1 to clear this bit to 0.
3
1
read-write
POE
POE
PWM Output Enable for Channel 0~3
0x7C
read-write
n
0x0
0x0
POE0
Channel 0 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function
0
1
read-write
0
PWM channel 0 output to pin Disabled
#0
1
PWM channel 0 output to pin Enabled
#1
POE1
Channel 1 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function
1
1
read-write
0
PWM channel 1 output to pin Disabled
#0
1
PWM channel 1 output to pin Enabled
#1
POE2
Channel 2 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function
2
1
read-write
0
PWM channel 2 output to pin Disabled
#0
1
PWM channel 2 output to pin Enabled
#1
POE3
Channel 3 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function
3
1
read-write
0
PWM channel 3 output to pin Disabled
#0
1
PWM channel 3 output to pin Enabled
#1
PPR
PPR
PWM Prescaler Register
0x0
read-write
n
0x0
0x0
CP01
Clock Prescaler 0 (PWM-timer 0 / 1 for Group A and PWM-timer 4 / 5 for Group B)\nClock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-timer\n
0
8
read-write
CP23
Clock Prescaler 2 (PWM-timer2 / 3 for Group A and PWM-timer 6 / 7 for Group B)\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM-timer\n
8
8
read-write
DZI01
Dead-zone Interval for Pair of Channel 0 and Channel 1 (PWM0 and PWM1 Pair for PWM Group A, PWM4 and PWM5 Pair for PWM Group B)\nThese 8-bit determine the Dead-zone length.\n
16
8
read-write
DZI23
Dead-zone Interval for Pair of Channel2 and Channel3 (PWM2 and PWM3 Pair for PWM Group A, PWM6 and PWM7 Pair for PWM Group B)\nThese 8-bit determine the Dead-zone length.\n
24
8
read-write
SYNCBUSY0
SYNCBUSY0
PWM0 Synchronous Busy Status Register
0x88
read-only
n
0x0
0x0
S_BUSY
PWM Synchronous Busy\nWhen software writes CNR0/CMR0/PPR or switches PWM0 operation mode (PCR[3]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writing CNR0/CMR0/PPR or switching PWM0 operation mode (PCR[3]) to make sure previous setting has been updated completely.\nThis bit will be set when software writes CNR0/CMR0/PPR or switches PWM0 operation mode (PCR[3]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
SYNCBUSY1
SYNCBUSY1
PWM1 Synchronous Busy Status Register
0x8C
read-only
n
0x0
0x0
S_BUSY
PWM Synchronous Busy\nWhen software writes CNR1/CMR1/PPR or switches PWM1 operation mode (PCR[11]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writing CNR1/CMR1/PPR or switch PWM1 operation mode (PCR[11]) to make sure previous setting has been update completely.\nThis bit will be set when software writes CNR1/CMR1/PPR or switches PWM1 operation mode (PCR[11]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
SYNCBUSY2
SYNCBUSY2
PWM2 Synchronous Busy Status Register
0x90
read-only
n
0x0
0x0
S_BUSY
PWM Synchronous Busy\nWhen software writes CNR2/CMR2/PPR or switches PWM2 operation mode (PCR[19]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software need to check this busy status before writing CNR2/CMR2/PPR or switching PWM2 operation mode (PCR[19]) to make sure previous setting has been update completely.\nThis bit will be set when software writes CNR2/CMR2/PPR or switches PWM2 operation mode (PCR[19]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
SYNCBUSY3
SYNCBUSY3
PWM3 Synchronous Busy Status Register
0x94
read-only
n
0x0
0x0
S_BUSY
PWM Synchronous Busy\nWhen software writes CNR3/CMR3/PPR or switches PWM3 operation mode (PCR[27]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writing CNR3/CMR3/PPR or switching PWM3 operation mode (PCR[27]) to make sure previous setting has been update completely.\nThis bit will be set when software writes CNR3/CMR3/PPR or switches PWM3 operation mode (PCR[27]) and will be cleared by hardware automatically when PWM update these value completely.
0
1
read-only
TCON
TCON
PWM Trigger Control for Channel 0~3
0x80
read-write
n
0x0
0x0
PWM0TEN
Channel 0 Center-aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type
0
1
read-write
0
PWM channel 0 trigger ADC function Disabled
#0
1
PWM channel 0 trigger ADC function Enabled
#1
PWM1TEN
Channel 1 Center-aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type
1
1
read-write
0
PWM channel 1 trigger ADC function Disabled
#0
1
PWM channel 1 trigger ADC function Enabled
#1
PWM2TEN
Channel 2 Center-aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type
2
1
read-write
0
PWM channel 2 trigger ADC function Disabled
#0
1
PWM channel 2 trigger ADC function Enabled
#1
PWM3TEN
Channel 3 Center-aligned Trigger Enable Register\nPWM can trigger ADC to start conversion when PWM counter up count to CNR if this bit is set to 1.\nNote: This function is only supported when PWM operating at Center-aligned type
3
1
read-write
0
PWM channel 3 trigger ADC function Disabled
#0
1
PWM channel 3 trigger ADC function Enabled
#1
TSTATUS
TSTATUS
PWM Trigger Status Register
0x84
read-write
n
0x0
0x0
PWM0TF
Channel 0 Center-aligned Trigger Flag\nFor Center-aligned Operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM0TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
0
1
read-write
PWM1TF
Channel 1 Center-aligned Trigger Flag\nFor Center-aligned Operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM1TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
1
1
read-write
PWM2TF
Channel 2 Center-aligned Trigger Flag\nFor Center-aligned Operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM2TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
2
1
read-write
PWM3TF
Channel 3 Center-aligned Trigger Flag\nFor Center-aligned Operating mode, this bit is set to 1 by hardware when PWM counter up count to CNR if PWM3TEN bit is set to 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nSoftware can write 1 to clear this bit.
3
1
read-write
RTC
RTC Register Map
RTC
0x0
0x0
0x30
registers
n
AER
AER
RTC Access Enable Register
0x4
read-write
n
0x0
0x0
AER
RTC Register Access Enable Password (Write Only)\nWriting 0xA965 to this register will enable RTC registers read/write access and keep 1024 RTC clocks.
0
16
write-only
ENF
RTC Register Access Enable Flag (Read Only)\n
16
1
read-only
0
RTC register read/write access Disabled
#0
1
RTC register read/write access Enabled
#1
CAR
CAR
RTC Calendar Alarm Register
0x20
read-write
n
0x0
0x0
_10DAY
10-Day Calendar Digit of Alarm Setting (0~3)
4
2
read-write
_10MON
10-Month Calendar Digit of Alarm Setting (0~1)
12
1
read-write
_10YEAR
10-Year Calendar Digit of Alarm Setting (0~9)
20
4
read-write
_1DAY
1-Day Calendar Digit of Alarm Setting (0~9)
0
4
read-write
_1MON
1-Month Calendar Digit of Alarm Setting (0~9)
8
4
read-write
_1YEAR
1-Year Calendar Digit of Alarm Setting (0~9)
16
4
read-write
CLR
CLR
RTC Calendar Loading Register
0x10
-1
read-write
n
0x0
0x0
_10DAY
10-Day Calendar Digit (0~3)
4
2
read-write
_10MON
10-Month Calendar Digit (0~1)
12
1
read-write
_10YEAR
10-Year Calendar Digit (0~9)
20
4
read-write
_1DAY
1-Day Calendar Digit (0~9)
0
4
read-write
_1MON
1-Month Calendar Digit (0~9)
8
4
read-write
_1YEAR
1-Year Calendar Digit (0~9)
16
4
read-write
DWR
DWR
RTC Day of the Week Register
0x18
-1
read-write
n
0x0
0x0
DWR
Day of the Week Register \n
0
3
read-write
FCR
FCR
RTC Frequency Compensation Register
0x8
-1
read-write
n
0x0
0x0
FRACTION
Fraction Part\nNote: Digit in FCR must be expressed as hexadecimal number. Refer to 6.11.4.4 for the examples.
0
6
read-write
INTEGER
Integer Part\n
8
4
read-write
INIR
INIR
RTC Initiation Register
0x0
read-write
n
0x0
0x0
INIR
RTC Initiation\nRead return current RTC active status\nA write of 0xa5eb1357 to make RTC leaving reset state.\nWhen RTC block is powered on, RTC is in reset state. User has to write a number 0x a5eb1357 to INIR register to make RTC leave reset state. Once the INIR is written as 0xa5eb1357, the RTC will be in normal active state permanently.
0
32
read-write
0
RTC is in reset state
0
1
RTC is in normal active state
1
LIR
LIR
RTC Leap Year Indication Register
0x24
read-only
n
0x0
0x0
LIR
Leap Year Indication Register (Read Only)\nThis bit indicates RTC current year is a leap year or not.\n
0
1
read-only
0
This year is not a leap year
#0
1
This year is a leap year
#1
RIER
RIER
RTC Interrupt Enable Register
0x28
read-write
n
0x0
0x0
AIER
Alarm Interrupt Enable\nThis bit is used to enable/disable RTC Alarm Interrupt, and generate an interrupt signal if AIF (RIIR [0] RTC Alarm Interrupt Flag) is set to 1.\nThis bit will also trigger a wake-up event while system runs in Idle/Power-Down mode and RTC Alarm Interrupt signal generated.
0
1
read-write
0
RTC Alarm Interrupt Disabled
#0
1
RTC Alarm Interrupt Enabled
#1
TIER
Time Tick Interrupt Enable\nThis bit is used to enable/disable RTC Time Tick Interrupt, and generate an interrupt signal if TIF (RIIR [1] RTC Time Tick Interrupt Flag) is set to 1.\nThis bit will also trigger a wake-up event while system runs in Idle/Power-Down mode and RTC Time Tick Interrupt signal generated.
1
1
read-write
0
RTC Time Tick Interrupt Disabled
#0
1
RTC Time Tick Interrupt Enabled
#1
RIIR
RIIR
RTC Interrupt Indication Register
0x2C
read-write
n
0x0
0x0
AIF
RTC Alarm Interrupt Flag\nWhen RTC real time counters TLR and CLR reach the alarm time setting registers TAR and CAR, this bit will be set to 1 and an interrupt signal will be generated if AIER bit is set to 1. \nSoftware can clear this bit by writing 1 to it.
0
1
read-write
TIF
RTC Time Tick Interrupt Flag\nWhen RTC Time Tick time-out happened, this bit will be set to 1 and an interrupt signal will be generated if TIER bit is set to 1.\nSoftware can clear this bit by writing 1 to it.
1
1
read-write
TAR
TAR
RTC Time Alarm Register
0x1C
read-write
n
0x0
0x0
_10HR
10-Hour Time Digit of Alarm Setting (0~3)
20
2
read-write
_10MIN
10-Min Time Digit of Alarm Setting (0~5)
12
3
read-write
_10SEC
10-Sec Time Digit of Alarm Setting (0~5)
4
3
read-write
_1HR
1-Hour Time Digit of Alarm Setting (0~9)
16
4
read-write
_1MIN
1-Min Time Digit of Alarm Setting (0~9)
8
4
read-write
_1SEC
1-Sec Time Digit of Alarm Setting (0~9)
0
4
read-write
TLR
TLR
RTC Time Loading Register
0xC
read-write
n
0x0
0x0
_10HR
10-Hour Time Digit (0~3)
20
2
read-write
_10MIN
10-Min Time Digit (0~5)
12
3
read-write
_10SEC
10-Sec Time Digit (0~5)
4
3
read-write
_1HR
1-Hour Time Digit (0~9)
16
4
read-write
_1MIN
1-Min Time Digit (0~9)
8
4
read-write
_1SEC
1-Sec Time Digit (0~9)
0
4
read-write
TSSR
TSSR
RTC Time Scale Selection Register
0x14
-1
read-write
n
0x0
0x0
_24H_12H
24-hour / 12-hour Time Scale Selection\n
0
1
read-write
0
Selected as 12-hour time scale with AM and PM indication (high bit of 10HR field in TLR and TAR)
#0
1
Selected as 24-hour time scale
#1
TTR
TTR
RTC Time Tick Register
0x30
read-write
n
0x0
0x0
TTR
Time Tick Register\n
0
3
read-write
SC0
SC Register Map
SC
0x0
0x0
0x30
registers
n
0x38
0x8
registers
n
SC_ALTCTL
SC_ALTCTL
SC Alternate Control State Register
0x8
read-write
n
0x0
0x0
ACT_EN
Activation Sequence Generator Enable
This bit enables SC controller to initiate the card by activation sequence
Note1: When the activation sequence completed, this bit will be cleared automatically and the SC_ISR [INIT_IS] will be set to 1 .
Note2: This field will be cleared when software set SC_ALTCTL[TX_RST] or SC_ALTCTL[RX_RST] to 1. So don't fill this bit, TX_RST, and RX_RST at the same time.
Note3: If SC_CTL[SC_CEN] not enabled, this field cannot be programmed.
3
1
read-write
0
No effect
#0
1
Activation sequence generator Enabled
#1
DACT_EN
Deactivation Sequence Generator Enable
This bit enables SC controller to initiate the card by deactivation sequence
Note1: When the deactivation sequence completed, this bit will be cleared automatically and the SC_ISR [INIT_IS] will be set to 1 .
Note2: This field will be cleared when software set SC_ALTCTL[TX_RST] or SC_ALTCTL[RX_RST] to 1. So don't fill this bit, TX_RST, and RX_RST at the same time.
Note3: If SC_CTL [SC_CEN] not enabled, this field cannot be programmed.
2
1
read-write
0
No effect
#0
1
Deactivation sequence generator Enabled
#1
INIT_SEL
Initial Timing Selection\n
8
2
read-write
RX_BGT_EN
Check Receiver Block Guard Time Function Enable\n
12
1
read-write
0
Check receiver block guard time function Disabled
#0
1
Check receiver block guard time function Enabled
#1
RX_RST
Rx Software Reset\nWhen RX_RST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared and it needs at least 3 SC peripheral clock cycles.
1
1
read-write
0
No effect
#0
1
Reset the Rx internal state machine and pointers
#1
TMR0_ATV
Internal Timer0 Active State (Read Only)\nThis bit indicates the Timer0 counter status.\n
13
1
read-only
0
Timer0 is not active
#0
1
Timer0 is active
#1
TMR0_SEN
Internal Timer0 Start Enable
This bit enables Timer0 to start counting. Software can fill 0 to stop it and set 1 to reload and count.
Note3: This field will be cleared when software set SC_ALTCTL[TX_RST] or SC_ALTCTL[RX_RST] to 1. So don't fill this bit, TX_RST and RX_RST at the same time.
Note4: If SC_CTL [SC_CEN] not enabled, this field cannot be programmed.
5
1
read-write
0
Stops counting
#0
1
Starts counting
#1
TMR1_ATV
Internal Timer1 Active State (Read Only)\nThis bit indicates the Timer1 counter status.\n
14
1
read-only
0
Timer1 is not active
#0
1
Timer1 is active
#1
TMR1_SEN
Internal Timer1 Start Enable
This bit enables Timer1 to start counting. Software can fill 0 to stop it and set 1 to reload and count.
Note3: This field will be cleared when software set SC_ALTCTL[TX_RST] or SC_ALTCTL[RX_RST] to 1, so don't fill this bit, TX_RST, and RX_RST at the same time.
Note4: If SC_CTL [SC_CEN] not enabled, this field cannot be programmed.
6
1
read-write
0
Stops counting
#0
1
Starts counting
#1
TMR2_ATV
Internal Timer2 Active State (Read Only)\nThis bit indicates the Timer2 counter status.\n
15
1
read-only
0
Timer2 is not active
#0
1
Timer2 is active
#1
TMR2_SEN
Internal Timer2 Start Enable
This bit enables Timer2 to start counting. Software can fill 0 to stop it and set 1 to reload and count.
Note3: This field will be cleared when software set SC_ALTCTL[TX_RST] or SC_ALTCTL [RX_RST] to 1. So don't fill this bit, TX_RST, and RX_RST at the same time.
Note4: If SC_CTL [SC_CEN] not enabled, this field cannot be programmed.
7
1
read-write
0
Stops counting
#0
1
Starts counting
#1
TX_RST
TX Software Reset\nWhen TX_RST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared and it needs at least 3 SC peripheral clock cycles.
0
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
WARST_EN
Warm Reset Sequence Generator Enable
This bit enables SC controller to initiate the card by warm reset sequence
Note1: When the warm reset sequence completed, this bit will be cleared automatically and the SC_ISR[INIT_IS] will be set to 1 .
Note2: This field will be cleared when software set SC_ALTCTL[TX_RST] or SC_ALTCTL[RX_RST] to 1. So don't fill this bit, TX_RST, and RX_RST at the same time.
Note3: If SC_CTL[SC_CEN] not enabled, this field cannot be programmed.
4
1
read-write
0
No effect
#0
1
Warm reset sequence generator Enabled
#1
SC_CTL
SC_CTL
SC Control Register
0x4
read-write
n
0x0
0x0
AUTO_CON_EN
Auto Convention Enable\n
3
1
read-write
0
Auto-convention Disabled
#0
1
Auto-convention Enabled
#1
BGT
Block Guard Time (BGT)\nIn TX mode, hardware will auto hold off first character until BGT has elapsed regardless of the TX data.\n\nIn RX mode, software can enable SC_ALTCTL [RX_BGT_EN] to detect the first coming character timing. If the incoming data timing less than BGT, an interrupt will be generated.\n\nNote: The real block guard time is BGT + 1.
8
5
read-write
CD_DEB_SEL
Card Detect De-bounce Select Register\n
24
2
read-write
CON_SEL
Convention Selection\nNote: If AUTO_CON_EN enabled, this fields must be ignored.
4
2
read-write
0
Direct convention
#00
1
Reserved
#01
2
Reserved
#10
3
Inverse convention
#11
DIS_RX
RX Transition Disable\nNote: If AUTO_CON_EN enabled, this fields must be ignored.
1
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
DIS_TX
TX Transition Disable\n
2
1
read-write
0
Transceiver Enabled
#0
1
Transceiver Disabled
#1
RX_ERETRY
RX Error Retry Count Register\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred.\nNote1: The real maximum retry number is RX_ERETRY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when RX_ERETRY_EN enabled. The change flow is to disable RX_ETRTRY_EN first and then fill new retry value.
16
3
read-write
RX_ERETRY_EN
RX Error Retry Enable Register\nThis bit enables receiver retry function when parity error has occurred.\nNote: Software must fill RX_ERETRY value before enabling this bit.
19
1
read-write
0
RX error retry function Disabled
#0
1
RX error retry function Enabled
#1
RX_FTRI_LEV
Rx Buffer Trigger Level \n
6
2
read-write
SC_CEN
SC Engine Enable
Setting this bit to 1 will enable SC operation. If this bit is cleared, SC will force all transition to IDLE state.
0
1
read-write
SLEN
Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2.
15
1
read-write
0
The stop bit length is 2 ETU
#0
1
The stop bit length is 1 ETU
#1
TMR_SEL
Timer Selection \n
13
2
read-write
TX_ERETRY
TX Error Retry Count Register\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TX_ERETRY + 1, 8 is the maximum retry number.\nNote2: This field cannot be changed when TX_ERETRY_EN enabled. The change flow is to disable TX_ETRTRY_EN first and then fill new retry value.
20
3
read-write
TX_ERETRY_EN
TX Error Retry Enable Register\nThis bit enables transmitter retry function when parity error has occurred.\nNote: Software must fill TX_ERETRY value before enabling this bit.
23
1
read-write
0
TX error retry function Disabled
#0
1
TX error retry function Enabled
#1
SC_EGTR
SC_EGTR
SC Extend Guard Time Register
0xC
read-write
n
0x0
0x0
EGT
Extended Guard Time\nThis field indicates the extended guard time value.\n\nNote: The counter is ETU based and the real extended guard time is EGT.
0
8
read-write
SC_ETUCR
SC_ETUCR
SC ETU Control Register
0x14
-1
read-write
n
0x0
0x0
COMPEN_EN
Compensation Mode Enable\nThis bit enables clock compensation function. When this bit enabled, hardware will alternate between n-1 clock cycles and n clock cycles, where n is the value to be written into the ETU_RDIV register.\n
15
1
read-write
0
Compensation function Disabled
#0
1
Compensation function Enabled
#1
ETU_RDIV
ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETU_RDIV + 1.\nNote1: Software can configure this field, but this field must be greater than 0x04.\nNote2: Software can configure this field, but if the error rate is equal to 2%, this field must be greater than 0x040.
0
12
read-write
SC_IER
SC_IER
SC Interrupt Enable Register
0x18
read-write
n
0x0
0x0
ACON_ERR_IE
Auto Convention Error Interrupt Enable \nThis field is used for auto-convention error interrupt enable.\n
10
1
read-write
0
Auto-convention error interrupt Disabled
#0
1
Auto-convention error interrupt Enabled
#1
BGT_IE
Block Guard Time Interrupt Enable\nThis field is used for block guard time interrupt enable.\n
6
1
read-write
0
Block guard time Disabled
#0
1
Block guard time Enabled
#1
CD_IE
Card Detect Interrupt Enable\nThis field is used for card detect interrupt enable. The card detect status register is SC_PINCSR[CD_INS_F] and SC_PINCSR[CD_REM_F].\n
7
1
read-write
0
Card detect interrupt Disabled
#0
1
Card detect interrupt Enabled
#1
INIT_IE
Initial End Interrupt Enable\nThis field is used for activation (SC_ALTCTL [ACT_EN]), deactivation (SC_ALTCTL [DACT_EN]) and warm reset (SC_ALTCTL [WARST_EN]) sequence interrupt enable.\n
8
1
read-write
0
Initial end interrupt Disabled
#0
1
Initial end interrupt Enabled
#1
RDA_IE
Receive Data Reach Interrupt Enable\nThis field is used for received data reaching trigger level (SC_CTL [RX_FTRI_LEV]) interrupt enable.\n
0
1
read-write
0
Receive data reach trigger level interrupt Disabled
#0
1
Receive data reach trigger level interrupt Enabled
#1
RTMR_IE
Receiver Buffer Time-out Interrupt Enable \nThis field is used for receiver buffer time-out interrupt enable.\n
9
1
read-write
0
Receiver buffer time-out interrupt Disabled
#0
1
Receiver buffer time-out interrupt Enabled
#1
TBE_IE
Transmit Buffer Empty Interrupt Enable\nThis field is used for transmit buffer empty interrupt enable.\n
1
1
read-write
0
Transmit buffer empty interrupt Disabled
#0
1
Transmit buffer empty interrupt Enabled
#1
TERR_IE
Transfer Error Interrupt Enable\nThis field is used for transfer error interrupt enable. The transfer error states is at SC_TRSR register which includes receiver break error (RX_EBR_F), frame error (RX_EFR_F), parity error (RX_EPA_F), receiver buffer overflow error (RX_OVER_F), transmit buffer overflow error (TX_OVER_F), receiver retry over limit error (RX_OVER_REERR) and transmitter retry over limit error (TX_OVER_REERR).\n
2
1
read-write
0
Transfer error interrupt Disabled
#0
1
Transfer error interrupt Enabled
#1
TMR0_IE
Timer0 Interrupt Enable\nThis field is used for TMR0 interrupt enable.\n
3
1
read-write
0
Timer0 interrupt Disabled
#0
1
Timer0 interrupt Enabled
#1
TMR1_IE
Timer1 Interrupt Enable\nThis field is used for TMR1 interrupt enable.\n
4
1
read-write
0
Timer1 interrupt Disabled
#0
1
Timer1 interrupt Enabled
#1
TMR2_IE
Timer2 Interrupt Enable\nThis field is used for TMR2 interrupt enable.\n
5
1
read-write
0
Timer2 interrupt Disabled
#0
1
Timer2 interrupt Enabled
#1
SC_ISR
SC_ISR
SC Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
ACON_ERR_IS
Auto Convention Error Interrupt Status Flag (Read Only)
This field indicates auto convention sequence error. If the received TS at ATR state is not 0x3B or 0x3F, this bit will be set.
Note: This bit is read only, but can be cleared by writing 1 to it.
10
1
read-only
BGT_IS
Block Guard Time Interrupt Status Flag (Read Only)
This field is used for block guard time interrupt status flag.
Note1: This bit is valid when SC_ALTCTL[RX_BGT_EN] is enabled.
Note2: This bit is read only, but it can be cleared by writing 1 to it.
6
1
read-only
CD_IS
Card Detect Interrupt Status Flag (Read Only)\nNote: If software wants to clear this field, software must clear SC_PINCSR [CD_INS_F] and SC_PINCSR [CD_REM_F].
7
1
read-only
INIT_IS
Initial End Interrupt Status Flag (Read Only)
This field is used for activation (SC_ALTCTL [ACT_EN]), deactivation (SC_ALTCTL [DACT_EN]) and warm reset (SC_ALTCTL [WARST_EN]) sequence interrupt status flag.
Note: This bit is read only, but it can be cleared by writing 1 to it.
8
1
read-only
RDA_IS
Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level (SC_CTL[RX_FTRI_LEV]) interrupt status flag.\nNote: This field is the status flag of received data reaching SC_CTL [RX_FTRI_LEV]. If software reads data from SC_RBR and receiver pointer is less than SC_CTL [RX_FTRI_LEV], this bit will be cleared automatically.
0
1
read-only
RTMR_IS
Receiver Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit, software must read the receiver buffer remaining data by reading SC_RBR register,
9
1
read-only
TBE_IS
Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This field is the status flag of transmit buffer empty state. If software wants to clear this bit, software must write data to SC_THR register and then this bit will be cleared automatically.
1
1
read-only
TERR_IS
Transfer Error Interrupt Status Flag (Read Only)
This field is used for transfer error interrupt status flag. The transfer error status is at the SC_TRSR register which includes receiver break error (RX_EBR_F), frame error (RX_EFR_F), parity error (RX_EPA_F) and receiver buffer overflow error (RX_OVER_F), transmit buffer overflow error (TX_OVER_F), receiver retry over limit error (RX_OVER_REERR) and transmitter retry over limit error (TX_OVER_REERR).
Note: This field is the status flag of SC_TRSR[RX_EBR_F], SC_TRSR[RX_EFR_F], SC_TRSR[RX_EPA_F], SC_TRSR[RX_OVER_F], SC_TRSR[TX_OVER_F], SC_TRSR[RX_OVER_REERR] or SC_TRSR[TX_OVER_REERR]. So if software wants to clear this bit, software must write 1 to each field.
2
1
read-only
TMR0_IS
Timer0 Interrupt Status Flag (Read Only)
This field is used for TMR0 interrupt status flag.
Note: This bit is read only, but it can be cleared by writing 1 to it.
3
1
read-only
TMR1_IS
Timer1 Interrupt Status Flag (Read Only)
This field is used for TMR1 interrupt status flag.
Note: This bit is read only, but it can be cleared by writing 1 to it.
4
1
read-only
TMR2_IS
Timer2 Interrupt Status Flag (Read Only)
This field is used for TMR2 interrupt status flag.
Note: This bit is read only, but it can be cleared by writing 1 to it.
5
1
read-only
SC_PINCSR
SC_PINCSR
SC Pin Control State Register
0x24
read-write
n
0x0
0x0
ADAC_CD_EN
Auto Deactivation When Card Removal\nNote: When the card is removed, hardware will stop any process and then do deactivation sequence (if this bit be setting). If this process completes. Hardware will generate an initial end interrupt to CPU.
7
1
read-write
0
Auto deactivation Disabled when hardware detected the card removal
#0
1
Auto deactivation Enabled when hardware detected the card removal
#1
CD_INS_F
Card Detect Insert Status Of SC_CD Pin (Read Only)
This bit is set whenever card has been inserted.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: The card detect engine will start after SC_CTL[SC_CEN] set.
3
1
read-only
0
No effect
#0
1
Card insert
#1
CD_LEV
Card Detect Level\n\nNote: Software must select card detect level before Smart Card engine is enabled.
10
1
read-write
0
When hardware detects the card detect pin from high to low, it indicates a card is detected
#0
1
When hardware detects the card detect pin from low to high, it indicates a card is detected
#1
CD_PIN_ST
Card Detect Status Of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD\n
4
1
read-only
0
The SC_CD pin state at low
#0
1
The SC_CD pin state at high
#1
CD_REM_F
Card Detect Removal Status Of SC_CD Pin (Read Only)
This bit is set whenever a card has been removed.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: Card detect engine will start after SC_CTL[SC_CEN] set.
2
1
read-only
0
No effect
#0
1
Card removed
#1
CLK_KEEP
SC Clock Enable\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
6
1
read-write
0
SC clock generation Disabled
#0
1
SC clock always keeps free running
#1
POW_EN
SC_POW_EN Pin Signal\n
0
1
read-write
0
SC_PWR pin status is low
#0
1
SC_PWR pin status is high
#1
POW_INV
SC_PWR Pin Inverse\n
11
1
read-write
SC_DATA_I_ST
SC Data Pin Status (Read Only)\nThis bit is the pin status of SC_DAT\n
16
1
read-only
0
The SC_DAT pin is low
#0
1
The SC_DAT pin is high
#1
SC_DATA_O
SC Data Output Pin \nThis bit is the pin status of SC_DAT but user can drive SC_DAT pin to high or low by setting this bit.\nWrite this field to drive SC_DAT pin.\nNote: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when SC is in these modes.
9
1
read-write
0
Drive SC_DAT pin to low.\nSC_DAT pin status is low
#0
1
Drive SC_DAT pin to high.\nSC_DAT pin status is high
#1
SC_OEN_ST
SC Data Output Enable Pin Status (Read Only)\nThis bit is the output enable status of the SC_DAT pin.\n
8
1
read-only
0
The SC_DAT pin state is output
#0
1
The SC_DAT pin state is not output
#1
SC_RST
SC_RST Pin Signal\nThis bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.\nWrite this field to drive SC_RST pin.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
1
1
read-write
0
Drive SC_RST pin to low.\nSC_RST pin status is low
#0
1
Drive SC_RST pin to high.\nSC_RST pin status is high
#1
SC_RBR
SC_RBR
SC Receiving Buffer Register.
0x0
read-only
n
0x0
0x0
RBR
Receive Buffer Register\nBy reading this register, the SC will return an 8-bit received data.
0
8
read-only
SC_RFTMR
SC_RFTMR
SC Receiver Buffer Time-out Register
0x10
read-write
n
0x0
0x0
RFTM
SC Receiver Buffer Time-out Register (ETU Based)
Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5
Note2: Filling all 0 to this field indicates to disable this function.
0
9
read-write
SC_TDRA
SC_TDRA
SC Timer Current Data Register A
0x38
-1
read-only
n
0x0
0x0
TDR0
Timer0 Current Data Register (Read Only)\nThis field indicates the current count values of timer0.
0
24
read-only
SC_TDRB
SC_TDRB
SC Timer Current Data Register B
0x3C
-1
read-only
n
0x0
0x0
TDR1
Timer1 Current Data Register (Read Only)\nThis field indicates the current count values of timer1.
0
8
read-only
TDR2
Timer2 Current Data Register (Read Only)\nThis field indicates the current count values of timer2.
8
8
read-only
SC_THR
SC_THR
SC Transmit Holding Register
SC_RBR
0x0
write-only
n
0x0
0x0
THR
Transmit Holding Register\nBy writing to this register, the SC will send out an 8-bit data.\nNote: If SC_CTL[SC_CEN] not enabled, this register cannot be programmed.
0
8
write-only
SC_TMR0
SC_TMR0
SC Internal Timer Control Register 0
0x28
read-write
n
0x0
0x0
CNT
Timer 0 Counter Value Register (ETU Based)\nThis field indicates the internal timer operation values.
0
24
read-write
MODE
Timer 0 Operation Mode Selection\n
24
4
read-write
SC_TMR1
SC_TMR1
SC Internal Timer Control Register 1
0x2C
read-write
n
0x0
0x0
CNT
Timer 1 Counter Value Register (ETU Based)\nThis field indicates the internal timer operation values.
0
8
read-write
MODE
Timer 1 Operation Mode Selection\n
24
4
read-write
SC_TMR2
SC_TMR2
SC Internal Timer Control Register 2
0x30
read-write
n
0x0
0x0
CNT
Timer 2 Counter Value Register (ETU Based)\nThis field indicates the internal timer operation values.
0
8
read-write
MODE
Timer 2 Operation Mode Selection\n
24
4
read-write
SC_TRSR
SC_TRSR
SC Transfer Status Register
0x20
-1
read-write
n
0x0
0x0
RX_ATV
Receiver In Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished.
23
1
read-only
RX_EBR_F
Receiver Break Error Status Flag (Read Only)
This bit is set to 1 whenever the received data input (RX) held in the spacing state (logic 0 ) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). .
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting SC_CTL[RX_ERETRY_EN] register, hardware will not set this flag.
6
1
read-only
RX_EFR_F
Receiver Frame Error Status Flag (Read Only)
This bit is set to 1 whenever the received character does not have a valid STOP bit (that is, the STOP bit following the last data bit or parity bit is detected as logic 0).
Note1: This bit is read only, but can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting SC_CTL[RX_ERETRY_EN] register, hardware will not set this flag.
5
1
read-only
RX_EMPTY_F
Receiver Buffer Empty Status Flag(Read Only)
This bit indicates RX buffer empty or not.
When the last byte of RX buffer has been read by CPU, hardware set this bit to 1 . It will be cleared by hardware when SC receives any new data.
1
1
read-only
RX_EPA_F
Receiver Parity Error Status Flag (Read Only)
This bit is set to 1 whenever the received character does not have a valid parity bit .
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting SC_CTL[RX_ERETRY_EN] register, hardware will not set this flag.
4
1
read-only
RX_FULL_F
Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
2
1
read-only
RX_OVER_F
RX Overflow Error Status Flag (Read Only)
This bit is set when RX buffer overflow.
If the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.
Note: This bit is read only, but it can be cleared by writing 1 to it.
0
1
read-only
RX_OVER_REERR
Receiver Over Retry Error (Read Only)
This bit is set by hardware when RX transfer error retry over retry number limit.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU enables receiver retries function by setting SC_CTL [RX_ERETRY_EN] register, the RX_EPA_F flag will be ignored (hardware will not set RX_EPA_F).
22
1
read-only
RX_POINT_F
Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device, RX_POINT_F increases one. When one byte of RX buffer is read by CPU, RX_POINT_F decreases one.
16
2
read-only
RX_REERR
Receiver Retry Error (Read Only)
This bit is set by hardware when RX has any error and retries transfer.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2 This bit is a flag and cannot generate any interrupt to CPU.
Note3: If CPU enables receiver retry function by setting SC_CTL [RX_ERETRY_EN] register, the RX_EPA_F flag will be ignored (hardware will not set RX_EPA_F).
21
1
read-only
TX_ATV
Transmit In Active Status Flag (Read Only)\nThis bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has not been transmitted.\nThis bit is cleared automatically when TX transfer is finished or the last byte transmission has completed.
31
1
read-only
TX_EMPTY_F
Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into SC_THR (TX buffer not empty).
9
1
read-only
TX_FULL_F
Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates TX buffer full or not.\nThis bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
10
1
read-only
TX_OVER_F
TX Overflow Error Interrupt Status Flag (Read Only)
If TX buffer is full, an additional write to SC_THR will cause this bit be set to 1 by hardware.
Note: This bit is read only, but it can be cleared by writing 1 to it.
8
1
read-only
TX_OVER_REERR
Transmitter Over Retry Error (Read Only)
This bit is set by hardware when transmitter re-transmits over retry number limitation.
Note: This bit is read only, but it can be cleared by writing 1 to it.
30
1
read-only
TX_POINT_F
Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_THR, TX_POINT_F increases one. When one byte of TX Buffer is transferred to transmitter shift register, TX_POINT_F decreases one.
24
2
read-only
TX_REERR
Transmitter Retry Error (Read Only)
This bit is set by hardware when transmitter re-transmits.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: This bit is a flag and cannot generate any interrupt to CPU.
29
1
read-only
SC1
SC Register Map
SC
0x0
0x0
0x30
registers
n
0x38
0x8
registers
n
SC_ALTCTL
SC_ALTCTL
SC Alternate Control State Register
0x8
read-write
n
0x0
0x0
ACT_EN
Activation Sequence Generator Enable
This bit enables SC controller to initiate the card by activation sequence
Note1: When the activation sequence completed, this bit will be cleared automatically and the SC_ISR [INIT_IS] will be set to 1 .
Note2: This field will be cleared when software set SC_ALTCTL[TX_RST] or SC_ALTCTL[RX_RST] to 1. So don't fill this bit, TX_RST, and RX_RST at the same time.
Note3: If SC_CTL[SC_CEN] not enabled, this field cannot be programmed.
3
1
read-write
0
No effect
#0
1
Activation sequence generator Enabled
#1
DACT_EN
Deactivation Sequence Generator Enable
This bit enables SC controller to initiate the card by deactivation sequence
Note1: When the deactivation sequence completed, this bit will be cleared automatically and the SC_ISR [INIT_IS] will be set to 1 .
Note2: This field will be cleared when software set SC_ALTCTL[TX_RST] or SC_ALTCTL[RX_RST] to 1. So don't fill this bit, TX_RST, and RX_RST at the same time.
Note3: If SC_CTL [SC_CEN] not enabled, this field cannot be programmed.
2
1
read-write
0
No effect
#0
1
Deactivation sequence generator Enabled
#1
INIT_SEL
Initial Timing Selection\n
8
2
read-write
RX_BGT_EN
Check Receiver Block Guard Time Function Enable\n
12
1
read-write
0
Check receiver block guard time function Disabled
#0
1
Check receiver block guard time function Enabled
#1
RX_RST
Rx Software Reset\nWhen RX_RST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared and it needs at least 3 SC peripheral clock cycles.
1
1
read-write
0
No effect
#0
1
Reset the Rx internal state machine and pointers
#1
TMR0_ATV
Internal Timer0 Active State (Read Only)\nThis bit indicates the Timer0 counter status.\n
13
1
read-only
0
Timer0 is not active
#0
1
Timer0 is active
#1
TMR0_SEN
Internal Timer0 Start Enable
This bit enables Timer0 to start counting. Software can fill 0 to stop it and set 1 to reload and count.
Note3: This field will be cleared when software set SC_ALTCTL[TX_RST] or SC_ALTCTL[RX_RST] to 1. So don't fill this bit, TX_RST and RX_RST at the same time.
Note4: If SC_CTL [SC_CEN] not enabled, this field cannot be programmed.
5
1
read-write
0
Stops counting
#0
1
Starts counting
#1
TMR1_ATV
Internal Timer1 Active State (Read Only)\nThis bit indicates the Timer1 counter status.\n
14
1
read-only
0
Timer1 is not active
#0
1
Timer1 is active
#1
TMR1_SEN
Internal Timer1 Start Enable
This bit enables Timer1 to start counting. Software can fill 0 to stop it and set 1 to reload and count.
Note3: This field will be cleared when software set SC_ALTCTL[TX_RST] or SC_ALTCTL[RX_RST] to 1, so don't fill this bit, TX_RST, and RX_RST at the same time.
Note4: If SC_CTL [SC_CEN] not enabled, this field cannot be programmed.
6
1
read-write
0
Stops counting
#0
1
Starts counting
#1
TMR2_ATV
Internal Timer2 Active State (Read Only)\nThis bit indicates the Timer2 counter status.\n
15
1
read-only
0
Timer2 is not active
#0
1
Timer2 is active
#1
TMR2_SEN
Internal Timer2 Start Enable
This bit enables Timer2 to start counting. Software can fill 0 to stop it and set 1 to reload and count.
Note3: This field will be cleared when software set SC_ALTCTL[TX_RST] or SC_ALTCTL [RX_RST] to 1. So don't fill this bit, TX_RST, and RX_RST at the same time.
Note4: If SC_CTL [SC_CEN] not enabled, this field cannot be programmed.
7
1
read-write
0
Stops counting
#0
1
Starts counting
#1
TX_RST
TX Software Reset\nWhen TX_RST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared and it needs at least 3 SC peripheral clock cycles.
0
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
WARST_EN
Warm Reset Sequence Generator Enable
This bit enables SC controller to initiate the card by warm reset sequence
Note1: When the warm reset sequence completed, this bit will be cleared automatically and the SC_ISR[INIT_IS] will be set to 1 .
Note2: This field will be cleared when software set SC_ALTCTL[TX_RST] or SC_ALTCTL[RX_RST] to 1. So don't fill this bit, TX_RST, and RX_RST at the same time.
Note3: If SC_CTL[SC_CEN] not enabled, this field cannot be programmed.
4
1
read-write
0
No effect
#0
1
Warm reset sequence generator Enabled
#1
SC_CTL
SC_CTL
SC Control Register
0x4
read-write
n
0x0
0x0
AUTO_CON_EN
Auto Convention Enable\n
3
1
read-write
0
Auto-convention Disabled
#0
1
Auto-convention Enabled
#1
BGT
Block Guard Time (BGT)\nIn TX mode, hardware will auto hold off first character until BGT has elapsed regardless of the TX data.\n\nIn RX mode, software can enable SC_ALTCTL [RX_BGT_EN] to detect the first coming character timing. If the incoming data timing less than BGT, an interrupt will be generated.\n\nNote: The real block guard time is BGT + 1.
8
5
read-write
CD_DEB_SEL
Card Detect De-bounce Select Register\n
24
2
read-write
CON_SEL
Convention Selection\nNote: If AUTO_CON_EN enabled, this fields must be ignored.
4
2
read-write
0
Direct convention
#00
1
Reserved
#01
2
Reserved
#10
3
Inverse convention
#11
DIS_RX
RX Transition Disable\nNote: If AUTO_CON_EN enabled, this fields must be ignored.
1
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
DIS_TX
TX Transition Disable\n
2
1
read-write
0
Transceiver Enabled
#0
1
Transceiver Disabled
#1
RX_ERETRY
RX Error Retry Count Register\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred.\nNote1: The real maximum retry number is RX_ERETRY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when RX_ERETRY_EN enabled. The change flow is to disable RX_ETRTRY_EN first and then fill new retry value.
16
3
read-write
RX_ERETRY_EN
RX Error Retry Enable Register\nThis bit enables receiver retry function when parity error has occurred.\nNote: Software must fill RX_ERETRY value before enabling this bit.
19
1
read-write
0
RX error retry function Disabled
#0
1
RX error retry function Enabled
#1
RX_FTRI_LEV
Rx Buffer Trigger Level \n
6
2
read-write
SC_CEN
SC Engine Enable
Setting this bit to 1 will enable SC operation. If this bit is cleared, SC will force all transition to IDLE state.
0
1
read-write
SLEN
Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2.
15
1
read-write
0
The stop bit length is 2 ETU
#0
1
The stop bit length is 1 ETU
#1
TMR_SEL
Timer Selection \n
13
2
read-write
TX_ERETRY
TX Error Retry Count Register\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TX_ERETRY + 1, 8 is the maximum retry number.\nNote2: This field cannot be changed when TX_ERETRY_EN enabled. The change flow is to disable TX_ETRTRY_EN first and then fill new retry value.
20
3
read-write
TX_ERETRY_EN
TX Error Retry Enable Register\nThis bit enables transmitter retry function when parity error has occurred.\nNote: Software must fill TX_ERETRY value before enabling this bit.
23
1
read-write
0
TX error retry function Disabled
#0
1
TX error retry function Enabled
#1
SC_EGTR
SC_EGTR
SC Extend Guard Time Register
0xC
read-write
n
0x0
0x0
EGT
Extended Guard Time\nThis field indicates the extended guard time value.\n\nNote: The counter is ETU based and the real extended guard time is EGT.
0
8
read-write
SC_ETUCR
SC_ETUCR
SC ETU Control Register
0x14
-1
read-write
n
0x0
0x0
COMPEN_EN
Compensation Mode Enable\nThis bit enables clock compensation function. When this bit enabled, hardware will alternate between n-1 clock cycles and n clock cycles, where n is the value to be written into the ETU_RDIV register.\n
15
1
read-write
0
Compensation function Disabled
#0
1
Compensation function Enabled
#1
ETU_RDIV
ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETU_RDIV + 1.\nNote1: Software can configure this field, but this field must be greater than 0x04.\nNote2: Software can configure this field, but if the error rate is equal to 2%, this field must be greater than 0x040.
0
12
read-write
SC_IER
SC_IER
SC Interrupt Enable Register
0x18
read-write
n
0x0
0x0
ACON_ERR_IE
Auto Convention Error Interrupt Enable \nThis field is used for auto-convention error interrupt enable.\n
10
1
read-write
0
Auto-convention error interrupt Disabled
#0
1
Auto-convention error interrupt Enabled
#1
BGT_IE
Block Guard Time Interrupt Enable\nThis field is used for block guard time interrupt enable.\n
6
1
read-write
0
Block guard time Disabled
#0
1
Block guard time Enabled
#1
CD_IE
Card Detect Interrupt Enable\nThis field is used for card detect interrupt enable. The card detect status register is SC_PINCSR[CD_INS_F] and SC_PINCSR[CD_REM_F].\n
7
1
read-write
0
Card detect interrupt Disabled
#0
1
Card detect interrupt Enabled
#1
INIT_IE
Initial End Interrupt Enable\nThis field is used for activation (SC_ALTCTL [ACT_EN]), deactivation (SC_ALTCTL [DACT_EN]) and warm reset (SC_ALTCTL [WARST_EN]) sequence interrupt enable.\n
8
1
read-write
0
Initial end interrupt Disabled
#0
1
Initial end interrupt Enabled
#1
RDA_IE
Receive Data Reach Interrupt Enable\nThis field is used for received data reaching trigger level (SC_CTL [RX_FTRI_LEV]) interrupt enable.\n
0
1
read-write
0
Receive data reach trigger level interrupt Disabled
#0
1
Receive data reach trigger level interrupt Enabled
#1
RTMR_IE
Receiver Buffer Time-out Interrupt Enable \nThis field is used for receiver buffer time-out interrupt enable.\n
9
1
read-write
0
Receiver buffer time-out interrupt Disabled
#0
1
Receiver buffer time-out interrupt Enabled
#1
TBE_IE
Transmit Buffer Empty Interrupt Enable\nThis field is used for transmit buffer empty interrupt enable.\n
1
1
read-write
0
Transmit buffer empty interrupt Disabled
#0
1
Transmit buffer empty interrupt Enabled
#1
TERR_IE
Transfer Error Interrupt Enable\nThis field is used for transfer error interrupt enable. The transfer error states is at SC_TRSR register which includes receiver break error (RX_EBR_F), frame error (RX_EFR_F), parity error (RX_EPA_F), receiver buffer overflow error (RX_OVER_F), transmit buffer overflow error (TX_OVER_F), receiver retry over limit error (RX_OVER_REERR) and transmitter retry over limit error (TX_OVER_REERR).\n
2
1
read-write
0
Transfer error interrupt Disabled
#0
1
Transfer error interrupt Enabled
#1
TMR0_IE
Timer0 Interrupt Enable\nThis field is used for TMR0 interrupt enable.\n
3
1
read-write
0
Timer0 interrupt Disabled
#0
1
Timer0 interrupt Enabled
#1
TMR1_IE
Timer1 Interrupt Enable\nThis field is used for TMR1 interrupt enable.\n
4
1
read-write
0
Timer1 interrupt Disabled
#0
1
Timer1 interrupt Enabled
#1
TMR2_IE
Timer2 Interrupt Enable\nThis field is used for TMR2 interrupt enable.\n
5
1
read-write
0
Timer2 interrupt Disabled
#0
1
Timer2 interrupt Enabled
#1
SC_ISR
SC_ISR
SC Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
ACON_ERR_IS
Auto Convention Error Interrupt Status Flag (Read Only)
This field indicates auto convention sequence error. If the received TS at ATR state is not 0x3B or 0x3F, this bit will be set.
Note: This bit is read only, but can be cleared by writing 1 to it.
10
1
read-only
BGT_IS
Block Guard Time Interrupt Status Flag (Read Only)
This field is used for block guard time interrupt status flag.
Note1: This bit is valid when SC_ALTCTL[RX_BGT_EN] is enabled.
Note2: This bit is read only, but it can be cleared by writing 1 to it.
6
1
read-only
CD_IS
Card Detect Interrupt Status Flag (Read Only)\nNote: If software wants to clear this field, software must clear SC_PINCSR [CD_INS_F] and SC_PINCSR [CD_REM_F].
7
1
read-only
INIT_IS
Initial End Interrupt Status Flag (Read Only)
This field is used for activation (SC_ALTCTL [ACT_EN]), deactivation (SC_ALTCTL [DACT_EN]) and warm reset (SC_ALTCTL [WARST_EN]) sequence interrupt status flag.
Note: This bit is read only, but it can be cleared by writing 1 to it.
8
1
read-only
RDA_IS
Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level (SC_CTL[RX_FTRI_LEV]) interrupt status flag.\nNote: This field is the status flag of received data reaching SC_CTL [RX_FTRI_LEV]. If software reads data from SC_RBR and receiver pointer is less than SC_CTL [RX_FTRI_LEV], this bit will be cleared automatically.
0
1
read-only
RTMR_IS
Receiver Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit, software must read the receiver buffer remaining data by reading SC_RBR register,
9
1
read-only
TBE_IS
Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This field is the status flag of transmit buffer empty state. If software wants to clear this bit, software must write data to SC_THR register and then this bit will be cleared automatically.
1
1
read-only
TERR_IS
Transfer Error Interrupt Status Flag (Read Only)
This field is used for transfer error interrupt status flag. The transfer error status is at the SC_TRSR register which includes receiver break error (RX_EBR_F), frame error (RX_EFR_F), parity error (RX_EPA_F) and receiver buffer overflow error (RX_OVER_F), transmit buffer overflow error (TX_OVER_F), receiver retry over limit error (RX_OVER_REERR) and transmitter retry over limit error (TX_OVER_REERR).
Note: This field is the status flag of SC_TRSR[RX_EBR_F], SC_TRSR[RX_EFR_F], SC_TRSR[RX_EPA_F], SC_TRSR[RX_OVER_F], SC_TRSR[TX_OVER_F], SC_TRSR[RX_OVER_REERR] or SC_TRSR[TX_OVER_REERR]. So if software wants to clear this bit, software must write 1 to each field.
2
1
read-only
TMR0_IS
Timer0 Interrupt Status Flag (Read Only)
This field is used for TMR0 interrupt status flag.
Note: This bit is read only, but it can be cleared by writing 1 to it.
3
1
read-only
TMR1_IS
Timer1 Interrupt Status Flag (Read Only)
This field is used for TMR1 interrupt status flag.
Note: This bit is read only, but it can be cleared by writing 1 to it.
4
1
read-only
TMR2_IS
Timer2 Interrupt Status Flag (Read Only)
This field is used for TMR2 interrupt status flag.
Note: This bit is read only, but it can be cleared by writing 1 to it.
5
1
read-only
SC_PINCSR
SC_PINCSR
SC Pin Control State Register
0x24
read-write
n
0x0
0x0
ADAC_CD_EN
Auto Deactivation When Card Removal\nNote: When the card is removed, hardware will stop any process and then do deactivation sequence (if this bit be setting). If this process completes. Hardware will generate an initial end interrupt to CPU.
7
1
read-write
0
Auto deactivation Disabled when hardware detected the card removal
#0
1
Auto deactivation Enabled when hardware detected the card removal
#1
CD_INS_F
Card Detect Insert Status Of SC_CD Pin (Read Only)
This bit is set whenever card has been inserted.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: The card detect engine will start after SC_CTL[SC_CEN] set.
3
1
read-only
0
No effect
#0
1
Card insert
#1
CD_LEV
Card Detect Level\n\nNote: Software must select card detect level before Smart Card engine is enabled.
10
1
read-write
0
When hardware detects the card detect pin from high to low, it indicates a card is detected
#0
1
When hardware detects the card detect pin from low to high, it indicates a card is detected
#1
CD_PIN_ST
Card Detect Status Of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD\n
4
1
read-only
0
The SC_CD pin state at low
#0
1
The SC_CD pin state at high
#1
CD_REM_F
Card Detect Removal Status Of SC_CD Pin (Read Only)
This bit is set whenever a card has been removed.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: Card detect engine will start after SC_CTL[SC_CEN] set.
2
1
read-only
0
No effect
#0
1
Card removed
#1
CLK_KEEP
SC Clock Enable\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
6
1
read-write
0
SC clock generation Disabled
#0
1
SC clock always keeps free running
#1
POW_EN
SC_POW_EN Pin Signal\n
0
1
read-write
0
SC_PWR pin status is low
#0
1
SC_PWR pin status is high
#1
POW_INV
SC_PWR Pin Inverse\n
11
1
read-write
SC_DATA_I_ST
SC Data Pin Status (Read Only)\nThis bit is the pin status of SC_DAT\n
16
1
read-only
0
The SC_DAT pin is low
#0
1
The SC_DAT pin is high
#1
SC_DATA_O
SC Data Output Pin \nThis bit is the pin status of SC_DAT but user can drive SC_DAT pin to high or low by setting this bit.\nWrite this field to drive SC_DAT pin.\nNote: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when SC is in these modes.
9
1
read-write
0
Drive SC_DAT pin to low.\nSC_DAT pin status is low
#0
1
Drive SC_DAT pin to high.\nSC_DAT pin status is high
#1
SC_OEN_ST
SC Data Output Enable Pin Status (Read Only)\nThis bit is the output enable status of the SC_DAT pin.\n
8
1
read-only
0
The SC_DAT pin state is output
#0
1
The SC_DAT pin state is not output
#1
SC_RST
SC_RST Pin Signal\nThis bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.\nWrite this field to drive SC_RST pin.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
1
1
read-write
0
Drive SC_RST pin to low.\nSC_RST pin status is low
#0
1
Drive SC_RST pin to high.\nSC_RST pin status is high
#1
SC_RBR
SC_RBR
SC Receiving Buffer Register.
0x0
read-only
n
0x0
0x0
RBR
Receive Buffer Register\nBy reading this register, the SC will return an 8-bit received data.
0
8
read-only
SC_RFTMR
SC_RFTMR
SC Receiver Buffer Time-out Register
0x10
read-write
n
0x0
0x0
RFTM
SC Receiver Buffer Time-out Register (ETU Based)
Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5
Note2: Filling all 0 to this field indicates to disable this function.
0
9
read-write
SC_TDRA
SC_TDRA
SC Timer Current Data Register A
0x38
-1
read-only
n
0x0
0x0
TDR0
Timer0 Current Data Register (Read Only)\nThis field indicates the current count values of timer0.
0
24
read-only
SC_TDRB
SC_TDRB
SC Timer Current Data Register B
0x3C
-1
read-only
n
0x0
0x0
TDR1
Timer1 Current Data Register (Read Only)\nThis field indicates the current count values of timer1.
0
8
read-only
TDR2
Timer2 Current Data Register (Read Only)\nThis field indicates the current count values of timer2.
8
8
read-only
SC_THR
SC_THR
SC Transmit Holding Register
SC_RBR
0x0
write-only
n
0x0
0x0
THR
Transmit Holding Register\nBy writing to this register, the SC will send out an 8-bit data.\nNote: If SC_CTL[SC_CEN] not enabled, this register cannot be programmed.
0
8
write-only
SC_TMR0
SC_TMR0
SC Internal Timer Control Register 0
0x28
read-write
n
0x0
0x0
CNT
Timer 0 Counter Value Register (ETU Based)\nThis field indicates the internal timer operation values.
0
24
read-write
MODE
Timer 0 Operation Mode Selection\n
24
4
read-write
SC_TMR1
SC_TMR1
SC Internal Timer Control Register 1
0x2C
read-write
n
0x0
0x0
CNT
Timer 1 Counter Value Register (ETU Based)\nThis field indicates the internal timer operation values.
0
8
read-write
MODE
Timer 1 Operation Mode Selection\n
24
4
read-write
SC_TMR2
SC_TMR2
SC Internal Timer Control Register 2
0x30
read-write
n
0x0
0x0
CNT
Timer 2 Counter Value Register (ETU Based)\nThis field indicates the internal timer operation values.
0
8
read-write
MODE
Timer 2 Operation Mode Selection\n
24
4
read-write
SC_TRSR
SC_TRSR
SC Transfer Status Register
0x20
-1
read-write
n
0x0
0x0
RX_ATV
Receiver In Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished.
23
1
read-only
RX_EBR_F
Receiver Break Error Status Flag (Read Only)
This bit is set to 1 whenever the received data input (RX) held in the spacing state (logic 0 ) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). .
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting SC_CTL[RX_ERETRY_EN] register, hardware will not set this flag.
6
1
read-only
RX_EFR_F
Receiver Frame Error Status Flag (Read Only)
This bit is set to 1 whenever the received character does not have a valid STOP bit (that is, the STOP bit following the last data bit or parity bit is detected as logic 0).
Note1: This bit is read only, but can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting SC_CTL[RX_ERETRY_EN] register, hardware will not set this flag.
5
1
read-only
RX_EMPTY_F
Receiver Buffer Empty Status Flag(Read Only)
This bit indicates RX buffer empty or not.
When the last byte of RX buffer has been read by CPU, hardware set this bit to 1 . It will be cleared by hardware when SC receives any new data.
1
1
read-only
RX_EPA_F
Receiver Parity Error Status Flag (Read Only)
This bit is set to 1 whenever the received character does not have a valid parity bit .
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting SC_CTL[RX_ERETRY_EN] register, hardware will not set this flag.
4
1
read-only
RX_FULL_F
Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
2
1
read-only
RX_OVER_F
RX Overflow Error Status Flag (Read Only)
This bit is set when RX buffer overflow.
If the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.
Note: This bit is read only, but it can be cleared by writing 1 to it.
0
1
read-only
RX_OVER_REERR
Receiver Over Retry Error (Read Only)
This bit is set by hardware when RX transfer error retry over retry number limit.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU enables receiver retries function by setting SC_CTL [RX_ERETRY_EN] register, the RX_EPA_F flag will be ignored (hardware will not set RX_EPA_F).
22
1
read-only
RX_POINT_F
Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device, RX_POINT_F increases one. When one byte of RX buffer is read by CPU, RX_POINT_F decreases one.
16
2
read-only
RX_REERR
Receiver Retry Error (Read Only)
This bit is set by hardware when RX has any error and retries transfer.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2 This bit is a flag and cannot generate any interrupt to CPU.
Note3: If CPU enables receiver retry function by setting SC_CTL [RX_ERETRY_EN] register, the RX_EPA_F flag will be ignored (hardware will not set RX_EPA_F).
21
1
read-only
TX_ATV
Transmit In Active Status Flag (Read Only)\nThis bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has not been transmitted.\nThis bit is cleared automatically when TX transfer is finished or the last byte transmission has completed.
31
1
read-only
TX_EMPTY_F
Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into SC_THR (TX buffer not empty).
9
1
read-only
TX_FULL_F
Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates TX buffer full or not.\nThis bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
10
1
read-only
TX_OVER_F
TX Overflow Error Interrupt Status Flag (Read Only)
If TX buffer is full, an additional write to SC_THR will cause this bit be set to 1 by hardware.
Note: This bit is read only, but it can be cleared by writing 1 to it.
8
1
read-only
TX_OVER_REERR
Transmitter Over Retry Error (Read Only)
This bit is set by hardware when transmitter re-transmits over retry number limitation.
Note: This bit is read only, but it can be cleared by writing 1 to it.
30
1
read-only
TX_POINT_F
Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_THR, TX_POINT_F increases one. When one byte of TX Buffer is transferred to transmitter shift register, TX_POINT_F decreases one.
24
2
read-only
TX_REERR
Transmitter Retry Error (Read Only)
This bit is set by hardware when transmitter re-transmits.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: This bit is a flag and cannot generate any interrupt to CPU.
29
1
read-only
SC2
SC Register Map
SC
0x0
0x0
0x30
registers
n
0x38
0x8
registers
n
SC_ALTCTL
SC_ALTCTL
SC Alternate Control State Register
0x8
read-write
n
0x0
0x0
ACT_EN
Activation Sequence Generator Enable
This bit enables SC controller to initiate the card by activation sequence
Note1: When the activation sequence completed, this bit will be cleared automatically and the SC_ISR [INIT_IS] will be set to 1 .
Note2: This field will be cleared when software set SC_ALTCTL[TX_RST] or SC_ALTCTL[RX_RST] to 1. So don't fill this bit, TX_RST, and RX_RST at the same time.
Note3: If SC_CTL[SC_CEN] not enabled, this field cannot be programmed.
3
1
read-write
0
No effect
#0
1
Activation sequence generator Enabled
#1
DACT_EN
Deactivation Sequence Generator Enable
This bit enables SC controller to initiate the card by deactivation sequence
Note1: When the deactivation sequence completed, this bit will be cleared automatically and the SC_ISR [INIT_IS] will be set to 1 .
Note2: This field will be cleared when software set SC_ALTCTL[TX_RST] or SC_ALTCTL[RX_RST] to 1. So don't fill this bit, TX_RST, and RX_RST at the same time.
Note3: If SC_CTL [SC_CEN] not enabled, this field cannot be programmed.
2
1
read-write
0
No effect
#0
1
Deactivation sequence generator Enabled
#1
INIT_SEL
Initial Timing Selection\n
8
2
read-write
RX_BGT_EN
Check Receiver Block Guard Time Function Enable\n
12
1
read-write
0
Check receiver block guard time function Disabled
#0
1
Check receiver block guard time function Enabled
#1
RX_RST
Rx Software Reset\nWhen RX_RST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared and it needs at least 3 SC peripheral clock cycles.
1
1
read-write
0
No effect
#0
1
Reset the Rx internal state machine and pointers
#1
TMR0_ATV
Internal Timer0 Active State (Read Only)\nThis bit indicates the Timer0 counter status.\n
13
1
read-only
0
Timer0 is not active
#0
1
Timer0 is active
#1
TMR0_SEN
Internal Timer0 Start Enable
This bit enables Timer0 to start counting. Software can fill 0 to stop it and set 1 to reload and count.
Note3: This field will be cleared when software set SC_ALTCTL[TX_RST] or SC_ALTCTL[RX_RST] to 1. So don't fill this bit, TX_RST and RX_RST at the same time.
Note4: If SC_CTL [SC_CEN] not enabled, this field cannot be programmed.
5
1
read-write
0
Stops counting
#0
1
Starts counting
#1
TMR1_ATV
Internal Timer1 Active State (Read Only)\nThis bit indicates the Timer1 counter status.\n
14
1
read-only
0
Timer1 is not active
#0
1
Timer1 is active
#1
TMR1_SEN
Internal Timer1 Start Enable
This bit enables Timer1 to start counting. Software can fill 0 to stop it and set 1 to reload and count.
Note3: This field will be cleared when software set SC_ALTCTL[TX_RST] or SC_ALTCTL[RX_RST] to 1, so don't fill this bit, TX_RST, and RX_RST at the same time.
Note4: If SC_CTL [SC_CEN] not enabled, this field cannot be programmed.
6
1
read-write
0
Stops counting
#0
1
Starts counting
#1
TMR2_ATV
Internal Timer2 Active State (Read Only)\nThis bit indicates the Timer2 counter status.\n
15
1
read-only
0
Timer2 is not active
#0
1
Timer2 is active
#1
TMR2_SEN
Internal Timer2 Start Enable
This bit enables Timer2 to start counting. Software can fill 0 to stop it and set 1 to reload and count.
Note3: This field will be cleared when software set SC_ALTCTL[TX_RST] or SC_ALTCTL [RX_RST] to 1. So don't fill this bit, TX_RST, and RX_RST at the same time.
Note4: If SC_CTL [SC_CEN] not enabled, this field cannot be programmed.
7
1
read-write
0
Stops counting
#0
1
Starts counting
#1
TX_RST
TX Software Reset\nWhen TX_RST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared and it needs at least 3 SC peripheral clock cycles.
0
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
WARST_EN
Warm Reset Sequence Generator Enable
This bit enables SC controller to initiate the card by warm reset sequence
Note1: When the warm reset sequence completed, this bit will be cleared automatically and the SC_ISR[INIT_IS] will be set to 1 .
Note2: This field will be cleared when software set SC_ALTCTL[TX_RST] or SC_ALTCTL[RX_RST] to 1. So don't fill this bit, TX_RST, and RX_RST at the same time.
Note3: If SC_CTL[SC_CEN] not enabled, this field cannot be programmed.
4
1
read-write
0
No effect
#0
1
Warm reset sequence generator Enabled
#1
SC_CTL
SC_CTL
SC Control Register
0x4
read-write
n
0x0
0x0
AUTO_CON_EN
Auto Convention Enable\n
3
1
read-write
0
Auto-convention Disabled
#0
1
Auto-convention Enabled
#1
BGT
Block Guard Time (BGT)\nIn TX mode, hardware will auto hold off first character until BGT has elapsed regardless of the TX data.\n\nIn RX mode, software can enable SC_ALTCTL [RX_BGT_EN] to detect the first coming character timing. If the incoming data timing less than BGT, an interrupt will be generated.\n\nNote: The real block guard time is BGT + 1.
8
5
read-write
CD_DEB_SEL
Card Detect De-bounce Select Register\n
24
2
read-write
CON_SEL
Convention Selection\nNote: If AUTO_CON_EN enabled, this fields must be ignored.
4
2
read-write
0
Direct convention
#00
1
Reserved
#01
2
Reserved
#10
3
Inverse convention
#11
DIS_RX
RX Transition Disable\nNote: If AUTO_CON_EN enabled, this fields must be ignored.
1
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
DIS_TX
TX Transition Disable\n
2
1
read-write
0
Transceiver Enabled
#0
1
Transceiver Disabled
#1
RX_ERETRY
RX Error Retry Count Register\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred.\nNote1: The real maximum retry number is RX_ERETRY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when RX_ERETRY_EN enabled. The change flow is to disable RX_ETRTRY_EN first and then fill new retry value.
16
3
read-write
RX_ERETRY_EN
RX Error Retry Enable Register\nThis bit enables receiver retry function when parity error has occurred.\nNote: Software must fill RX_ERETRY value before enabling this bit.
19
1
read-write
0
RX error retry function Disabled
#0
1
RX error retry function Enabled
#1
RX_FTRI_LEV
Rx Buffer Trigger Level \n
6
2
read-write
SC_CEN
SC Engine Enable
Setting this bit to 1 will enable SC operation. If this bit is cleared, SC will force all transition to IDLE state.
0
1
read-write
SLEN
Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2.
15
1
read-write
0
The stop bit length is 2 ETU
#0
1
The stop bit length is 1 ETU
#1
TMR_SEL
Timer Selection \n
13
2
read-write
TX_ERETRY
TX Error Retry Count Register\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TX_ERETRY + 1, 8 is the maximum retry number.\nNote2: This field cannot be changed when TX_ERETRY_EN enabled. The change flow is to disable TX_ETRTRY_EN first and then fill new retry value.
20
3
read-write
TX_ERETRY_EN
TX Error Retry Enable Register\nThis bit enables transmitter retry function when parity error has occurred.\nNote: Software must fill TX_ERETRY value before enabling this bit.
23
1
read-write
0
TX error retry function Disabled
#0
1
TX error retry function Enabled
#1
SC_EGTR
SC_EGTR
SC Extend Guard Time Register
0xC
read-write
n
0x0
0x0
EGT
Extended Guard Time\nThis field indicates the extended guard time value.\n\nNote: The counter is ETU based and the real extended guard time is EGT.
0
8
read-write
SC_ETUCR
SC_ETUCR
SC ETU Control Register
0x14
-1
read-write
n
0x0
0x0
COMPEN_EN
Compensation Mode Enable\nThis bit enables clock compensation function. When this bit enabled, hardware will alternate between n-1 clock cycles and n clock cycles, where n is the value to be written into the ETU_RDIV register.\n
15
1
read-write
0
Compensation function Disabled
#0
1
Compensation function Enabled
#1
ETU_RDIV
ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETU_RDIV + 1.\nNote1: Software can configure this field, but this field must be greater than 0x04.\nNote2: Software can configure this field, but if the error rate is equal to 2%, this field must be greater than 0x040.
0
12
read-write
SC_IER
SC_IER
SC Interrupt Enable Register
0x18
read-write
n
0x0
0x0
ACON_ERR_IE
Auto Convention Error Interrupt Enable \nThis field is used for auto-convention error interrupt enable.\n
10
1
read-write
0
Auto-convention error interrupt Disabled
#0
1
Auto-convention error interrupt Enabled
#1
BGT_IE
Block Guard Time Interrupt Enable\nThis field is used for block guard time interrupt enable.\n
6
1
read-write
0
Block guard time Disabled
#0
1
Block guard time Enabled
#1
CD_IE
Card Detect Interrupt Enable\nThis field is used for card detect interrupt enable. The card detect status register is SC_PINCSR[CD_INS_F] and SC_PINCSR[CD_REM_F].\n
7
1
read-write
0
Card detect interrupt Disabled
#0
1
Card detect interrupt Enabled
#1
INIT_IE
Initial End Interrupt Enable\nThis field is used for activation (SC_ALTCTL [ACT_EN]), deactivation (SC_ALTCTL [DACT_EN]) and warm reset (SC_ALTCTL [WARST_EN]) sequence interrupt enable.\n
8
1
read-write
0
Initial end interrupt Disabled
#0
1
Initial end interrupt Enabled
#1
RDA_IE
Receive Data Reach Interrupt Enable\nThis field is used for received data reaching trigger level (SC_CTL [RX_FTRI_LEV]) interrupt enable.\n
0
1
read-write
0
Receive data reach trigger level interrupt Disabled
#0
1
Receive data reach trigger level interrupt Enabled
#1
RTMR_IE
Receiver Buffer Time-out Interrupt Enable \nThis field is used for receiver buffer time-out interrupt enable.\n
9
1
read-write
0
Receiver buffer time-out interrupt Disabled
#0
1
Receiver buffer time-out interrupt Enabled
#1
TBE_IE
Transmit Buffer Empty Interrupt Enable\nThis field is used for transmit buffer empty interrupt enable.\n
1
1
read-write
0
Transmit buffer empty interrupt Disabled
#0
1
Transmit buffer empty interrupt Enabled
#1
TERR_IE
Transfer Error Interrupt Enable\nThis field is used for transfer error interrupt enable. The transfer error states is at SC_TRSR register which includes receiver break error (RX_EBR_F), frame error (RX_EFR_F), parity error (RX_EPA_F), receiver buffer overflow error (RX_OVER_F), transmit buffer overflow error (TX_OVER_F), receiver retry over limit error (RX_OVER_REERR) and transmitter retry over limit error (TX_OVER_REERR).\n
2
1
read-write
0
Transfer error interrupt Disabled
#0
1
Transfer error interrupt Enabled
#1
TMR0_IE
Timer0 Interrupt Enable\nThis field is used for TMR0 interrupt enable.\n
3
1
read-write
0
Timer0 interrupt Disabled
#0
1
Timer0 interrupt Enabled
#1
TMR1_IE
Timer1 Interrupt Enable\nThis field is used for TMR1 interrupt enable.\n
4
1
read-write
0
Timer1 interrupt Disabled
#0
1
Timer1 interrupt Enabled
#1
TMR2_IE
Timer2 Interrupt Enable\nThis field is used for TMR2 interrupt enable.\n
5
1
read-write
0
Timer2 interrupt Disabled
#0
1
Timer2 interrupt Enabled
#1
SC_ISR
SC_ISR
SC Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
ACON_ERR_IS
Auto Convention Error Interrupt Status Flag (Read Only)
This field indicates auto convention sequence error. If the received TS at ATR state is not 0x3B or 0x3F, this bit will be set.
Note: This bit is read only, but can be cleared by writing 1 to it.
10
1
read-only
BGT_IS
Block Guard Time Interrupt Status Flag (Read Only)
This field is used for block guard time interrupt status flag.
Note1: This bit is valid when SC_ALTCTL[RX_BGT_EN] is enabled.
Note2: This bit is read only, but it can be cleared by writing 1 to it.
6
1
read-only
CD_IS
Card Detect Interrupt Status Flag (Read Only)\nNote: If software wants to clear this field, software must clear SC_PINCSR [CD_INS_F] and SC_PINCSR [CD_REM_F].
7
1
read-only
INIT_IS
Initial End Interrupt Status Flag (Read Only)
This field is used for activation (SC_ALTCTL [ACT_EN]), deactivation (SC_ALTCTL [DACT_EN]) and warm reset (SC_ALTCTL [WARST_EN]) sequence interrupt status flag.
Note: This bit is read only, but it can be cleared by writing 1 to it.
8
1
read-only
RDA_IS
Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level (SC_CTL[RX_FTRI_LEV]) interrupt status flag.\nNote: This field is the status flag of received data reaching SC_CTL [RX_FTRI_LEV]. If software reads data from SC_RBR and receiver pointer is less than SC_CTL [RX_FTRI_LEV], this bit will be cleared automatically.
0
1
read-only
RTMR_IS
Receiver Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit, software must read the receiver buffer remaining data by reading SC_RBR register,
9
1
read-only
TBE_IS
Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This field is the status flag of transmit buffer empty state. If software wants to clear this bit, software must write data to SC_THR register and then this bit will be cleared automatically.
1
1
read-only
TERR_IS
Transfer Error Interrupt Status Flag (Read Only)
This field is used for transfer error interrupt status flag. The transfer error status is at the SC_TRSR register which includes receiver break error (RX_EBR_F), frame error (RX_EFR_F), parity error (RX_EPA_F) and receiver buffer overflow error (RX_OVER_F), transmit buffer overflow error (TX_OVER_F), receiver retry over limit error (RX_OVER_REERR) and transmitter retry over limit error (TX_OVER_REERR).
Note: This field is the status flag of SC_TRSR[RX_EBR_F], SC_TRSR[RX_EFR_F], SC_TRSR[RX_EPA_F], SC_TRSR[RX_OVER_F], SC_TRSR[TX_OVER_F], SC_TRSR[RX_OVER_REERR] or SC_TRSR[TX_OVER_REERR]. So if software wants to clear this bit, software must write 1 to each field.
2
1
read-only
TMR0_IS
Timer0 Interrupt Status Flag (Read Only)
This field is used for TMR0 interrupt status flag.
Note: This bit is read only, but it can be cleared by writing 1 to it.
3
1
read-only
TMR1_IS
Timer1 Interrupt Status Flag (Read Only)
This field is used for TMR1 interrupt status flag.
Note: This bit is read only, but it can be cleared by writing 1 to it.
4
1
read-only
TMR2_IS
Timer2 Interrupt Status Flag (Read Only)
This field is used for TMR2 interrupt status flag.
Note: This bit is read only, but it can be cleared by writing 1 to it.
5
1
read-only
SC_PINCSR
SC_PINCSR
SC Pin Control State Register
0x24
read-write
n
0x0
0x0
ADAC_CD_EN
Auto Deactivation When Card Removal\nNote: When the card is removed, hardware will stop any process and then do deactivation sequence (if this bit be setting). If this process completes. Hardware will generate an initial end interrupt to CPU.
7
1
read-write
0
Auto deactivation Disabled when hardware detected the card removal
#0
1
Auto deactivation Enabled when hardware detected the card removal
#1
CD_INS_F
Card Detect Insert Status Of SC_CD Pin (Read Only)
This bit is set whenever card has been inserted.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: The card detect engine will start after SC_CTL[SC_CEN] set.
3
1
read-only
0
No effect
#0
1
Card insert
#1
CD_LEV
Card Detect Level\n\nNote: Software must select card detect level before Smart Card engine is enabled.
10
1
read-write
0
When hardware detects the card detect pin from high to low, it indicates a card is detected
#0
1
When hardware detects the card detect pin from low to high, it indicates a card is detected
#1
CD_PIN_ST
Card Detect Status Of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD\n
4
1
read-only
0
The SC_CD pin state at low
#0
1
The SC_CD pin state at high
#1
CD_REM_F
Card Detect Removal Status Of SC_CD Pin (Read Only)
This bit is set whenever a card has been removed.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: Card detect engine will start after SC_CTL[SC_CEN] set.
2
1
read-only
0
No effect
#0
1
Card removed
#1
CLK_KEEP
SC Clock Enable\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
6
1
read-write
0
SC clock generation Disabled
#0
1
SC clock always keeps free running
#1
POW_EN
SC_POW_EN Pin Signal\n
0
1
read-write
0
SC_PWR pin status is low
#0
1
SC_PWR pin status is high
#1
POW_INV
SC_PWR Pin Inverse\n
11
1
read-write
SC_DATA_I_ST
SC Data Pin Status (Read Only)\nThis bit is the pin status of SC_DAT\n
16
1
read-only
0
The SC_DAT pin is low
#0
1
The SC_DAT pin is high
#1
SC_DATA_O
SC Data Output Pin \nThis bit is the pin status of SC_DAT but user can drive SC_DAT pin to high or low by setting this bit.\nWrite this field to drive SC_DAT pin.\nNote: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when SC is in these modes.
9
1
read-write
0
Drive SC_DAT pin to low.\nSC_DAT pin status is low
#0
1
Drive SC_DAT pin to high.\nSC_DAT pin status is high
#1
SC_OEN_ST
SC Data Output Enable Pin Status (Read Only)\nThis bit is the output enable status of the SC_DAT pin.\n
8
1
read-only
0
The SC_DAT pin state is output
#0
1
The SC_DAT pin state is not output
#1
SC_RST
SC_RST Pin Signal\nThis bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.\nWrite this field to drive SC_RST pin.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes.
1
1
read-write
0
Drive SC_RST pin to low.\nSC_RST pin status is low
#0
1
Drive SC_RST pin to high.\nSC_RST pin status is high
#1
SC_RBR
SC_RBR
SC Receiving Buffer Register.
0x0
read-only
n
0x0
0x0
RBR
Receive Buffer Register\nBy reading this register, the SC will return an 8-bit received data.
0
8
read-only
SC_RFTMR
SC_RFTMR
SC Receiver Buffer Time-out Register
0x10
read-write
n
0x0
0x0
RFTM
SC Receiver Buffer Time-out Register (ETU Based)
Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5
Note2: Filling all 0 to this field indicates to disable this function.
0
9
read-write
SC_TDRA
SC_TDRA
SC Timer Current Data Register A
0x38
-1
read-only
n
0x0
0x0
TDR0
Timer0 Current Data Register (Read Only)\nThis field indicates the current count values of timer0.
0
24
read-only
SC_TDRB
SC_TDRB
SC Timer Current Data Register B
0x3C
-1
read-only
n
0x0
0x0
TDR1
Timer1 Current Data Register (Read Only)\nThis field indicates the current count values of timer1.
0
8
read-only
TDR2
Timer2 Current Data Register (Read Only)\nThis field indicates the current count values of timer2.
8
8
read-only
SC_THR
SC_THR
SC Transmit Holding Register
SC_RBR
0x0
write-only
n
0x0
0x0
THR
Transmit Holding Register\nBy writing to this register, the SC will send out an 8-bit data.\nNote: If SC_CTL[SC_CEN] not enabled, this register cannot be programmed.
0
8
write-only
SC_TMR0
SC_TMR0
SC Internal Timer Control Register 0
0x28
read-write
n
0x0
0x0
CNT
Timer 0 Counter Value Register (ETU Based)\nThis field indicates the internal timer operation values.
0
24
read-write
MODE
Timer 0 Operation Mode Selection\n
24
4
read-write
SC_TMR1
SC_TMR1
SC Internal Timer Control Register 1
0x2C
read-write
n
0x0
0x0
CNT
Timer 1 Counter Value Register (ETU Based)\nThis field indicates the internal timer operation values.
0
8
read-write
MODE
Timer 1 Operation Mode Selection\n
24
4
read-write
SC_TMR2
SC_TMR2
SC Internal Timer Control Register 2
0x30
read-write
n
0x0
0x0
CNT
Timer 2 Counter Value Register (ETU Based)\nThis field indicates the internal timer operation values.
0
8
read-write
MODE
Timer 2 Operation Mode Selection\n
24
4
read-write
SC_TRSR
SC_TRSR
SC Transfer Status Register
0x20
-1
read-write
n
0x0
0x0
RX_ATV
Receiver In Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished.
23
1
read-only
RX_EBR_F
Receiver Break Error Status Flag (Read Only)
This bit is set to 1 whenever the received data input (RX) held in the spacing state (logic 0 ) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). .
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting SC_CTL[RX_ERETRY_EN] register, hardware will not set this flag.
6
1
read-only
RX_EFR_F
Receiver Frame Error Status Flag (Read Only)
This bit is set to 1 whenever the received character does not have a valid STOP bit (that is, the STOP bit following the last data bit or parity bit is detected as logic 0).
Note1: This bit is read only, but can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting SC_CTL[RX_ERETRY_EN] register, hardware will not set this flag.
5
1
read-only
RX_EMPTY_F
Receiver Buffer Empty Status Flag(Read Only)
This bit indicates RX buffer empty or not.
When the last byte of RX buffer has been read by CPU, hardware set this bit to 1 . It will be cleared by hardware when SC receives any new data.
1
1
read-only
RX_EPA_F
Receiver Parity Error Status Flag (Read Only)
This bit is set to 1 whenever the received character does not have a valid parity bit .
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU sets receiver retries function by setting SC_CTL[RX_ERETRY_EN] register, hardware will not set this flag.
4
1
read-only
RX_FULL_F
Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
2
1
read-only
RX_OVER_F
RX Overflow Error Status Flag (Read Only)
This bit is set when RX buffer overflow.
If the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.
Note: This bit is read only, but it can be cleared by writing 1 to it.
0
1
read-only
RX_OVER_REERR
Receiver Over Retry Error (Read Only)
This bit is set by hardware when RX transfer error retry over retry number limit.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU enables receiver retries function by setting SC_CTL [RX_ERETRY_EN] register, the RX_EPA_F flag will be ignored (hardware will not set RX_EPA_F).
22
1
read-only
RX_POINT_F
Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device, RX_POINT_F increases one. When one byte of RX buffer is read by CPU, RX_POINT_F decreases one.
16
2
read-only
RX_REERR
Receiver Retry Error (Read Only)
This bit is set by hardware when RX has any error and retries transfer.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2 This bit is a flag and cannot generate any interrupt to CPU.
Note3: If CPU enables receiver retry function by setting SC_CTL [RX_ERETRY_EN] register, the RX_EPA_F flag will be ignored (hardware will not set RX_EPA_F).
21
1
read-only
TX_ATV
Transmit In Active Status Flag (Read Only)\nThis bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has not been transmitted.\nThis bit is cleared automatically when TX transfer is finished or the last byte transmission has completed.
31
1
read-only
TX_EMPTY_F
Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into SC_THR (TX buffer not empty).
9
1
read-only
TX_FULL_F
Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates TX buffer full or not.\nThis bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
10
1
read-only
TX_OVER_F
TX Overflow Error Interrupt Status Flag (Read Only)
If TX buffer is full, an additional write to SC_THR will cause this bit be set to 1 by hardware.
Note: This bit is read only, but it can be cleared by writing 1 to it.
8
1
read-only
TX_OVER_REERR
Transmitter Over Retry Error (Read Only)
This bit is set by hardware when transmitter re-transmits over retry number limitation.
Note: This bit is read only, but it can be cleared by writing 1 to it.
30
1
read-only
TX_POINT_F
Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_THR, TX_POINT_F increases one. When one byte of TX Buffer is transferred to transmitter shift register, TX_POINT_F decreases one.
24
2
read-only
TX_REERR
Transmitter Retry Error (Read Only)
This bit is set by hardware when transmitter re-transmits.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: This bit is a flag and cannot generate any interrupt to CPU.
29
1
read-only
SCS
SCS Register Map
SCS
0x0
0xD00
0x8
registers
n
0xD0C
0x8
registers
n
0xD1C
0x8
registers
n
AIRCR
AIRCR
Application Interrupt and Reset Control Register
0xD0C
-1
read-write
n
0x0
0x0
SYSRESETREQ
Writing this Bit 1 Will Cause a Reset Signal to Be Asserted to the Chip to Indicate a Reset Is Requested\nThe bit is a write only bit and self-clears as part of the reset sequence.
2
1
read-write
VECTCLRACTIVE
Setting this Bit to 1 Will Clear All Active State Information for Fixed and Configurable Exceptions\nThe bit is a write only bit and can only be written when the core is halted.\nNote: It is the debugger's responsibility to re-initialize the stack.
1
1
read-write
VECTORKEY
When writing this register, this field should be 0x05FA, otherwise the write action will be unpredictable.
16
16
read-write
CPUID
CPUID
CPUID Register
0xD00
-1
read-only
n
0x0
0x0
IMPLEMENTER
None
24
8
read-only
PART
Read as 0xC for ARMv6-M parts
16
4
read-only
PARTNO
Read as 0xC20.
4
12
read-only
REVISION
Read as 0x0
0
4
read-only
ICSR
ICSR
Interrupt Control and State Register
0xD04
read-write
n
0x0
0x0
ISRPENDING
Interrupt Pending Flag, Excluding NMI and Faults:\nThis bit is read only.
22
1
read-write
0
Interrupt not pending
#0
1
Interrupt pending
#1
ISRPREEMPT
If Set, a Pending Exception Will Be Serviced on Exit From the Debug Halt State\nThis bit is read only.
23
1
read-write
NMIPENDSET
NMI Set-pending Bit\nWrite:\nBecause NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.
31
1
read-write
0
No effect.\nNMI exception not pending
#0
1
Changes NMI exception state to pending.\nNMI exception pending
#1
PENDSTCLR
SysTick Exception Clear-pending Bit
Write:
This is a write only bit. When you want to clear PENDST bit, you must write 0 to PENDSTSET and write 1 to PENDSTCLR at the same time.
25
1
read-write
0
No effect
#0
1
Removes the pending state from the SysTick exception
#1
PENDSTSET
SysTick Exception Set-pending Bit\nWrite:\n
26
1
read-write
0
No effect.\nSysTick exception is not pending
#0
1
Changes SysTick exception state to pending.\nSysTick exception is pending
#1
PENDSVCLR
PendSV Clear-pending Bit
Write:
This is a write only bit. When you want to clear PENDSV bit, you must write 0 to PENDSVSET and write 1 to PENDSVCLR at the same time.
27
1
read-write
0
No effect
#0
1
Removes the pending state from the PendSV exception
#1
PENDSVSET
PendSV Set-pending Bit\nWrite:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending.
28
1
read-write
0
No effect.\nPendSV exception is not pending
#0
1
Changes PendSV exception state to pending.\nPendSV exception is pending
#1
VECTACTIVE
Contains the Active Exception Number\n
0
6
read-write
0
Thread mode
0
VECTPENDING
Indicates the Exception Number of the Highest Priority Pending Enabled Exception:\n
12
6
read-write
0
No pending exceptions
0
SCR
SCR
System Control Register
0xD10
read-write
n
0x0
0x0
SEVONPEND
Send Event on Pending Bit:\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event.
4
1
read-write
0
Only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded
#0
1
Enabled events and all interrupts, including disabled interrupts, can wake-up the processor
#1
SLEEPDEEP
Controls Whether the Processor Uses Sleep or Deep Sleep As Its Low Power Mode:\n
2
1
read-write
0
Sleep
#0
1
Deep sleep
#1
SLEEPONEXIT
Indicates Sleep-on-exit When Returning From Handler Mode to Thread Mode:\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
1
1
read-write
0
Do not sleep when returning to Thread mode
#0
1
Enter sleep, or deep sleep, on return from an ISR to Thread mode
#1
SHPR2
SHPR2
System Handler Priority Register 2
0xD1C
read-write
n
0x0
0x0
PRI_11
Priority of System Handler 11 - SVCall
0 denotes the highest priority and 3 denotes the lowest priority
30
2
read-write
SHPR3
SHPR3
System Handler Priority Register 3
0xD20
read-write
n
0x0
0x0
PRI_14
Priority of System Handler 14 - PendSV
0 denotes the highest priority and 3 denotes the lowest priority
22
2
read-write
PRI_15
Priority of System Handler 15 - SysTick
0 denotes the highest priority and 3 denotes the lowest priority
30
2
read-write
SPI0
SPI Register Map
SPI
0x0
0x0
0xC
registers
n
0x10
0x8
registers
n
0x20
0x8
registers
n
0x34
0x14
registers
n
SPI_CNTRL
SPI_CNTRL
Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CLKP
Clock Polarity\n
11
1
read-write
0
SPICLK is idle low
#0
1
SPICLK is idle high
#1
FIFO
FIFO Mode Enable
Note:
Before enabling FIFO mode, the other related settings should be set in advance.
In Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data to the transmit FIFO buffer the GO_BUSY bit will be cleared to 0 automatically when the SPI controller is in idle. If all data stored at transmit FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 and the GO_BUSY bit will be cleared to 0.
21
1
read-write
0
FIFO mode Disabled
#0
1
FIFO mode Enabled
#1
GO_BUSY
SPI Transfer Control Bit and Busy Status\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In Slave mode, this bit always returns 1 when this register is read by software. In Master mode, this bit reflects the busy or idle status of SPI.\nNote:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit.\nWhen FIFO mode is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA finishes the data transfer.
0
1
read-write
0
Data transfer stopped
#0
1
In Master mode, writing 1 to this bit to start the SPI data transfer in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master
#1
IE
Unit Transfer Interrupt Enable\n
17
1
read-write
0
SPI unit transfer interrupt Disabled
#0
1
SPI unit transfer interrupt Enabled
#1
IF
Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
LSB
Send LSB First\n
10
1
read-write
0
The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI TX0/1 register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX0/1)
#1
REORDER
Byte Reorder Function Enable\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\nIn Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval.\nThe byte reorder function is not supported when the variable serial clock function or Dual I/O mode is enabled.
19
1
read-write
0
Byte reorder function Disabled
#0
1
Byte reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SP_CYCLE
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n
24
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_FULL
Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25].\n
25
1
read-only
0
Receive FIOF buffer is not full
#0
1
Receive FIFO buffer is full
#1
RX_NEG
Receive on Negative Edge\n
1
1
read-write
0
Received data input signal is latched on the rising edge of SPICLK
#0
1
Received data input signal is latched on the falling edge of SPICLK
#1
SLAVE
Slave Mode Enable\n
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SP_CYCLE
Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\nIf the variable clock function is enabled and the transmit FIFO buffer is not empty, the minimum period of suspend interval between the successive transactions is (6.5 + SP_CYCLE) * SPICLK clock cycle.
12
4
read-write
TWOB
2-bit Mode Enable\nNote: When 2-bit mode is enabled, the serial transmitted 2-bit data are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0.
22
1
read-write
0
2-bit mode Disabled
#0
1
2-bit mode Enabled
#1
TX_BIT_LEN
Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n
3
5
read-write
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STAUTS[26].\n
26
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TX_FULL
Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27].\n
27
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TX_NEG
Transmit on Negative Edge\n
2
1
read-write
0
Transmitted data output signal is changed on the rising edge of SPICLK
#0
1
Transmitted data output signal is changed on the falling edge of SPICLK
#1
VARCLK_EN
Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is set to 1, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode).
23
1
read-write
0
SPI clock output frequency is fixed and decided only by the value of DIVIDER
#0
1
SPI clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2
#1
SPI_CNTRL2
SPI_CNTRL2
Control and Status Register 2
0x3C
-1
read-write
n
0x0
0x0
BCn
SPI Peripheral clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details.
31
1
read-write
0
Backward compatible clock configuration
#0
1
Clock configuration is not backward compatible
#1
DUAL_IO_DIR
Dual I/O Mode Direction Control\n
12
1
read-write
0
Dual Input mode
#0
1
Dual Output mode
#1
DUAL_IO_EN
Dual I/O Mode Enable\n
13
1
read-write
0
Dual I/O mode Disabled
#0
1
Dual I/O mode Enabled
#1
NOSLVSEL
Slave 3-wire Mode Enable\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI.\nNote: In Slave 3-wire mode, the SS_LTRIG, SPI_SSR[4] will be set as 1 automatically.
8
1
read-write
0
4-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLV_ABORT
Slave 3-wire Mode Abort Control\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more SPI clock input over the one transfer time in Slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software.
9
1
read-write
SLV_START_INTSTS
Slave 3-wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n
11
1
read-write
0
Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1
#0
1
A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit
#1
SSTA_INTEN
Slave 3-wire Mode Start Interrupt Enable\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.\n
10
1
read-write
0
Transaction start interrupt Disabled
#0
1
Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared
#1
SS_INT_OPT
Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n
16
1
read-write
0
As the slave select signal goes to inactive level, the IF bit will NOT be set to 1
#0
1
As the slave select signal goes to inactive level, the IF bit will be set to 1
#1
SPI_DIVIDER
SPI_DIVIDER
Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI peripheral clock, fspi_eclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. \nIf the bit of BCn, SPI_CNTRL2[31], is set to 0,\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI peripheral clock source, which is defined in the CLKSEL1 register.
0
8
read-write
DIVIDER2
Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation: \n\nIf the VARCLK_EN bit is cleared to 0, this setting is unmeaning.
16
8
read-write
SPI_DMA
SPI_DMA
SPI DMA Control Register
0x38
read-write
n
0x0
0x0
PDMA_RST
PDMA Reset\n
2
1
read-write
0
No effect
#0
1
Reset the PDMA control logic of the SPI controller. This bit will be cleared to 0 automatically
#1
RX_DMA_GO
Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware automatically after PDMA transfer is done.\nIf the software uses the receive PDMA function to access the received data of SPI and does not use the transmit PDMA function, the GO_BUSY bit should be set by software.\nEnabling FIFO mode is recommended if the software uses more than one PDMA channel to transfer data.\nIn Slave mode and when FIFO mode is disabled, if the software only uses one PDMA channel for SPI receive PDMA function and the other PDMA channels are not in use, the minimal suspend interval between two successive transactions must be larger than (9 SPI slave peripheral clock periods + 4 APB clock periods) for Edge-trigger mode or (9.5 SPI slave peripheral clock periods + 4 APB clock periods) for Level-trigger mode.
1
1
read-write
TX_DMA_GO
Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.\nIf the SPI transmit PDMA function is used to transfer data, the GO_BUSY bit should not be set to 1 by software. The PDMA control logic of SPI controller will set it automatically whenever necessary.\nIn Slave mode and when FIFO mode is disabled, the minimal suspend interval between two successive transactions must be larger than (8 SPI clock periods + 14 APB clock periods) for edge-trigger mode or (9.5 SPI clock periods + 14 APB clock periods) for level-trigger mode. If the 2-bit Transfer mode is enabled, additional 18 APB clock periods for the above conditions is required.
0
1
read-write
SPI_FIFO_CTL
SPI_FIFO_CTL
SPI FIFO Control Register
0x40
-1
read-write
n
0x0
0x0
RXOV_INTEN
Receive FIFO Overrun Interrupt Enable\n
6
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RX_CLR
Clear Receive FIFO Buffer\n
0
1
read-write
0
No effect
#0
1
Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software
#1
RX_INTEN
Receive Threshold Interrupt Enable\n
2
1
read-write
0
RX threshold interrupt Disabled
#0
1
RX threshold interrupt Enabled
#1
RX_THRESHOLD
Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0.
24
3
read-write
TIMEOUT_INTEN
Receive FIFO Time-out Interrupt Enable \n
21
1
read-write
0
Time-out interrupt Disabled
#0
1
Time-out interrupt Enabled
#1
TX_CLR
Clear Transmit FIFO Buffer\n
1
1
read-write
0
No effect
#0
1
Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software
#1
TX_INTEN
Transmit Threshold Interrupt Enable\n
3
1
read-write
0
TX threshold interrupt Disabled
#0
1
TX threshold interrupt Enabled
#1
TX_THRESHOLD
Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0.
28
3
read-write
SPI_RX0
SPI_RX0
Data Receive Register 0
0x10
read-only
n
0x0
0x0
RX
Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled, the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the receive FIFO buffer can be accessed through software by reading this register. This is a read-only register.
0
32
read-only
SPI_RX1
SPI_RX1
Data Receive Register 1
0x14
read-write
n
0x0
0x0
SPI_SSR
SPI_SSR
Slave Select Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select Function Enable (Master Only)\n
3
1
read-write
0
If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[1:0]
#0
1
If this bit is set, SPI_SS0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSR[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
#1
LTRIG_FLAG
Level Trigger Accomplish Flag\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \nNote: This bit is READ only. As the GO_BUSY bit is set to 1 by software, the LTRIG_FLAG will be cleared to 0 after 4 SPI peripheral clock periods plus 1 system clock period. In FIFO mode, this bit has no meaning.
5
1
read-write
0
Transferred bit length of one transaction does not meet the specified requirement
#0
1
Transferred bit length meets the specified requirement which defined in TX_BIT_LEN
#1
SSR
Slave Select Control Bits (Master Only)
If AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.
If the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPI_SS0/1 line at inactive state writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPI_SS0/1 is specified in SS_LVL.
Note: SPI_SS0 is defined as the slave select input in Slave mode.
0
2
read-write
SS_LTRIG
Slave Select Level Trigger Enable (Slave Only)\n
4
1
read-write
0
Slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge
#0
1
Slave select signal is level-trigger. The SS_LVL bit decides the signal is active low or active high
#1
SS_LVL
Slave Select Active Level\nThis bit defines the active status of slave select signal (SPI_SS0/1).\n
2
1
read-write
0
The slave select signal SPI_SS0/1 is active on low-level/falling-edge
#0
1
The slave select signal SPI_SS0/1 is active on high-level/rising-edge
#1
SPI_STATUS
SPI_STATUS
SPI Status Register
0x44
-1
read-write
n
0x0
0x0
IF
SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n
24
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_FIFO_COUNT
Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
12
4
read-only
RX_FULL
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[25].\n
25
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RX_INTSTS
Receive FIFO Threshold Interrupt Status (Read Only)\n
0
1
read-only
0
The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD
#1
RX_OVERRUN
Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself.
2
1
read-write
SLV_START_INTSTS
Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].\n
11
1
read-write
0
Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1
#0
1
A transaction has started in Slave 3-wire mode. It will be cleared as a transaction is done or by writing 1 to this bit
#1
TIMEOUT
Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
20
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26].\n
26
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TX_FIFO_COUNT
Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TX_FULL
Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n
27
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TX_INTSTS
Transmit FIFO Threshold Interrupt Status (Read Only)\n
4
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD
#1
SPI_TX0
SPI_TX0
Data Transmit Register 0
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bits TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: When the SPI controller is configured as a slave device and FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the transmit data register should be updated by software before setting the GO_BUSY bit to 1
0
32
write-only
SPI_TX1
SPI_TX1
Data Transmit Register 1
0x24
read-write
n
0x0
0x0
SPI_VARCLK
SPI_VARCLK
Variable Clock Pattern Register
0x34
-1
read-write
n
0x0
0x0
VARCLK
Variable Clock Pattern
This register defines the clock pattern of the SPI transfer. If the variable clock function is disabled, this setting is unmeaning. Refer to the Variable Clock Function paragraph for more detail description.
0
32
read-write
SPI1
SPI Register Map
SPI
0x0
0x0
0xC
registers
n
0x10
0x8
registers
n
0x20
0x8
registers
n
0x34
0x14
registers
n
SPI_CNTRL
SPI_CNTRL
Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CLKP
Clock Polarity\n
11
1
read-write
0
SPICLK is idle low
#0
1
SPICLK is idle high
#1
FIFO
FIFO Mode Enable
Note:
Before enabling FIFO mode, the other related settings should be set in advance.
In Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data to the transmit FIFO buffer the GO_BUSY bit will be cleared to 0 automatically when the SPI controller is in idle. If all data stored at transmit FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 and the GO_BUSY bit will be cleared to 0.
21
1
read-write
0
FIFO mode Disabled
#0
1
FIFO mode Enabled
#1
GO_BUSY
SPI Transfer Control Bit and Busy Status\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In Slave mode, this bit always returns 1 when this register is read by software. In Master mode, this bit reflects the busy or idle status of SPI.\nNote:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit.\nWhen FIFO mode is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA finishes the data transfer.
0
1
read-write
0
Data transfer stopped
#0
1
In Master mode, writing 1 to this bit to start the SPI data transfer in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master
#1
IE
Unit Transfer Interrupt Enable\n
17
1
read-write
0
SPI unit transfer interrupt Disabled
#0
1
SPI unit transfer interrupt Enabled
#1
IF
Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
LSB
Send LSB First\n
10
1
read-write
0
The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI TX0/1 register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX0/1)
#1
REORDER
Byte Reorder Function Enable\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\nIn Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval.\nThe byte reorder function is not supported when the variable serial clock function or Dual I/O mode is enabled.
19
1
read-write
0
Byte reorder function Disabled
#0
1
Byte reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SP_CYCLE
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n
24
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_FULL
Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25].\n
25
1
read-only
0
Receive FIOF buffer is not full
#0
1
Receive FIFO buffer is full
#1
RX_NEG
Receive on Negative Edge\n
1
1
read-write
0
Received data input signal is latched on the rising edge of SPICLK
#0
1
Received data input signal is latched on the falling edge of SPICLK
#1
SLAVE
Slave Mode Enable\n
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SP_CYCLE
Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\nIf the variable clock function is enabled and the transmit FIFO buffer is not empty, the minimum period of suspend interval between the successive transactions is (6.5 + SP_CYCLE) * SPICLK clock cycle.
12
4
read-write
TWOB
2-bit Mode Enable\nNote: When 2-bit mode is enabled, the serial transmitted 2-bit data are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0.
22
1
read-write
0
2-bit mode Disabled
#0
1
2-bit mode Enabled
#1
TX_BIT_LEN
Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n
3
5
read-write
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STAUTS[26].\n
26
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TX_FULL
Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27].\n
27
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TX_NEG
Transmit on Negative Edge\n
2
1
read-write
0
Transmitted data output signal is changed on the rising edge of SPICLK
#0
1
Transmitted data output signal is changed on the falling edge of SPICLK
#1
VARCLK_EN
Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is set to 1, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode).
23
1
read-write
0
SPI clock output frequency is fixed and decided only by the value of DIVIDER
#0
1
SPI clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2
#1
SPI_CNTRL2
SPI_CNTRL2
Control and Status Register 2
0x3C
-1
read-write
n
0x0
0x0
BCn
SPI Peripheral clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details.
31
1
read-write
0
Backward compatible clock configuration
#0
1
Clock configuration is not backward compatible
#1
DUAL_IO_DIR
Dual I/O Mode Direction Control\n
12
1
read-write
0
Dual Input mode
#0
1
Dual Output mode
#1
DUAL_IO_EN
Dual I/O Mode Enable\n
13
1
read-write
0
Dual I/O mode Disabled
#0
1
Dual I/O mode Enabled
#1
NOSLVSEL
Slave 3-wire Mode Enable\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI.\nNote: In Slave 3-wire mode, the SS_LTRIG, SPI_SSR[4] will be set as 1 automatically.
8
1
read-write
0
4-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLV_ABORT
Slave 3-wire Mode Abort Control\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more SPI clock input over the one transfer time in Slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software.
9
1
read-write
SLV_START_INTSTS
Slave 3-wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n
11
1
read-write
0
Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1
#0
1
A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit
#1
SSTA_INTEN
Slave 3-wire Mode Start Interrupt Enable\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.\n
10
1
read-write
0
Transaction start interrupt Disabled
#0
1
Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared
#1
SS_INT_OPT
Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n
16
1
read-write
0
As the slave select signal goes to inactive level, the IF bit will NOT be set to 1
#0
1
As the slave select signal goes to inactive level, the IF bit will be set to 1
#1
SPI_DIVIDER
SPI_DIVIDER
Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI peripheral clock, fspi_eclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. \nIf the bit of BCn, SPI_CNTRL2[31], is set to 0,\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI peripheral clock source, which is defined in the CLKSEL1 register.
0
8
read-write
DIVIDER2
Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation: \n\nIf the VARCLK_EN bit is cleared to 0, this setting is unmeaning.
16
8
read-write
SPI_DMA
SPI_DMA
SPI DMA Control Register
0x38
read-write
n
0x0
0x0
PDMA_RST
PDMA Reset\n
2
1
read-write
0
No effect
#0
1
Reset the PDMA control logic of the SPI controller. This bit will be cleared to 0 automatically
#1
RX_DMA_GO
Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware automatically after PDMA transfer is done.\nIf the software uses the receive PDMA function to access the received data of SPI and does not use the transmit PDMA function, the GO_BUSY bit should be set by software.\nEnabling FIFO mode is recommended if the software uses more than one PDMA channel to transfer data.\nIn Slave mode and when FIFO mode is disabled, if the software only uses one PDMA channel for SPI receive PDMA function and the other PDMA channels are not in use, the minimal suspend interval between two successive transactions must be larger than (9 SPI slave peripheral clock periods + 4 APB clock periods) for Edge-trigger mode or (9.5 SPI slave peripheral clock periods + 4 APB clock periods) for Level-trigger mode.
1
1
read-write
TX_DMA_GO
Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.\nIf the SPI transmit PDMA function is used to transfer data, the GO_BUSY bit should not be set to 1 by software. The PDMA control logic of SPI controller will set it automatically whenever necessary.\nIn Slave mode and when FIFO mode is disabled, the minimal suspend interval between two successive transactions must be larger than (8 SPI clock periods + 14 APB clock periods) for edge-trigger mode or (9.5 SPI clock periods + 14 APB clock periods) for level-trigger mode. If the 2-bit Transfer mode is enabled, additional 18 APB clock periods for the above conditions is required.
0
1
read-write
SPI_FIFO_CTL
SPI_FIFO_CTL
SPI FIFO Control Register
0x40
-1
read-write
n
0x0
0x0
RXOV_INTEN
Receive FIFO Overrun Interrupt Enable\n
6
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RX_CLR
Clear Receive FIFO Buffer\n
0
1
read-write
0
No effect
#0
1
Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software
#1
RX_INTEN
Receive Threshold Interrupt Enable\n
2
1
read-write
0
RX threshold interrupt Disabled
#0
1
RX threshold interrupt Enabled
#1
RX_THRESHOLD
Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0.
24
3
read-write
TIMEOUT_INTEN
Receive FIFO Time-out Interrupt Enable \n
21
1
read-write
0
Time-out interrupt Disabled
#0
1
Time-out interrupt Enabled
#1
TX_CLR
Clear Transmit FIFO Buffer\n
1
1
read-write
0
No effect
#0
1
Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software
#1
TX_INTEN
Transmit Threshold Interrupt Enable\n
3
1
read-write
0
TX threshold interrupt Disabled
#0
1
TX threshold interrupt Enabled
#1
TX_THRESHOLD
Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0.
28
3
read-write
SPI_RX0
SPI_RX0
Data Receive Register 0
0x10
read-only
n
0x0
0x0
RX
Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled, the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the receive FIFO buffer can be accessed through software by reading this register. This is a read-only register.
0
32
read-only
SPI_RX1
SPI_RX1
Data Receive Register 1
0x14
read-write
n
0x0
0x0
SPI_SSR
SPI_SSR
Slave Select Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select Function Enable (Master Only)\n
3
1
read-write
0
If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[1:0]
#0
1
If this bit is set, SPI_SS0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSR[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
#1
LTRIG_FLAG
Level Trigger Accomplish Flag\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \nNote: This bit is READ only. As the GO_BUSY bit is set to 1 by software, the LTRIG_FLAG will be cleared to 0 after 4 SPI peripheral clock periods plus 1 system clock period. In FIFO mode, this bit has no meaning.
5
1
read-write
0
Transferred bit length of one transaction does not meet the specified requirement
#0
1
Transferred bit length meets the specified requirement which defined in TX_BIT_LEN
#1
SSR
Slave Select Control Bits (Master Only)
If AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.
If the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPI_SS0/1 line at inactive state writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPI_SS0/1 is specified in SS_LVL.
Note: SPI_SS0 is defined as the slave select input in Slave mode.
0
2
read-write
SS_LTRIG
Slave Select Level Trigger Enable (Slave Only)\n
4
1
read-write
0
Slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge
#0
1
Slave select signal is level-trigger. The SS_LVL bit decides the signal is active low or active high
#1
SS_LVL
Slave Select Active Level\nThis bit defines the active status of slave select signal (SPI_SS0/1).\n
2
1
read-write
0
The slave select signal SPI_SS0/1 is active on low-level/falling-edge
#0
1
The slave select signal SPI_SS0/1 is active on high-level/rising-edge
#1
SPI_STATUS
SPI_STATUS
SPI Status Register
0x44
-1
read-write
n
0x0
0x0
IF
SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n
24
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_FIFO_COUNT
Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
12
4
read-only
RX_FULL
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[25].\n
25
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RX_INTSTS
Receive FIFO Threshold Interrupt Status (Read Only)\n
0
1
read-only
0
The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD
#1
RX_OVERRUN
Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself.
2
1
read-write
SLV_START_INTSTS
Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].\n
11
1
read-write
0
Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1
#0
1
A transaction has started in Slave 3-wire mode. It will be cleared as a transaction is done or by writing 1 to this bit
#1
TIMEOUT
Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
20
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26].\n
26
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TX_FIFO_COUNT
Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TX_FULL
Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n
27
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TX_INTSTS
Transmit FIFO Threshold Interrupt Status (Read Only)\n
4
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD
#1
SPI_TX0
SPI_TX0
Data Transmit Register 0
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bits TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: When the SPI controller is configured as a slave device and FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the transmit data register should be updated by software before setting the GO_BUSY bit to 1
0
32
write-only
SPI_TX1
SPI_TX1
Data Transmit Register 1
0x24
read-write
n
0x0
0x0
SPI_VARCLK
SPI_VARCLK
Variable Clock Pattern Register
0x34
-1
read-write
n
0x0
0x0
VARCLK
Variable Clock Pattern
This register defines the clock pattern of the SPI transfer. If the variable clock function is disabled, this setting is unmeaning. Refer to the Variable Clock Function paragraph for more detail description.
0
32
read-write
SPI2
SPI Register Map
SPI
0x0
0x0
0xC
registers
n
0x10
0x8
registers
n
0x20
0x8
registers
n
0x34
0x14
registers
n
SPI_CNTRL
SPI_CNTRL
Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CLKP
Clock Polarity\n
11
1
read-write
0
SPICLK is idle low
#0
1
SPICLK is idle high
#1
FIFO
FIFO Mode Enable
Note:
Before enabling FIFO mode, the other related settings should be set in advance.
In Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data to the transmit FIFO buffer the GO_BUSY bit will be cleared to 0 automatically when the SPI controller is in idle. If all data stored at transmit FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 and the GO_BUSY bit will be cleared to 0.
21
1
read-write
0
FIFO mode Disabled
#0
1
FIFO mode Enabled
#1
GO_BUSY
SPI Transfer Control Bit and Busy Status\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In Slave mode, this bit always returns 1 when this register is read by software. In Master mode, this bit reflects the busy or idle status of SPI.\nNote:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit.\nWhen FIFO mode is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA finishes the data transfer.
0
1
read-write
0
Data transfer stopped
#0
1
In Master mode, writing 1 to this bit to start the SPI data transfer in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master
#1
IE
Unit Transfer Interrupt Enable\n
17
1
read-write
0
SPI unit transfer interrupt Disabled
#0
1
SPI unit transfer interrupt Enabled
#1
IF
Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
LSB
Send LSB First\n
10
1
read-write
0
The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI TX0/1 register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX0/1)
#1
REORDER
Byte Reorder Function Enable\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\nIn Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval.\nThe byte reorder function is not supported when the variable serial clock function or Dual I/O mode is enabled.
19
1
read-write
0
Byte reorder function Disabled
#0
1
Byte reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SP_CYCLE
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n
24
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_FULL
Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25].\n
25
1
read-only
0
Receive FIOF buffer is not full
#0
1
Receive FIFO buffer is full
#1
RX_NEG
Receive on Negative Edge\n
1
1
read-write
0
Received data input signal is latched on the rising edge of SPICLK
#0
1
Received data input signal is latched on the falling edge of SPICLK
#1
SLAVE
Slave Mode Enable\n
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SP_CYCLE
Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\nIf the variable clock function is enabled and the transmit FIFO buffer is not empty, the minimum period of suspend interval between the successive transactions is (6.5 + SP_CYCLE) * SPICLK clock cycle.
12
4
read-write
TWOB
2-bit Mode Enable\nNote: When 2-bit mode is enabled, the serial transmitted 2-bit data are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0.
22
1
read-write
0
2-bit mode Disabled
#0
1
2-bit mode Enabled
#1
TX_BIT_LEN
Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n
3
5
read-write
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STAUTS[26].\n
26
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TX_FULL
Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27].\n
27
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TX_NEG
Transmit on Negative Edge\n
2
1
read-write
0
Transmitted data output signal is changed on the rising edge of SPICLK
#0
1
Transmitted data output signal is changed on the falling edge of SPICLK
#1
VARCLK_EN
Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is set to 1, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode).
23
1
read-write
0
SPI clock output frequency is fixed and decided only by the value of DIVIDER
#0
1
SPI clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2
#1
SPI_CNTRL2
SPI_CNTRL2
Control and Status Register 2
0x3C
-1
read-write
n
0x0
0x0
BCn
SPI Peripheral clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details.
31
1
read-write
0
Backward compatible clock configuration
#0
1
Clock configuration is not backward compatible
#1
DUAL_IO_DIR
Dual I/O Mode Direction Control\n
12
1
read-write
0
Dual Input mode
#0
1
Dual Output mode
#1
DUAL_IO_EN
Dual I/O Mode Enable\n
13
1
read-write
0
Dual I/O mode Disabled
#0
1
Dual I/O mode Enabled
#1
NOSLVSEL
Slave 3-wire Mode Enable\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI.\nNote: In Slave 3-wire mode, the SS_LTRIG, SPI_SSR[4] will be set as 1 automatically.
8
1
read-write
0
4-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLV_ABORT
Slave 3-wire Mode Abort Control\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more SPI clock input over the one transfer time in Slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software.
9
1
read-write
SLV_START_INTSTS
Slave 3-wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n
11
1
read-write
0
Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1
#0
1
A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit
#1
SSTA_INTEN
Slave 3-wire Mode Start Interrupt Enable\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.\n
10
1
read-write
0
Transaction start interrupt Disabled
#0
1
Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared
#1
SS_INT_OPT
Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n
16
1
read-write
0
As the slave select signal goes to inactive level, the IF bit will NOT be set to 1
#0
1
As the slave select signal goes to inactive level, the IF bit will be set to 1
#1
SPI_DIVIDER
SPI_DIVIDER
Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI peripheral clock, fspi_eclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. \nIf the bit of BCn, SPI_CNTRL2[31], is set to 0,\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI peripheral clock source, which is defined in the CLKSEL1 register.
0
8
read-write
DIVIDER2
Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation: \n\nIf the VARCLK_EN bit is cleared to 0, this setting is unmeaning.
16
8
read-write
SPI_DMA
SPI_DMA
SPI DMA Control Register
0x38
read-write
n
0x0
0x0
PDMA_RST
PDMA Reset\n
2
1
read-write
0
No effect
#0
1
Reset the PDMA control logic of the SPI controller. This bit will be cleared to 0 automatically
#1
RX_DMA_GO
Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware automatically after PDMA transfer is done.\nIf the software uses the receive PDMA function to access the received data of SPI and does not use the transmit PDMA function, the GO_BUSY bit should be set by software.\nEnabling FIFO mode is recommended if the software uses more than one PDMA channel to transfer data.\nIn Slave mode and when FIFO mode is disabled, if the software only uses one PDMA channel for SPI receive PDMA function and the other PDMA channels are not in use, the minimal suspend interval between two successive transactions must be larger than (9 SPI slave peripheral clock periods + 4 APB clock periods) for Edge-trigger mode or (9.5 SPI slave peripheral clock periods + 4 APB clock periods) for Level-trigger mode.
1
1
read-write
TX_DMA_GO
Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.\nIf the SPI transmit PDMA function is used to transfer data, the GO_BUSY bit should not be set to 1 by software. The PDMA control logic of SPI controller will set it automatically whenever necessary.\nIn Slave mode and when FIFO mode is disabled, the minimal suspend interval between two successive transactions must be larger than (8 SPI clock periods + 14 APB clock periods) for edge-trigger mode or (9.5 SPI clock periods + 14 APB clock periods) for level-trigger mode. If the 2-bit Transfer mode is enabled, additional 18 APB clock periods for the above conditions is required.
0
1
read-write
SPI_FIFO_CTL
SPI_FIFO_CTL
SPI FIFO Control Register
0x40
-1
read-write
n
0x0
0x0
RXOV_INTEN
Receive FIFO Overrun Interrupt Enable\n
6
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RX_CLR
Clear Receive FIFO Buffer\n
0
1
read-write
0
No effect
#0
1
Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software
#1
RX_INTEN
Receive Threshold Interrupt Enable\n
2
1
read-write
0
RX threshold interrupt Disabled
#0
1
RX threshold interrupt Enabled
#1
RX_THRESHOLD
Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0.
24
3
read-write
TIMEOUT_INTEN
Receive FIFO Time-out Interrupt Enable \n
21
1
read-write
0
Time-out interrupt Disabled
#0
1
Time-out interrupt Enabled
#1
TX_CLR
Clear Transmit FIFO Buffer\n
1
1
read-write
0
No effect
#0
1
Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software
#1
TX_INTEN
Transmit Threshold Interrupt Enable\n
3
1
read-write
0
TX threshold interrupt Disabled
#0
1
TX threshold interrupt Enabled
#1
TX_THRESHOLD
Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0.
28
3
read-write
SPI_RX0
SPI_RX0
Data Receive Register 0
0x10
read-only
n
0x0
0x0
RX
Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled, the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the receive FIFO buffer can be accessed through software by reading this register. This is a read-only register.
0
32
read-only
SPI_RX1
SPI_RX1
Data Receive Register 1
0x14
read-write
n
0x0
0x0
SPI_SSR
SPI_SSR
Slave Select Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select Function Enable (Master Only)\n
3
1
read-write
0
If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[1:0]
#0
1
If this bit is set, SPI_SS0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSR[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
#1
LTRIG_FLAG
Level Trigger Accomplish Flag\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \nNote: This bit is READ only. As the GO_BUSY bit is set to 1 by software, the LTRIG_FLAG will be cleared to 0 after 4 SPI peripheral clock periods plus 1 system clock period. In FIFO mode, this bit has no meaning.
5
1
read-write
0
Transferred bit length of one transaction does not meet the specified requirement
#0
1
Transferred bit length meets the specified requirement which defined in TX_BIT_LEN
#1
SSR
Slave Select Control Bits (Master Only)
If AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.
If the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPI_SS0/1 line at inactive state writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPI_SS0/1 is specified in SS_LVL.
Note: SPI_SS0 is defined as the slave select input in Slave mode.
0
2
read-write
SS_LTRIG
Slave Select Level Trigger Enable (Slave Only)\n
4
1
read-write
0
Slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge
#0
1
Slave select signal is level-trigger. The SS_LVL bit decides the signal is active low or active high
#1
SS_LVL
Slave Select Active Level\nThis bit defines the active status of slave select signal (SPI_SS0/1).\n
2
1
read-write
0
The slave select signal SPI_SS0/1 is active on low-level/falling-edge
#0
1
The slave select signal SPI_SS0/1 is active on high-level/rising-edge
#1
SPI_STATUS
SPI_STATUS
SPI Status Register
0x44
-1
read-write
n
0x0
0x0
IF
SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n
24
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_FIFO_COUNT
Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
12
4
read-only
RX_FULL
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[25].\n
25
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RX_INTSTS
Receive FIFO Threshold Interrupt Status (Read Only)\n
0
1
read-only
0
The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD
#1
RX_OVERRUN
Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself.
2
1
read-write
SLV_START_INTSTS
Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].\n
11
1
read-write
0
Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1
#0
1
A transaction has started in Slave 3-wire mode. It will be cleared as a transaction is done or by writing 1 to this bit
#1
TIMEOUT
Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
20
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26].\n
26
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TX_FIFO_COUNT
Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TX_FULL
Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n
27
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TX_INTSTS
Transmit FIFO Threshold Interrupt Status (Read Only)\n
4
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD
#1
SPI_TX0
SPI_TX0
Data Transmit Register 0
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bits TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: When the SPI controller is configured as a slave device and FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the transmit data register should be updated by software before setting the GO_BUSY bit to 1
0
32
write-only
SPI_TX1
SPI_TX1
Data Transmit Register 1
0x24
read-write
n
0x0
0x0
SPI_VARCLK
SPI_VARCLK
Variable Clock Pattern Register
0x34
-1
read-write
n
0x0
0x0
VARCLK
Variable Clock Pattern
This register defines the clock pattern of the SPI transfer. If the variable clock function is disabled, this setting is unmeaning. Refer to the Variable Clock Function paragraph for more detail description.
0
32
read-write
SPI3
SPI Register Map
SPI
0x0
0x0
0xC
registers
n
0x10
0x8
registers
n
0x20
0x8
registers
n
0x34
0x14
registers
n
SPI_CNTRL
SPI_CNTRL
Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CLKP
Clock Polarity\n
11
1
read-write
0
SPICLK is idle low
#0
1
SPICLK is idle high
#1
FIFO
FIFO Mode Enable
Note:
Before enabling FIFO mode, the other related settings should be set in advance.
In Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data to the transmit FIFO buffer the GO_BUSY bit will be cleared to 0 automatically when the SPI controller is in idle. If all data stored at transmit FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 and the GO_BUSY bit will be cleared to 0.
21
1
read-write
0
FIFO mode Disabled
#0
1
FIFO mode Enabled
#1
GO_BUSY
SPI Transfer Control Bit and Busy Status\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In Slave mode, this bit always returns 1 when this register is read by software. In Master mode, this bit reflects the busy or idle status of SPI.\nNote:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit.\nWhen FIFO mode is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA finishes the data transfer.
0
1
read-write
0
Data transfer stopped
#0
1
In Master mode, writing 1 to this bit to start the SPI data transfer in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master
#1
IE
Unit Transfer Interrupt Enable\n
17
1
read-write
0
SPI unit transfer interrupt Disabled
#0
1
SPI unit transfer interrupt Enabled
#1
IF
Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
LSB
Send LSB First\n
10
1
read-write
0
The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI TX0/1 register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX0/1)
#1
REORDER
Byte Reorder Function Enable\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\nIn Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval.\nThe byte reorder function is not supported when the variable serial clock function or Dual I/O mode is enabled.
19
1
read-write
0
Byte reorder function Disabled
#0
1
Byte reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SP_CYCLE
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n
24
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_FULL
Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25].\n
25
1
read-only
0
Receive FIOF buffer is not full
#0
1
Receive FIFO buffer is full
#1
RX_NEG
Receive on Negative Edge\n
1
1
read-write
0
Received data input signal is latched on the rising edge of SPICLK
#0
1
Received data input signal is latched on the falling edge of SPICLK
#1
SLAVE
Slave Mode Enable\n
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SP_CYCLE
Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\nIf the variable clock function is enabled and the transmit FIFO buffer is not empty, the minimum period of suspend interval between the successive transactions is (6.5 + SP_CYCLE) * SPICLK clock cycle.
12
4
read-write
TWOB
2-bit Mode Enable\nNote: When 2-bit mode is enabled, the serial transmitted 2-bit data are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0.
22
1
read-write
0
2-bit mode Disabled
#0
1
2-bit mode Enabled
#1
TX_BIT_LEN
Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n
3
5
read-write
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STAUTS[26].\n
26
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TX_FULL
Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27].\n
27
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TX_NEG
Transmit on Negative Edge\n
2
1
read-write
0
Transmitted data output signal is changed on the rising edge of SPICLK
#0
1
Transmitted data output signal is changed on the falling edge of SPICLK
#1
VARCLK_EN
Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is set to 1, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode).
23
1
read-write
0
SPI clock output frequency is fixed and decided only by the value of DIVIDER
#0
1
SPI clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2
#1
SPI_CNTRL2
SPI_CNTRL2
Control and Status Register 2
0x3C
-1
read-write
n
0x0
0x0
BCn
SPI Peripheral clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details.
31
1
read-write
0
Backward compatible clock configuration
#0
1
Clock configuration is not backward compatible
#1
DUAL_IO_DIR
Dual I/O Mode Direction Control\n
12
1
read-write
0
Dual Input mode
#0
1
Dual Output mode
#1
DUAL_IO_EN
Dual I/O Mode Enable\n
13
1
read-write
0
Dual I/O mode Disabled
#0
1
Dual I/O mode Enabled
#1
NOSLVSEL
Slave 3-wire Mode Enable\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI.\nNote: In Slave 3-wire mode, the SS_LTRIG, SPI_SSR[4] will be set as 1 automatically.
8
1
read-write
0
4-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLV_ABORT
Slave 3-wire Mode Abort Control\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more SPI clock input over the one transfer time in Slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software.
9
1
read-write
SLV_START_INTSTS
Slave 3-wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n
11
1
read-write
0
Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1
#0
1
A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit
#1
SSTA_INTEN
Slave 3-wire Mode Start Interrupt Enable\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.\n
10
1
read-write
0
Transaction start interrupt Disabled
#0
1
Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared
#1
SS_INT_OPT
Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n
16
1
read-write
0
As the slave select signal goes to inactive level, the IF bit will NOT be set to 1
#0
1
As the slave select signal goes to inactive level, the IF bit will be set to 1
#1
SPI_DIVIDER
SPI_DIVIDER
Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI peripheral clock, fspi_eclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. \nIf the bit of BCn, SPI_CNTRL2[31], is set to 0,\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI peripheral clock source, which is defined in the CLKSEL1 register.
0
8
read-write
DIVIDER2
Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation: \n\nIf the VARCLK_EN bit is cleared to 0, this setting is unmeaning.
16
8
read-write
SPI_DMA
SPI_DMA
SPI DMA Control Register
0x38
read-write
n
0x0
0x0
PDMA_RST
PDMA Reset\n
2
1
read-write
0
No effect
#0
1
Reset the PDMA control logic of the SPI controller. This bit will be cleared to 0 automatically
#1
RX_DMA_GO
Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware automatically after PDMA transfer is done.\nIf the software uses the receive PDMA function to access the received data of SPI and does not use the transmit PDMA function, the GO_BUSY bit should be set by software.\nEnabling FIFO mode is recommended if the software uses more than one PDMA channel to transfer data.\nIn Slave mode and when FIFO mode is disabled, if the software only uses one PDMA channel for SPI receive PDMA function and the other PDMA channels are not in use, the minimal suspend interval between two successive transactions must be larger than (9 SPI slave peripheral clock periods + 4 APB clock periods) for Edge-trigger mode or (9.5 SPI slave peripheral clock periods + 4 APB clock periods) for Level-trigger mode.
1
1
read-write
TX_DMA_GO
Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.\nIf the SPI transmit PDMA function is used to transfer data, the GO_BUSY bit should not be set to 1 by software. The PDMA control logic of SPI controller will set it automatically whenever necessary.\nIn Slave mode and when FIFO mode is disabled, the minimal suspend interval between two successive transactions must be larger than (8 SPI clock periods + 14 APB clock periods) for edge-trigger mode or (9.5 SPI clock periods + 14 APB clock periods) for level-trigger mode. If the 2-bit Transfer mode is enabled, additional 18 APB clock periods for the above conditions is required.
0
1
read-write
SPI_FIFO_CTL
SPI_FIFO_CTL
SPI FIFO Control Register
0x40
-1
read-write
n
0x0
0x0
RXOV_INTEN
Receive FIFO Overrun Interrupt Enable\n
6
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RX_CLR
Clear Receive FIFO Buffer\n
0
1
read-write
0
No effect
#0
1
Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software
#1
RX_INTEN
Receive Threshold Interrupt Enable\n
2
1
read-write
0
RX threshold interrupt Disabled
#0
1
RX threshold interrupt Enabled
#1
RX_THRESHOLD
Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0.
24
3
read-write
TIMEOUT_INTEN
Receive FIFO Time-out Interrupt Enable \n
21
1
read-write
0
Time-out interrupt Disabled
#0
1
Time-out interrupt Enabled
#1
TX_CLR
Clear Transmit FIFO Buffer\n
1
1
read-write
0
No effect
#0
1
Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software
#1
TX_INTEN
Transmit Threshold Interrupt Enable\n
3
1
read-write
0
TX threshold interrupt Disabled
#0
1
TX threshold interrupt Enabled
#1
TX_THRESHOLD
Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0.
28
3
read-write
SPI_RX0
SPI_RX0
Data Receive Register 0
0x10
read-only
n
0x0
0x0
RX
Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled, the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the receive FIFO buffer can be accessed through software by reading this register. This is a read-only register.
0
32
read-only
SPI_RX1
SPI_RX1
Data Receive Register 1
0x14
read-write
n
0x0
0x0
SPI_SSR
SPI_SSR
Slave Select Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select Function Enable (Master Only)\n
3
1
read-write
0
If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[1:0]
#0
1
If this bit is set, SPI_SS0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSR[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
#1
LTRIG_FLAG
Level Trigger Accomplish Flag\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \nNote: This bit is READ only. As the GO_BUSY bit is set to 1 by software, the LTRIG_FLAG will be cleared to 0 after 4 SPI peripheral clock periods plus 1 system clock period. In FIFO mode, this bit has no meaning.
5
1
read-write
0
Transferred bit length of one transaction does not meet the specified requirement
#0
1
Transferred bit length meets the specified requirement which defined in TX_BIT_LEN
#1
SSR
Slave Select Control Bits (Master Only)
If AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.
If the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPI_SS0/1 line at inactive state writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPI_SS0/1 is specified in SS_LVL.
Note: SPI_SS0 is defined as the slave select input in Slave mode.
0
2
read-write
SS_LTRIG
Slave Select Level Trigger Enable (Slave Only)\n
4
1
read-write
0
Slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge
#0
1
Slave select signal is level-trigger. The SS_LVL bit decides the signal is active low or active high
#1
SS_LVL
Slave Select Active Level\nThis bit defines the active status of slave select signal (SPI_SS0/1).\n
2
1
read-write
0
The slave select signal SPI_SS0/1 is active on low-level/falling-edge
#0
1
The slave select signal SPI_SS0/1 is active on high-level/rising-edge
#1
SPI_STATUS
SPI_STATUS
SPI Status Register
0x44
-1
read-write
n
0x0
0x0
IF
SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].\n
24
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_FIFO_COUNT
Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
12
4
read-only
RX_FULL
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[25].\n
25
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RX_INTSTS
Receive FIFO Threshold Interrupt Status (Read Only)\n
0
1
read-only
0
The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD
#1
RX_OVERRUN
Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself.
2
1
read-write
SLV_START_INTSTS
Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].\n
11
1
read-write
0
Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1
#0
1
A transaction has started in Slave 3-wire mode. It will be cleared as a transaction is done or by writing 1 to this bit
#1
TIMEOUT
Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
20
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26].\n
26
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TX_FIFO_COUNT
Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TX_FULL
Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n
27
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TX_INTSTS
Transmit FIFO Threshold Interrupt Status (Read Only)\n
4
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD
#1
SPI_TX0
SPI_TX0
Data Transmit Register 0
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bits TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: When the SPI controller is configured as a slave device and FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the transmit data register should be updated by software before setting the GO_BUSY bit to 1
0
32
write-only
SPI_TX1
SPI_TX1
Data Transmit Register 1
0x24
read-write
n
0x0
0x0
SPI_VARCLK
SPI_VARCLK
Variable Clock Pattern Register
0x34
-1
read-write
n
0x0
0x0
VARCLK
Variable Clock Pattern
This register defines the clock pattern of the SPI transfer. If the variable clock function is disabled, this setting is unmeaning. Refer to the Variable Clock Function paragraph for more detail description.
0
32
read-write
SYST
SYST Register Map
SYST
0x0
0x10
0xC
registers
n
CSR
SYST_CSR
SysTick Control and Status Register
0x10
read-write
n
0x0
0x0
CLKSRC
None
2
1
read-write
0
Clock source is (optional) external reference clock
#0
1
Core clock used for SysTick
#1
COUNTFLAG
Returns 1 If Timer Counted to 0 Since Last Time this Register Was Read\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register.
16
1
read-write
ENABLE
None
0
1
read-write
0
Counter Disabled
#0
1
Counter will operate in a multi-shot manner
#1
TICKINT
None
1
1
read-write
0
Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to 0 has occurred
#0
1
Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick Current Value register by a register write in software will not cause SysTick to be pended
#1
CVR
SYST_CVR
SysTick Current Value Register
0x18
read-write
n
0x0
0x0
CURRENT
Current Counter Value This Is the Value of the Counter at the Time It Is Sampled The Counter Does Not Provide Read-modify-write Protection The register is write-clear. A software write of any value will clear the register to 0. Unsupported bits RAZ (see SysTick Reload Value register).
0
24
read-write
RVR
SYST_RVR
SysTick Reload Value Register
0x14
read-write
n
0x0
0x0
RELOAD
Value to load into the Current Value register when the counter reaches 0.
0
24
read-write
TMR01
TIMER Register Map
TIMER
0x0
0x0
0x1C
registers
n
0x20
0x1C
registers
n
TCAP0
TCAP0
Timer0 Capture Data Register
0x10
read-only
n
0x0
0x0
TCAP
Timer Capture Data Register
When TEXEN (TEXCON[3] timer external pin enable) bit is set, RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select) bit is 0, and a transition on TMx_EXT pin matched the TEX_EDGE (TEXCON[2:1] timer external pin edge detect) setting, TEXIF (TEXISR[0] timer external interrupt flag) will set to 1 and the current timer counter value (TDR value) will be auto-loaded into this TCAP field.
0
24
read-only
TCAP1
TCAP1
Timer1 Capture Data Register
0x30
read-write
n
0x0
0x0
TCMPR0
TCMPR0
Timer0 Compare Register
0x4
read-write
n
0x0
0x0
TCMP
Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value, the TIF (TISR[0] timet interrupt flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if software writes a new value into TCMP field. But if timer is operating at other modes, the 24-bit up counter will restart counting and using newest TCMP value to be the timer compared value if software writes a new value into TCMP field.
0
24
read-write
TCMPR1
TCMPR1
Timer1 Compare Register
0x24
read-write
n
0x0
0x0
TCSR0
TCSR0
Timer0 Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CACT
Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\n
25
1
read-only
0
24-bit up counter is not active
#0
1
24-bit up counter is active
#1
CEN
Timer Enable Bit\n
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
CRST
Timer Reset Bit\nSetting this bit will reset the 24-bit up counter value (TDR) and also force CEN (TCSR[30] timer enable bit) to 0 if CACT (TCSR[25] timer active status bit) is 1.\n
26
1
read-write
0
No effect
#0
1
Reset 8-bit prescale counter, 24-bit up counter value and CEN bit
#1
CTB
Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source. Please refer to 6.7.4.5 for detail description.\n
24
1
read-write
0
External counter mode Disabled
#0
1
External counter mode Enabled
#1
DBGACK_TMR
ICE Debug Mode Acknowledge Disable (Write Protected)\nTIMER counter will keep going no matter CPU is held by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement Disabled
#1
IE
Interrupt Enable Bit\nIf this bit is enabled, when the timer interrupt flag (TISR[0] TIF) is set to 1, the timer interrupt signal is generated and inform to CPU.
29
1
read-write
0
Timer Interrupt Disabled
#0
1
Timer Interrupt Enabled
#1
MODE
Timer Operating Mode\n
27
2
read-write
PRESCALE
Prescale Counter\n
0
8
read-write
TDR_EN
Data Load Enable\nWhen this bit is set, timer counter value (TDR) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n
16
1
read-write
0
Timer Data Register update Disabled
#0
1
Timer Data Register update Enabled while timer counter is active
#1
WAKE_EN
Wake-up Enable\nIf this bit is set to 1, while timer interrupt flag (TISR[0] TIF) is generated to 1 and IE (TCSR[29] interrupt enable bit) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.\n
23
1
read-write
0
Wake-up trigger event Disabled if timer interrupt signal generated
#0
1
Wake-up trigger event Enabled if timer interrupt signal generated
#1
TCSR1
TCSR1
Timer1 Control and Status Register
0x20
read-write
n
0x0
0x0
TDR0
TDR0
Timer0 Data Register
0xC
read-only
n
0x0
0x0
TDR
Timer Data Register\nIf TDR_EN (TCSR[16]) is set to 1, TDR will be updated continuously to monitor 24-bit timer counter value.
0
24
read-only
TDR1
TDR1
Timer1 Data Register
0x2C
read-write
n
0x0
0x0
TEXCON0
TEXCON0
Timer0 External Control Register
0x14
read-write
n
0x0
0x0
RSTCAPSEL
Timer External Reset Counter / Capture Mode Select\n
4
1
read-write
0
Transition on TMx_EXT pin is using to save the 24-bit timer counter value (TDR value) to timer capture value (TCAP value) if TEXIF (TEXISR[0] timer external interrupt flag) is set to 1
#0
1
Transition on TMx_EXT pin is using to reset the 24-bit timer counter
#1
TCDB
Timer Counter Pin De-bounce Enable\nIf this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
7
1
read-write
0
TMx pin de-bounce Disabled
#0
1
TMx pin de-bounce Enabled
#1
TEXDB
Timer External Capture Pin De-bounce Enable \nIf this bit is enabled, the edge detection of TMx_EXT pin is detected with de-bounce circuit.
6
1
read-write
0
TMx_EXT pin de-bounce Disabled
#0
1
TMx_EXT pin de-bounce Enabled
#1
TEXEN
Timer External Pin Enable \nThis bit enables the RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select ) function on the TMx_EXT pin. \n
3
1
read-write
0
RSTCAPSEL function of TMx_EXT pin will be ignored
#0
1
RSTCAPSEL function of TMx_EXT pin is active
#1
TEXIEN
Timer External Interrupt Enable\n
5
1
read-write
0
TMx_EXT pin detection Interrupt Disabled
#0
1
TMx_EXT pin detection Interrupt Enabled
#1
TEX_EDGE
Timer External Pin Edge Detect\n
1
2
read-write
0
A 1 to 0 transition on TMx_EXT pin will be detected
#00
1
A 0 to 1 transition on TMx_EXT pin will be detected
#01
2
Either 1 to 0 or 0 to 1 transition on TMx_EXT pin will be detected
#10
3
Reserved
#11
TX_PHASE
Timer External Count Phase \nThis bit indicates the detection phase of external counting pin.\n
0
1
read-write
0
A falling edge of external counting pin will be counted
#0
1
A rising edge of external counting pin will be counted
#1
TEXCON1
TEXCON1
Timer1 External Control Register
0x34
read-write
n
0x0
0x0
TEXISR0
TEXISR0
Timer0 External Interrupt Status Register
0x18
read-write
n
0x0
0x0
TEXIF
Timer External Interrupt Flag
This bit indicates the timer external interrupt flag status.
When TEXEN (TEXCON[3] timer external pin enable) bit is set, RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select) bit is 0, and a transition on TMx_EXT pin matched the TEX_EDGE (TEXCON[2:1] timer external pin edge detect) setting, this bit will set to 1 by hardware.
This bit is cleared by writing 1 to it through software.
0
1
read-write
TEXISR1
TEXISR1
Timer1 External Interrupt Status Register
0x38
read-write
n
0x0
0x0
TISR0
TISR0
Timer0 Interrupt Status Register
0x8
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer.\nAnd this bit is set by hardware when the timer counter value) matches the timer compared value (TCMP value). It is cleared by writing 1 to it through software.
0
1
read-write
TWF
Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nIt must be cleared by writing 1 to it through software.
1
1
read-write
0
Timer does not cause CPU wake-up
#0
1
CPU wake-up from Idle or power-down mode if timer interrupt signal generated
#1
TISR1
TISR1
Timer1 Interrupt Status Register
0x28
read-write
n
0x0
0x0
TMR23
TIMER Register Map
TIMER
0x0
0x0
0x1C
registers
n
0x20
0x1C
registers
n
TCAP2
TCAP2
Timer2 Capture Data Register
0x10
read-only
n
0x0
0x0
TCAP
Timer Capture Data Register
When TEXEN (TEXCON[3] timer external pin enable) bit is set, RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select) bit is 0, and a transition on TMx_EXT pin matched the TEX_EDGE (TEXCON[2:1] timer external pin edge detect) setting, TEXIF (TEXISR[0] timer external interrupt flag) will set to 1 and the current timer counter value (TDR value) will be auto-loaded into this TCAP field.
0
24
read-only
TCAP3
TCAP3
Timer3 Capture Data Register
0x30
read-write
n
0x0
0x0
TCMPR2
TCMPR2
Timer2 Compare Register
0x4
read-write
n
0x0
0x0
TCMP
Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value, the TIF (TISR[0] timet interrupt flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if software writes a new value into TCMP field. But if timer is operating at other modes, the 24-bit up counter will restart counting and using newest TCMP value to be the timer compared value if software writes a new value into TCMP field.
0
24
read-write
TCMPR3
TCMPR3
Timer3 Compare Register
0x24
read-write
n
0x0
0x0
TCSR2
TCSR2
Timer2 Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CACT
Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\n
25
1
read-only
0
24-bit up counter is not active
#0
1
24-bit up counter is active
#1
CEN
Timer Enable Bit\n
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
CRST
Timer Reset Bit\nSetting this bit will reset the 24-bit up counter value (TDR) and also force CEN (TCSR[30] timer enable bit) to 0 if CACT (TCSR[25] timer active status bit) is 1.\n
26
1
read-write
0
No effect
#0
1
Reset 8-bit prescale counter, 24-bit up counter value and CEN bit
#1
CTB
Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source. Please refer to 6.7.4.5 for detail description.\n
24
1
read-write
0
External counter mode Disabled
#0
1
External counter mode Enabled
#1
DBGACK_TMR
ICE Debug Mode Acknowledge Disable (Write Protected)\nTIMER counter will keep going no matter CPU is held by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement Disabled
#1
IE
Interrupt Enable Bit\nIf this bit is enabled, when the timer interrupt flag (TISR[0] TIF) is set to 1, the timer interrupt signal is generated and inform to CPU.
29
1
read-write
0
Timer Interrupt Disabled
#0
1
Timer Interrupt Enabled
#1
MODE
Timer Operating Mode\n
27
2
read-write
PRESCALE
Prescale Counter\n
0
8
read-write
TDR_EN
Data Load Enable\nWhen this bit is set, timer counter value (TDR) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n
16
1
read-write
0
Timer Data Register update Disabled
#0
1
Timer Data Register update Enabled while timer counter is active
#1
WAKE_EN
Wake-up Enable\nIf this bit is set to 1, while timer interrupt flag (TISR[0] TIF) is generated to 1 and IE (TCSR[29] interrupt enable bit) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.\n
23
1
read-write
0
Wake-up trigger event Disabled if timer interrupt signal generated
#0
1
Wake-up trigger event Enabled if timer interrupt signal generated
#1
TCSR3
TCSR3
Timer3 Control and Status Register
0x20
read-write
n
0x0
0x0
TDR2
TDR2
Timer2 Data Register
0xC
read-only
n
0x0
0x0
TDR
Timer Data Register\nIf TDR_EN (TCSR[16]) is set to 1, TDR will be updated continuously to monitor 24-bit timer counter value.
0
24
read-only
TDR3
TDR3
Timer3 Data Register
0x2C
read-write
n
0x0
0x0
TEXCON2
TEXCON2
Timer2 External Control Register
0x14
read-write
n
0x0
0x0
RSTCAPSEL
Timer External Reset Counter / Capture Mode Select\n
4
1
read-write
0
Transition on TMx_EXT pin is using to save the 24-bit timer counter value (TDR value) to timer capture value (TCAP value) if TEXIF (TEXISR[0] timer external interrupt flag) is set to 1
#0
1
Transition on TMx_EXT pin is using to reset the 24-bit timer counter
#1
TCDB
Timer Counter Pin De-bounce Enable\nIf this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
7
1
read-write
0
TMx pin de-bounce Disabled
#0
1
TMx pin de-bounce Enabled
#1
TEXDB
Timer External Capture Pin De-bounce Enable \nIf this bit is enabled, the edge detection of TMx_EXT pin is detected with de-bounce circuit.
6
1
read-write
0
TMx_EXT pin de-bounce Disabled
#0
1
TMx_EXT pin de-bounce Enabled
#1
TEXEN
Timer External Pin Enable \nThis bit enables the RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select ) function on the TMx_EXT pin. \n
3
1
read-write
0
RSTCAPSEL function of TMx_EXT pin will be ignored
#0
1
RSTCAPSEL function of TMx_EXT pin is active
#1
TEXIEN
Timer External Interrupt Enable\n
5
1
read-write
0
TMx_EXT pin detection Interrupt Disabled
#0
1
TMx_EXT pin detection Interrupt Enabled
#1
TEX_EDGE
Timer External Pin Edge Detect\n
1
2
read-write
0
A 1 to 0 transition on TMx_EXT pin will be detected
#00
1
A 0 to 1 transition on TMx_EXT pin will be detected
#01
2
Either 1 to 0 or 0 to 1 transition on TMx_EXT pin will be detected
#10
3
Reserved
#11
TX_PHASE
Timer External Count Phase \nThis bit indicates the detection phase of external counting pin.\n
0
1
read-write
0
A falling edge of external counting pin will be counted
#0
1
A rising edge of external counting pin will be counted
#1
TEXCON3
TEXCON3
Timer3 External Control Register
0x34
read-write
n
0x0
0x0
TEXISR2
TEXISR2
Timer2 External Interrupt Status Register
0x18
read-write
n
0x0
0x0
TEXIF
Timer External Interrupt Flag
This bit indicates the timer external interrupt flag status.
When TEXEN (TEXCON[3] timer external pin enable) bit is set, RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select) bit is 0, and a transition on TMx_EXT pin matched the TEX_EDGE (TEXCON[2:1] timer external pin edge detect) setting, this bit will set to 1 by hardware.
This bit is cleared by writing 1 to it through software.
0
1
read-write
TEXISR3
TEXISR3
Timer3 External Interrupt Status Register
0x38
read-write
n
0x0
0x0
TISR2
TISR2
Timer2 Interrupt Status Register
0x8
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer.\nAnd this bit is set by hardware when the timer counter value) matches the timer compared value (TCMP value). It is cleared by writing 1 to it through software.
0
1
read-write
TWF
Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nIt must be cleared by writing 1 to it through software.
1
1
read-write
0
Timer does not cause CPU wake-up
#0
1
CPU wake-up from Idle or power-down mode if timer interrupt signal generated
#1
TISR3
TISR3
Timer3 Interrupt Status Register
0x28
read-write
n
0x0
0x0
UART0
UART Register Map
UART
0x0
0x0
0x3C
registers
n
UA_ALT_CSR
UA_ALT_CSR
UART Alternate Control/Status Register
0x2C
read-write
n
0x0
0x0
ADDR_MATCH
Address Match Value Register \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
LIN_BKFL
UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is UA_LIN_BKFL + 1\n
0
4
read-write
LIN_RX_EN
LIN RX Enable\n
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LIN_TX_EN
LIN TX Break Mode Enable\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
LIN TX Break mode Disabled
#0
1
LIN TX Break mode Enabled
#1
RS485_AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485_ADD_EN
RS-485 Address Detection Enable \nThis bit is used to enable RS-485 Address Detection mode. \nNote: This field is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
RS485_AUD
RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation mode (AUO) Disabled
#0
1
RS-485 Auto Direction Operation mode (AUO) Enabled
#1
RS485_NMM
RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UA_BAUD
UA_BAUD
UART Baud Rate Divisor Register
0x24
-1
read-write
n
0x0
0x0
BRD
Baud Rate Divider\nThe field indicates the baud rate divider
0
16
read-write
DIVIDER_X
Divider X\n
24
4
read-write
DIV_X_EN
Divider X Enable\nRefer to Table 611 for more information.\nNote: In IrDA mode, this bit must disable.
29
1
read-write
0
Divider X Disabled (the equation of M = 16)
#0
1
Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8)
#1
DIV_X_ONE
Divider X Equal to 1\nRefer to Table 611 for more information.
28
1
read-write
0
Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8)
#0
1
Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 3)
#1
UA_FCR
UA_FCR
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt (INT_RDA) Trigger Level\n
4
4
read-write
RFR
RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
RTS_TRI_LEV
NRTS Trigger Level for Auto-flow Control Use (Not Available in UART2 Channel)
16
4
read-write
RX_DIS
Receiver Disable Register\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
TFR
TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UA_FSR
UA_FSR
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
BIF
Break Interrupt Flag (Read Only)
This bit is set to logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but can be cleared by writing '1' to it.
6
1
read-only
FEF
Framing Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0), and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but can be cleared by writing '1' to it.
5
1
read-only
PEF
Parity Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but can be cleared by writing '1' to it.
4
1
read-only
RS485_ADD_DETF
RS-485 Address Byte Detection Flag (Read Only) \nNote: This field is used for RS-485 function mode.\nNote: This bit is read only, but can be cleared by writing '1' to it.
3
1
read-only
RX_EMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
RX_FULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO is full or not.\nThis bit is set when the number of usage in RX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2), otherwise is cleared by hardware.
15
1
read-only
RX_OVER_IF
RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 64/16/16 bytes of UART0/UART1/UART2, this bit will be set.\nNote: This bit is read only, but can be cleared by writing '1' to it.
0
1
read-only
RX_POINTER
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, then RX_POINTER increases one. When one byte of RX FIFO is read by CPU, then RX_POINTER decreases one.\nThe Maximum value shown in RX_POINTER is 63/15/15 (UART0/UART1/UART2). When the using level of RX FIFO Buffer equal to 64/16/16, the RX_FULL bit is set to 1 and RX_POINTER will show 0. As one byte of RX FIFO is read by CPU, the RX_FULL bit is cleared to 0 and RX_POINTER will show 63/15/15 (UART0/UART1/UART2).
8
6
read-only
TE_FLAG
Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
TX_EMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO is empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty).
22
1
read-only
TX_FULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO is full or not.\nThis bit is set when the number of usage in TX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2), otherwise is cleared by hardware.
23
1
read-only
TX_OVER_IF
TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1.\nNote: This bit is read only, but can be cleared by writing '1' to it.
24
1
read-only
TX_POINTER
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, then TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, then TX_POINTER decreases one.\nThe Maximum value shown in TX_POINTER is 63/15/15 (UART0/UART1/UART2). When the using level of TX FIFO Buffer equal to 64/16/16, the TX_FULL bit is set to 1 and TX_POINTER will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TX_FULL bit is cleared to 0 and TX_POINTER will show 63/15/15 (UART0/UART1/UART2).
16
6
read-only
UA_FUN_SEL
UA_FUN_SEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUN_SEL
Function Select Enable\n
0
2
read-write
0
UART function Enabled
#00
1
LIN function Enabled
#01
2
IrDA function Enabled
#10
3
RS-485 function Enabled
#11
UA_IER
UA_IER
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
AUTO_CTS_EN
NCTS Auto Flow Control Enable (Not Available in UART2 Channel)\nWhen nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto flow control Disabled
#0
1
nCTS auto flow control Enabled
#1
AUTO_RTS_EN
NRTS Auto Flow Control Enable (Not Available in UART2 Channel)\nWhen nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the UA_FCR [RTS_TRI_LEV], the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto flow control Disabled
#0
1
nRTS auto flow control Enabled
#1
BUF_ERR_IEN
Buffer Error Interrupt Enable\n
5
1
read-write
0
INT_BUF_ERR Masked off
#0
1
INT_BUF_ERR Enabled
#1
DMA_RX_EN
RX DMA Enable (Not Available in UART2 Channel)\nThis bit can enable or disable RX DMA service.\n
15
1
read-write
0
RX DMA Disabled
#0
1
RX DMA Enabled
#1
DMA_TX_EN
TX DMA Enable (Not Available in UART2 Channel)\nThis bit can enable or disable TX DMA service.\n
14
1
read-write
0
TX DMA Disabled
#0
1
TX DMA Enabled
#1
LIN_IEN
LIN Bus Interrupt Enable\nNote: This field is used for LIN function mode.
8
1
read-write
0
Lin bus interrupt Disabled
#0
1
Lin bus interrupt Enabled
#1
MODEM_IEN
Modem Status Interrupt Enable (Not Available in UART2 Channel)\n
3
1
read-write
0
INT_MODEM Masked off
#0
1
INT_MODEM Enabled
#1
RDA_IEN
Receive Data Available Interrupt Enable\n
0
1
read-write
0
INT_RDA Masked off
#0
1
INT_RDA Enabled
#1
RLS_IEN
Receive Line Status Interrupt Enable \n
2
1
read-write
0
INT_RLS Masked off
#0
1
INT_RLS Enabled
#1
THRE_IEN
Transmit Holding Register Empty Interrupt Enable\n
1
1
read-write
0
INT_THRE Masked off
#0
1
INT_THRE Enabled
#1
TIME_OUT_EN
Time-out Counter Enable\n
11
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TOUT_IEN
RX Time-out Interrupt Enable\n
4
1
read-write
0
INT_TOUT Masked off
#0
1
INT_TOUT Enabled
#1
WAKE_EN
UART Wake-up Function Enable (Not Available in UART2 Channel)\n
6
1
read-write
0
UART wake-up function Disabled
#0
1
UART wake-up function Enabled, when the chip is in Power-down mode, an external nCTS change will wake-up chip from Power-down mode
#1
UA_IRCR
UA_IRCR
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
INV_RX
INV_RX\n
6
1
read-write
0
No inversion
#0
1
Inverse RX input signal
#1
INV_TX
INV_TX\n
5
1
read-write
0
No inversion
#0
1
Inverse TX output signal
#1
TX_SELECT
TX_SELECT\n
1
1
read-write
0
IrDA receiver Enabled
#0
1
IrDA transmitter Enabled
#1
UA_ISR
UA_ISR
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
BUF_ERR_IF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.
5
1
read-only
BUF_ERR_INT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.\n
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HW_BUF_ERR_IF
In DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared.
21
1
read-only
HW_BUF_ERR_INT
In DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and HW_BUF_ERR_IF are both set to 1.\n
29
1
read-only
0
No buffer error interrupt is generated in DMA mode
#0
1
Buffer error interrupt is generated in DMA mode
#1
HW_MODEM_IF
In DMA Mode, MODEM Interrupt Flag (Read Only) (Not Available in UART2 Channel)\nNote: This bit is read only and reset to 0 when the bit DCTSF is cleared by writing 1 on DCTSF.
19
1
read-only
HW_MODEM_INT
In DMA Mode, MODEM Status Interrupt Indicator (Read Only) (Not Available in UART2 Channel)\nThis bit is set if MODEM_IEN and HW_MODEM_IF are both set to 1.\n
27
1
read-only
0
No Modem interrupt is generated in DMA mode
#0
1
Modem interrupt is generated in DMA mode
#1
HW_RLS_IF
In DMA Mode, Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
18
1
read-only
HW_RLS_INT
In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLS_IEN and HW_RLS_IF are both set to 1.\n
26
1
read-only
0
No RLS interrupt is generated in DMA mode
#0
1
RLS interrupt is generated in DMA mode
#1
HW_TOUT_IF
In DMA Mode, Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.
20
1
read-only
HW_TOUT_INT
In DMA Mode, Time-out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and HW_TOUT_IF are both set to 1.\n
28
1
read-only
0
No Tout interrupt is generated in DMA mode
#0
1
Tout interrupt is generated in DMA mode
#1
LIN_IF
LIN Bus Flag (Read Only)\nNote: This bit is cleared when LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPENR_F and LINS_HERR_F all are cleared
7
1
read-only
LIN_INT
LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN and LIN _IF are both set to 1.\n
15
1
read-only
0
No LIN Bus interrupt is generated
#0
1
The LIN Bus interrupt is generated
#1
MODEM_IF
MODEM Interrupt Flag (Read Only) (Not Available in UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.
3
1
read-only
MODEM_INT
MODEM Status Interrupt Indicator (Read Only) (Not Available in UART2 Channel)\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.\n
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDA_IF
Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
0
1
read-only
RDA_INT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.\n
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLS_IF
Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.
Note: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
2
1
read-only
RLS_INT
Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN and RLS_IF are both set to 1.\n
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
THRE_IF
Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty).
1
1
read-only
THRE_INT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.\n
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TOUT_IF
Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.
4
1
read-only
TOUT_INT
Time-out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and TOUT_IF are both set to 1.\n
12
1
read-only
0
No Tout interrupt is generated
#0
1
Tout interrupt is generated
#1
UA_LCR
UA_LCR
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.
6
1
read-write
EPE
Even Parity Enable\nThis bit has effect only when PBE (UA_LCR[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of STOP Bit
2
1
read-write
0
One STOP bit is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 STOP bit is generated in the transmitted data. When select 6-,7- and 8-bti word length, 2 STOP bit is generated in the transmitted data
#1
PBE
Parity Bit Enable\n
3
1
read-write
0
No parity bit
#0
1
Parity bit is generated on each outgoing character and is checked on each incoming data
#1
SPE
Stick Parity Enable\n
5
1
read-write
0
Stick parity Disabled
#0
1
If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UA_LCR[3]) is 1 and EBE (UA_LCR[4]) is 0 then the parity bit is transmitted and checked as 1
#1
WLS
Word Length Selection\n
0
2
read-write
UA_LIN_CTL
UA_LIN_CTL
UART LIN Control Register
0x34
-1
read-write
n
0x0
0x0
BIT_ERR_EN
Bit Error Detect Enable\n
12
1
read-write
0
Bit error detection function Disabled
#0
1
Bit error detection Enabled
#1
LINS_ARS_EN
LIN Slave Automatic Resynchronization Mode Enable\nNote2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (UA_BAUD [DIV_X_EN] and UA_BAUD [DIV_X_ONE] must be 1).\nNote3: The control and interactions of this field are explained in character 6.12.5.4 (Slave mode with automatic resynchronization).
2
1
read-write
0
LIN automatic resynchronization Disabled
#0
1
LIN automatic resynchronization Enabled
#1
LINS_DUM_EN
LIN Slave Divider Update Method Enable\nNote2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) \nNote3: The control and interactions of this field are explained in character 6.12.5.4 (Slave mode with automatic resynchronization).
3
1
read-write
0
UA_BAUD is updated as soon as UA_BAUD is writing by software (if no automatic resynchronization update occurs at the same time)
#0
1
UA_BAUD is updated at the next received character. User must set the bit before checksum reception
#1
LINS_EN
LIN Slave Mode Enable\n
0
1
read-write
0
LIN slave mode Disabled
#0
1
LIN slave mode Enabled
#1
LINS_HDET_EN
LIN Slave Header Detection Enable\n
1
1
read-write
0
LIN slave header detection Disabled
#0
1
LIN slave header detection Enabled
#1
LIN_BKDET_EN
LIN Break Detection Enable\n
10
1
read-write
0
Disable LIN break detection
#0
1
Enable LIN break detection
#1
LIN_BKFL
LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of UA_ALT_CSR [LIN_BKFL], User can read/write it by setting UA_ALT_CSR [LIN_BKFL] or UA_LIN_CTL [LIN_BKFL].\nNote2: This break field length is LIN_BKFL + 1.\n
16
4
read-write
LIN_BS_LEN
LIN Break/Sync Delimiter Length\n\nNote: This bit used for LIN master to sending header field.
20
2
read-write
0
The LIN break/sync delimiter length is 1 bit time
#00
2
The LIN break/sync delimiter length is 2 bit time.\nThe LIN break/sync delimiter length is 3 bit time
#10
3
The LIN break/sync delimiter length is 4 bit time
#11
LIN_HEAD_SEL
LIN Header Select\n
22
2
read-write
0
The LIN header includes break field
#00
1
The LIN header includes break field and sync field
#01
2
The LIN header includes break field , sync field and frame ID field
#10
3
Reserved
#11
LIN_IDPEN
LIN ID Parity Enable\n
9
1
read-write
0
LIN frame ID parity Disabled
#0
1
LIN frame ID parity Enabled
#1
LIN_MUTE_EN
LIN Mute Mode Enable\nNote: The exit from mute mode condition and each control and interactions of this field are explained in character 6.12.5.4 (LIN slave mode).
4
1
read-write
0
LIN mute mode Disabled
#0
1
LIN mute mode Enabled
#1
LIN_PID
LIN PID Register\nThis field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on UA_LIN_CTL [LIN_IDPEN]. \n\nNote1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first)\nNote2: This field can be used for LIN master mode or slave mode.
24
8
read-write
LIN_RX_DIS
None
11
1
read-write
0
Error detection function Disabled
#0
1
Bit error detection Enabled
#1
LIN_SHD
LIN TX Send Header Enable
The LIN TX header can be break field or break and sync field or break, sync and frame ID field , it is depend on setting LIN_HEAD_SEL register.
Note1: These registers are shadow registers of UA_ALT_CSR [LIN_SHD] user can read/write it by setting UA_ALT_CSR [LIN_SHD] or UA_LIN_CTL [LIN_SHD].
Note2: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by LIN_HEAD_SEL field) transfer operation finished, this bit will be cleared automatically.
8
1
read-write
0
Send LIN TX header Disabled
#0
1
Send LIN TX header Enabled
#1
UA_LIN_SR
UA_LIN_SR
UART LIN Status Register
0x38
read-write
n
0x0
0x0
BIT_ERR_F
Bit Error Detect Status Flag (Read Only)\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BIT_ERR_F will be set.\n
9
1
read-only
LINS_HDET_F
LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\n
0
1
read-only
0
LIN header not detected
#0
1
LIN header detected (break + sync + frame ID)
#1
LINS_HERR_F
LIN Slave Header Error Flag (Read Only)
This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include break delimiter is too short , frame error in sync field or Identifier field , sync field data is not 0x55 in Non-Automatic Resynchronization mode , sync field deviation error with Automatic Resynchronization mode , sync field measure time-out with Automatic Resynchronization mode and LIN header reception time-out .
1
1
read-only
0
LIN header error not detected
#0
1
LIN header error detected
#1
LINS_IDPERR_F
LIN Slave ID Parity Error Flag (Read Only)\nThis bit is set by hardware when receipted frame ID parity is not correct.\n
2
1
read-only
0
No active
#0
1
Receipted frame ID parity is not correct
#1
LINS_SYNC_F
LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit is read only, but it can be cleared by writing 1 to it.\nNote3: When writing 1 to it, hardware will reload the initial baud-rate and re-search a new frame header.
3
1
read-write
0
The current character is not at LIN sync state
#0
1
The current character is at LIN sync state
#1
LIN_BKDET_F
LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: This bit is only valid when enable LIN break detection function (UA_ALT_CSR [LIN_BKDET_EN])
8
1
read-only
0
LIN break not detected
#0
1
LIN break detected
#1
UA_MCR
UA_MCR
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
LEV_RTS
NRTS Trigger Level (Not Available in UART2 Channel)\nThis bit can change the nRTS trigger level.\n
9
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
RTS
NRTS (Request-to-send) Signal (Not Available in UART2 Channel)\n
1
1
read-write
0
Drive nRTS pin to logic 1 (If the LEV_RTS set to low level triggered).\nDrive nRTS pin to logic 0 (If the LEV_RTS set to high level triggered)
#0
1
Drive nRTS pin to logic 0 (If the LEV_RTS set to low level triggered).\nDrive nRTS pin to logic 1 (If the LEV_RTS set to high level triggered)
#1
RTS_ST
NRTS Pin State (Read Only) (Not Available in UART2 Channel)\nThis bit is the output pin status of nRTS.
13
1
read-only
UA_MSR
UA_MSR
UART Modem Status Register
0x14
-1
read-write
n
0x0
0x0
CTS_ST
NCTS Pin Status (Read Only) (Not Available in UART2 Channel)\nThis bit is the pin status of nCTS.
4
1
read-only
DCTSF
Detect NCTS State Change Flag (Read Only) (Not Available in UART2 Channel)\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1.\nWrite 1 to clear this bit to 0
0
1
read-only
LEV_CTS
NCTS Trigger Level (Not Available in UART2 Channel)\nThis bit can change the nCTS trigger level.\n
8
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
UA_RBR
UA_RBR
UART Receive Buffer Register
0x0
read-only
n
0x0
0x0
RBR
Receive Buffer Register (Read Only)\nBy reading this register, the UART will return an 8-bit data received from UART_RXD pin (LSB first).
0
8
read-only
UA_THR
UA_THR
UART Transmit Holding Register
UA_RBR
0x0
write-only
n
0x0
0x0
THR
Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the UART_TXD pin (LSB first).
0
8
write-only
UA_TOR
UA_TOR
UART Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit.
8
8
read-write
TOIC
Time-out Interrupt Comparator\n
0
8
read-write
UART1
UART Register Map
UART
0x0
0x0
0x3C
registers
n
UA_ALT_CSR
UA_ALT_CSR
UART Alternate Control/Status Register
0x2C
read-write
n
0x0
0x0
ADDR_MATCH
Address Match Value Register \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
LIN_BKFL
UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is UA_LIN_BKFL + 1\n
0
4
read-write
LIN_RX_EN
LIN RX Enable\n
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LIN_TX_EN
LIN TX Break Mode Enable\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
LIN TX Break mode Disabled
#0
1
LIN TX Break mode Enabled
#1
RS485_AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485_ADD_EN
RS-485 Address Detection Enable \nThis bit is used to enable RS-485 Address Detection mode. \nNote: This field is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
RS485_AUD
RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation mode (AUO) Disabled
#0
1
RS-485 Auto Direction Operation mode (AUO) Enabled
#1
RS485_NMM
RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UA_BAUD
UA_BAUD
UART Baud Rate Divisor Register
0x24
-1
read-write
n
0x0
0x0
BRD
Baud Rate Divider\nThe field indicates the baud rate divider
0
16
read-write
DIVIDER_X
Divider X\n
24
4
read-write
DIV_X_EN
Divider X Enable\nRefer to Table 611 for more information.\nNote: In IrDA mode, this bit must disable.
29
1
read-write
0
Divider X Disabled (the equation of M = 16)
#0
1
Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8)
#1
DIV_X_ONE
Divider X Equal to 1\nRefer to Table 611 for more information.
28
1
read-write
0
Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8)
#0
1
Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 3)
#1
UA_FCR
UA_FCR
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt (INT_RDA) Trigger Level\n
4
4
read-write
RFR
RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
RTS_TRI_LEV
NRTS Trigger Level for Auto-flow Control Use (Not Available in UART2 Channel)
16
4
read-write
RX_DIS
Receiver Disable Register\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
TFR
TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UA_FSR
UA_FSR
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
BIF
Break Interrupt Flag (Read Only)
This bit is set to logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but can be cleared by writing '1' to it.
6
1
read-only
FEF
Framing Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0), and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but can be cleared by writing '1' to it.
5
1
read-only
PEF
Parity Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but can be cleared by writing '1' to it.
4
1
read-only
RS485_ADD_DETF
RS-485 Address Byte Detection Flag (Read Only) \nNote: This field is used for RS-485 function mode.\nNote: This bit is read only, but can be cleared by writing '1' to it.
3
1
read-only
RX_EMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
RX_FULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO is full or not.\nThis bit is set when the number of usage in RX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2), otherwise is cleared by hardware.
15
1
read-only
RX_OVER_IF
RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 64/16/16 bytes of UART0/UART1/UART2, this bit will be set.\nNote: This bit is read only, but can be cleared by writing '1' to it.
0
1
read-only
RX_POINTER
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, then RX_POINTER increases one. When one byte of RX FIFO is read by CPU, then RX_POINTER decreases one.\nThe Maximum value shown in RX_POINTER is 63/15/15 (UART0/UART1/UART2). When the using level of RX FIFO Buffer equal to 64/16/16, the RX_FULL bit is set to 1 and RX_POINTER will show 0. As one byte of RX FIFO is read by CPU, the RX_FULL bit is cleared to 0 and RX_POINTER will show 63/15/15 (UART0/UART1/UART2).
8
6
read-only
TE_FLAG
Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
TX_EMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO is empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty).
22
1
read-only
TX_FULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO is full or not.\nThis bit is set when the number of usage in TX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2), otherwise is cleared by hardware.
23
1
read-only
TX_OVER_IF
TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1.\nNote: This bit is read only, but can be cleared by writing '1' to it.
24
1
read-only
TX_POINTER
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, then TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, then TX_POINTER decreases one.\nThe Maximum value shown in TX_POINTER is 63/15/15 (UART0/UART1/UART2). When the using level of TX FIFO Buffer equal to 64/16/16, the TX_FULL bit is set to 1 and TX_POINTER will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TX_FULL bit is cleared to 0 and TX_POINTER will show 63/15/15 (UART0/UART1/UART2).
16
6
read-only
UA_FUN_SEL
UA_FUN_SEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUN_SEL
Function Select Enable\n
0
2
read-write
0
UART function Enabled
#00
1
LIN function Enabled
#01
2
IrDA function Enabled
#10
3
RS-485 function Enabled
#11
UA_IER
UA_IER
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
AUTO_CTS_EN
NCTS Auto Flow Control Enable (Not Available in UART2 Channel)\nWhen nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto flow control Disabled
#0
1
nCTS auto flow control Enabled
#1
AUTO_RTS_EN
NRTS Auto Flow Control Enable (Not Available in UART2 Channel)\nWhen nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the UA_FCR [RTS_TRI_LEV], the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto flow control Disabled
#0
1
nRTS auto flow control Enabled
#1
BUF_ERR_IEN
Buffer Error Interrupt Enable\n
5
1
read-write
0
INT_BUF_ERR Masked off
#0
1
INT_BUF_ERR Enabled
#1
DMA_RX_EN
RX DMA Enable (Not Available in UART2 Channel)\nThis bit can enable or disable RX DMA service.\n
15
1
read-write
0
RX DMA Disabled
#0
1
RX DMA Enabled
#1
DMA_TX_EN
TX DMA Enable (Not Available in UART2 Channel)\nThis bit can enable or disable TX DMA service.\n
14
1
read-write
0
TX DMA Disabled
#0
1
TX DMA Enabled
#1
LIN_IEN
LIN Bus Interrupt Enable\nNote: This field is used for LIN function mode.
8
1
read-write
0
Lin bus interrupt Disabled
#0
1
Lin bus interrupt Enabled
#1
MODEM_IEN
Modem Status Interrupt Enable (Not Available in UART2 Channel)\n
3
1
read-write
0
INT_MODEM Masked off
#0
1
INT_MODEM Enabled
#1
RDA_IEN
Receive Data Available Interrupt Enable\n
0
1
read-write
0
INT_RDA Masked off
#0
1
INT_RDA Enabled
#1
RLS_IEN
Receive Line Status Interrupt Enable \n
2
1
read-write
0
INT_RLS Masked off
#0
1
INT_RLS Enabled
#1
THRE_IEN
Transmit Holding Register Empty Interrupt Enable\n
1
1
read-write
0
INT_THRE Masked off
#0
1
INT_THRE Enabled
#1
TIME_OUT_EN
Time-out Counter Enable\n
11
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TOUT_IEN
RX Time-out Interrupt Enable\n
4
1
read-write
0
INT_TOUT Masked off
#0
1
INT_TOUT Enabled
#1
WAKE_EN
UART Wake-up Function Enable (Not Available in UART2 Channel)\n
6
1
read-write
0
UART wake-up function Disabled
#0
1
UART wake-up function Enabled, when the chip is in Power-down mode, an external nCTS change will wake-up chip from Power-down mode
#1
UA_IRCR
UA_IRCR
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
INV_RX
INV_RX\n
6
1
read-write
0
No inversion
#0
1
Inverse RX input signal
#1
INV_TX
INV_TX\n
5
1
read-write
0
No inversion
#0
1
Inverse TX output signal
#1
TX_SELECT
TX_SELECT\n
1
1
read-write
0
IrDA receiver Enabled
#0
1
IrDA transmitter Enabled
#1
UA_ISR
UA_ISR
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
BUF_ERR_IF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.
5
1
read-only
BUF_ERR_INT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.\n
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HW_BUF_ERR_IF
In DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared.
21
1
read-only
HW_BUF_ERR_INT
In DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and HW_BUF_ERR_IF are both set to 1.\n
29
1
read-only
0
No buffer error interrupt is generated in DMA mode
#0
1
Buffer error interrupt is generated in DMA mode
#1
HW_MODEM_IF
In DMA Mode, MODEM Interrupt Flag (Read Only) (Not Available in UART2 Channel)\nNote: This bit is read only and reset to 0 when the bit DCTSF is cleared by writing 1 on DCTSF.
19
1
read-only
HW_MODEM_INT
In DMA Mode, MODEM Status Interrupt Indicator (Read Only) (Not Available in UART2 Channel)\nThis bit is set if MODEM_IEN and HW_MODEM_IF are both set to 1.\n
27
1
read-only
0
No Modem interrupt is generated in DMA mode
#0
1
Modem interrupt is generated in DMA mode
#1
HW_RLS_IF
In DMA Mode, Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
18
1
read-only
HW_RLS_INT
In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLS_IEN and HW_RLS_IF are both set to 1.\n
26
1
read-only
0
No RLS interrupt is generated in DMA mode
#0
1
RLS interrupt is generated in DMA mode
#1
HW_TOUT_IF
In DMA Mode, Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.
20
1
read-only
HW_TOUT_INT
In DMA Mode, Time-out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and HW_TOUT_IF are both set to 1.\n
28
1
read-only
0
No Tout interrupt is generated in DMA mode
#0
1
Tout interrupt is generated in DMA mode
#1
LIN_IF
LIN Bus Flag (Read Only)\nNote: This bit is cleared when LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPENR_F and LINS_HERR_F all are cleared
7
1
read-only
LIN_INT
LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN and LIN _IF are both set to 1.\n
15
1
read-only
0
No LIN Bus interrupt is generated
#0
1
The LIN Bus interrupt is generated
#1
MODEM_IF
MODEM Interrupt Flag (Read Only) (Not Available in UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.
3
1
read-only
MODEM_INT
MODEM Status Interrupt Indicator (Read Only) (Not Available in UART2 Channel)\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.\n
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDA_IF
Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
0
1
read-only
RDA_INT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.\n
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLS_IF
Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.
Note: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
2
1
read-only
RLS_INT
Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN and RLS_IF are both set to 1.\n
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
THRE_IF
Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty).
1
1
read-only
THRE_INT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.\n
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TOUT_IF
Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.
4
1
read-only
TOUT_INT
Time-out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and TOUT_IF are both set to 1.\n
12
1
read-only
0
No Tout interrupt is generated
#0
1
Tout interrupt is generated
#1
UA_LCR
UA_LCR
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.
6
1
read-write
EPE
Even Parity Enable\nThis bit has effect only when PBE (UA_LCR[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of STOP Bit
2
1
read-write
0
One STOP bit is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 STOP bit is generated in the transmitted data. When select 6-,7- and 8-bti word length, 2 STOP bit is generated in the transmitted data
#1
PBE
Parity Bit Enable\n
3
1
read-write
0
No parity bit
#0
1
Parity bit is generated on each outgoing character and is checked on each incoming data
#1
SPE
Stick Parity Enable\n
5
1
read-write
0
Stick parity Disabled
#0
1
If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UA_LCR[3]) is 1 and EBE (UA_LCR[4]) is 0 then the parity bit is transmitted and checked as 1
#1
WLS
Word Length Selection\n
0
2
read-write
UA_LIN_CTL
UA_LIN_CTL
UART LIN Control Register
0x34
-1
read-write
n
0x0
0x0
BIT_ERR_EN
Bit Error Detect Enable\n
12
1
read-write
0
Bit error detection function Disabled
#0
1
Bit error detection Enabled
#1
LINS_ARS_EN
LIN Slave Automatic Resynchronization Mode Enable\nNote2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (UA_BAUD [DIV_X_EN] and UA_BAUD [DIV_X_ONE] must be 1).\nNote3: The control and interactions of this field are explained in character 6.12.5.4 (Slave mode with automatic resynchronization).
2
1
read-write
0
LIN automatic resynchronization Disabled
#0
1
LIN automatic resynchronization Enabled
#1
LINS_DUM_EN
LIN Slave Divider Update Method Enable\nNote2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) \nNote3: The control and interactions of this field are explained in character 6.12.5.4 (Slave mode with automatic resynchronization).
3
1
read-write
0
UA_BAUD is updated as soon as UA_BAUD is writing by software (if no automatic resynchronization update occurs at the same time)
#0
1
UA_BAUD is updated at the next received character. User must set the bit before checksum reception
#1
LINS_EN
LIN Slave Mode Enable\n
0
1
read-write
0
LIN slave mode Disabled
#0
1
LIN slave mode Enabled
#1
LINS_HDET_EN
LIN Slave Header Detection Enable\n
1
1
read-write
0
LIN slave header detection Disabled
#0
1
LIN slave header detection Enabled
#1
LIN_BKDET_EN
LIN Break Detection Enable\n
10
1
read-write
0
Disable LIN break detection
#0
1
Enable LIN break detection
#1
LIN_BKFL
LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of UA_ALT_CSR [LIN_BKFL], User can read/write it by setting UA_ALT_CSR [LIN_BKFL] or UA_LIN_CTL [LIN_BKFL].\nNote2: This break field length is LIN_BKFL + 1.\n
16
4
read-write
LIN_BS_LEN
LIN Break/Sync Delimiter Length\n\nNote: This bit used for LIN master to sending header field.
20
2
read-write
0
The LIN break/sync delimiter length is 1 bit time
#00
2
The LIN break/sync delimiter length is 2 bit time.\nThe LIN break/sync delimiter length is 3 bit time
#10
3
The LIN break/sync delimiter length is 4 bit time
#11
LIN_HEAD_SEL
LIN Header Select\n
22
2
read-write
0
The LIN header includes break field
#00
1
The LIN header includes break field and sync field
#01
2
The LIN header includes break field , sync field and frame ID field
#10
3
Reserved
#11
LIN_IDPEN
LIN ID Parity Enable\n
9
1
read-write
0
LIN frame ID parity Disabled
#0
1
LIN frame ID parity Enabled
#1
LIN_MUTE_EN
LIN Mute Mode Enable\nNote: The exit from mute mode condition and each control and interactions of this field are explained in character 6.12.5.4 (LIN slave mode).
4
1
read-write
0
LIN mute mode Disabled
#0
1
LIN mute mode Enabled
#1
LIN_PID
LIN PID Register\nThis field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on UA_LIN_CTL [LIN_IDPEN]. \n\nNote1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first)\nNote2: This field can be used for LIN master mode or slave mode.
24
8
read-write
LIN_RX_DIS
None
11
1
read-write
0
Error detection function Disabled
#0
1
Bit error detection Enabled
#1
LIN_SHD
LIN TX Send Header Enable
The LIN TX header can be break field or break and sync field or break, sync and frame ID field , it is depend on setting LIN_HEAD_SEL register.
Note1: These registers are shadow registers of UA_ALT_CSR [LIN_SHD] user can read/write it by setting UA_ALT_CSR [LIN_SHD] or UA_LIN_CTL [LIN_SHD].
Note2: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by LIN_HEAD_SEL field) transfer operation finished, this bit will be cleared automatically.
8
1
read-write
0
Send LIN TX header Disabled
#0
1
Send LIN TX header Enabled
#1
UA_LIN_SR
UA_LIN_SR
UART LIN Status Register
0x38
read-write
n
0x0
0x0
BIT_ERR_F
Bit Error Detect Status Flag (Read Only)\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BIT_ERR_F will be set.\n
9
1
read-only
LINS_HDET_F
LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\n
0
1
read-only
0
LIN header not detected
#0
1
LIN header detected (break + sync + frame ID)
#1
LINS_HERR_F
LIN Slave Header Error Flag (Read Only)
This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include break delimiter is too short , frame error in sync field or Identifier field , sync field data is not 0x55 in Non-Automatic Resynchronization mode , sync field deviation error with Automatic Resynchronization mode , sync field measure time-out with Automatic Resynchronization mode and LIN header reception time-out .
1
1
read-only
0
LIN header error not detected
#0
1
LIN header error detected
#1
LINS_IDPERR_F
LIN Slave ID Parity Error Flag (Read Only)\nThis bit is set by hardware when receipted frame ID parity is not correct.\n
2
1
read-only
0
No active
#0
1
Receipted frame ID parity is not correct
#1
LINS_SYNC_F
LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit is read only, but it can be cleared by writing 1 to it.\nNote3: When writing 1 to it, hardware will reload the initial baud-rate and re-search a new frame header.
3
1
read-write
0
The current character is not at LIN sync state
#0
1
The current character is at LIN sync state
#1
LIN_BKDET_F
LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: This bit is only valid when enable LIN break detection function (UA_ALT_CSR [LIN_BKDET_EN])
8
1
read-only
0
LIN break not detected
#0
1
LIN break detected
#1
UA_MCR
UA_MCR
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
LEV_RTS
NRTS Trigger Level (Not Available in UART2 Channel)\nThis bit can change the nRTS trigger level.\n
9
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
RTS
NRTS (Request-to-send) Signal (Not Available in UART2 Channel)\n
1
1
read-write
0
Drive nRTS pin to logic 1 (If the LEV_RTS set to low level triggered).\nDrive nRTS pin to logic 0 (If the LEV_RTS set to high level triggered)
#0
1
Drive nRTS pin to logic 0 (If the LEV_RTS set to low level triggered).\nDrive nRTS pin to logic 1 (If the LEV_RTS set to high level triggered)
#1
RTS_ST
NRTS Pin State (Read Only) (Not Available in UART2 Channel)\nThis bit is the output pin status of nRTS.
13
1
read-only
UA_MSR
UA_MSR
UART Modem Status Register
0x14
-1
read-write
n
0x0
0x0
CTS_ST
NCTS Pin Status (Read Only) (Not Available in UART2 Channel)\nThis bit is the pin status of nCTS.
4
1
read-only
DCTSF
Detect NCTS State Change Flag (Read Only) (Not Available in UART2 Channel)\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1.\nWrite 1 to clear this bit to 0
0
1
read-only
LEV_CTS
NCTS Trigger Level (Not Available in UART2 Channel)\nThis bit can change the nCTS trigger level.\n
8
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
UA_RBR
UA_RBR
UART Receive Buffer Register
0x0
read-only
n
0x0
0x0
RBR
Receive Buffer Register (Read Only)\nBy reading this register, the UART will return an 8-bit data received from UART_RXD pin (LSB first).
0
8
read-only
UA_THR
UA_THR
UART Transmit Holding Register
UA_RBR
0x0
write-only
n
0x0
0x0
THR
Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the UART_TXD pin (LSB first).
0
8
write-only
UA_TOR
UA_TOR
UART Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit.
8
8
read-write
TOIC
Time-out Interrupt Comparator\n
0
8
read-write
UART2
UART Register Map
UART
0x0
0x0
0x10
registers
n
0x18
0x24
registers
n
UA_ALT_CSR
UA_ALT_CSR
UART Alternate Control/Status Register
0x2C
read-write
n
0x0
0x0
ADDR_MATCH
Address Match Value Register \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
LIN_BKFL
UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is UA_LIN_BKFL + 1\n
0
4
read-write
LIN_RX_EN
LIN RX Enable\n
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LIN_TX_EN
LIN TX Break Mode Enable\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
LIN TX Break mode Disabled
#0
1
LIN TX Break mode Enabled
#1
RS485_AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485_ADD_EN
RS-485 Address Detection Enable \nThis bit is used to enable RS-485 Address Detection mode. \nNote: This field is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
RS485_AUD
RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation mode (AUO) Disabled
#0
1
RS-485 Auto Direction Operation mode (AUO) Enabled
#1
RS485_NMM
RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UA_BAUD
UA_BAUD
UART Baud Rate Divisor Register
0x24
-1
read-write
n
0x0
0x0
BRD
Baud Rate Divider\nThe field indicates the baud rate divider
0
16
read-write
DIVIDER_X
Divider X\n
24
4
read-write
DIV_X_EN
Divider X Enable\nRefer to Table 611 for more information.\nNote: In IrDA mode, this bit must disable.
29
1
read-write
0
Divider X Disabled (the equation of M = 16)
#0
1
Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8)
#1
DIV_X_ONE
Divider X Equal to 1\nRefer to Table 611 for more information.
28
1
read-write
0
Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8)
#0
1
Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 3)
#1
UA_FCR
UA_FCR
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt (INT_RDA) Trigger Level\n
4
4
read-write
RFR
RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
RTS_TRI_LEV
NRTS Trigger Level for Auto-flow Control Use (Not Available in UART2 Channel)
16
4
read-write
RX_DIS
Receiver Disable Register\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
TFR
TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UA_FSR
UA_FSR
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
BIF
Break Interrupt Flag (Read Only)
This bit is set to logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but can be cleared by writing '1' to it.
6
1
read-only
FEF
Framing Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0), and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but can be cleared by writing '1' to it.
5
1
read-only
PEF
Parity Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit.
Note: This bit is read only, but can be cleared by writing '1' to it.
4
1
read-only
RS485_ADD_DETF
RS-485 Address Byte Detection Flag (Read Only) \nNote: This field is used for RS-485 function mode.\nNote: This bit is read only, but can be cleared by writing '1' to it.
3
1
read-only
RX_EMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
RX_FULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO is full or not.\nThis bit is set when the number of usage in RX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2), otherwise is cleared by hardware.
15
1
read-only
RX_OVER_IF
RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 64/16/16 bytes of UART0/UART1/UART2, this bit will be set.\nNote: This bit is read only, but can be cleared by writing '1' to it.
0
1
read-only
RX_POINTER
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, then RX_POINTER increases one. When one byte of RX FIFO is read by CPU, then RX_POINTER decreases one.\nThe Maximum value shown in RX_POINTER is 63/15/15 (UART0/UART1/UART2). When the using level of RX FIFO Buffer equal to 64/16/16, the RX_FULL bit is set to 1 and RX_POINTER will show 0. As one byte of RX FIFO is read by CPU, the RX_FULL bit is cleared to 0 and RX_POINTER will show 63/15/15 (UART0/UART1/UART2).
8
6
read-only
TE_FLAG
Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
TX_EMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO is empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty).
22
1
read-only
TX_FULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO is full or not.\nThis bit is set when the number of usage in TX FIFO Buffer is equal to 64/16/16(UART0/UART1/UART2), otherwise is cleared by hardware.
23
1
read-only
TX_OVER_IF
TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1.\nNote: This bit is read only, but can be cleared by writing '1' to it.
24
1
read-only
TX_POINTER
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, then TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, then TX_POINTER decreases one.\nThe Maximum value shown in TX_POINTER is 63/15/15 (UART0/UART1/UART2). When the using level of TX FIFO Buffer equal to 64/16/16, the TX_FULL bit is set to 1 and TX_POINTER will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TX_FULL bit is cleared to 0 and TX_POINTER will show 63/15/15 (UART0/UART1/UART2).
16
6
read-only
UA_FUN_SEL
UA_FUN_SEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUN_SEL
Function Select Enable\n
0
2
read-write
0
UART function Enabled
#00
1
LIN function Enabled
#01
2
IrDA function Enabled
#10
3
RS-485 function Enabled
#11
UA_IER
UA_IER
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
AUTO_CTS_EN
NCTS Auto Flow Control Enable (Not Available in UART2 Channel)\nWhen nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto flow control Disabled
#0
1
nCTS auto flow control Enabled
#1
AUTO_RTS_EN
NRTS Auto Flow Control Enable (Not Available in UART2 Channel)\nWhen nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the UA_FCR [RTS_TRI_LEV], the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto flow control Disabled
#0
1
nRTS auto flow control Enabled
#1
BUF_ERR_IEN
Buffer Error Interrupt Enable\n
5
1
read-write
0
INT_BUF_ERR Masked off
#0
1
INT_BUF_ERR Enabled
#1
DMA_RX_EN
RX DMA Enable (Not Available in UART2 Channel)\nThis bit can enable or disable RX DMA service.\n
15
1
read-write
0
RX DMA Disabled
#0
1
RX DMA Enabled
#1
DMA_TX_EN
TX DMA Enable (Not Available in UART2 Channel)\nThis bit can enable or disable TX DMA service.\n
14
1
read-write
0
TX DMA Disabled
#0
1
TX DMA Enabled
#1
LIN_IEN
LIN Bus Interrupt Enable\nNote: This field is used for LIN function mode.
8
1
read-write
0
Lin bus interrupt Disabled
#0
1
Lin bus interrupt Enabled
#1
MODEM_IEN
Modem Status Interrupt Enable (Not Available in UART2 Channel)\n
3
1
read-write
0
INT_MODEM Masked off
#0
1
INT_MODEM Enabled
#1
RDA_IEN
Receive Data Available Interrupt Enable\n
0
1
read-write
0
INT_RDA Masked off
#0
1
INT_RDA Enabled
#1
RLS_IEN
Receive Line Status Interrupt Enable \n
2
1
read-write
0
INT_RLS Masked off
#0
1
INT_RLS Enabled
#1
THRE_IEN
Transmit Holding Register Empty Interrupt Enable\n
1
1
read-write
0
INT_THRE Masked off
#0
1
INT_THRE Enabled
#1
TIME_OUT_EN
Time-out Counter Enable\n
11
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TOUT_IEN
RX Time-out Interrupt Enable\n
4
1
read-write
0
INT_TOUT Masked off
#0
1
INT_TOUT Enabled
#1
WAKE_EN
UART Wake-up Function Enable (Not Available in UART2 Channel)\n
6
1
read-write
0
UART wake-up function Disabled
#0
1
UART wake-up function Enabled, when the chip is in Power-down mode, an external nCTS change will wake-up chip from Power-down mode
#1
UA_IRCR
UA_IRCR
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
INV_RX
INV_RX\n
6
1
read-write
0
No inversion
#0
1
Inverse RX input signal
#1
INV_TX
INV_TX\n
5
1
read-write
0
No inversion
#0
1
Inverse TX output signal
#1
TX_SELECT
TX_SELECT\n
1
1
read-write
0
IrDA receiver Enabled
#0
1
IrDA transmitter Enabled
#1
UA_ISR
UA_ISR
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
BUF_ERR_IF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.
5
1
read-only
BUF_ERR_INT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.\n
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HW_BUF_ERR_IF
In DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared.
21
1
read-only
HW_BUF_ERR_INT
In DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and HW_BUF_ERR_IF are both set to 1.\n
29
1
read-only
0
No buffer error interrupt is generated in DMA mode
#0
1
Buffer error interrupt is generated in DMA mode
#1
HW_MODEM_IF
In DMA Mode, MODEM Interrupt Flag (Read Only) (Not Available in UART2 Channel)\nNote: This bit is read only and reset to 0 when the bit DCTSF is cleared by writing 1 on DCTSF.
19
1
read-only
HW_MODEM_INT
In DMA Mode, MODEM Status Interrupt Indicator (Read Only) (Not Available in UART2 Channel)\nThis bit is set if MODEM_IEN and HW_MODEM_IF are both set to 1.\n
27
1
read-only
0
No Modem interrupt is generated in DMA mode
#0
1
Modem interrupt is generated in DMA mode
#1
HW_RLS_IF
In DMA Mode, Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
18
1
read-only
HW_RLS_INT
In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLS_IEN and HW_RLS_IF are both set to 1.\n
26
1
read-only
0
No RLS interrupt is generated in DMA mode
#0
1
RLS interrupt is generated in DMA mode
#1
HW_TOUT_IF
In DMA Mode, Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.
20
1
read-only
HW_TOUT_INT
In DMA Mode, Time-out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and HW_TOUT_IF are both set to 1.\n
28
1
read-only
0
No Tout interrupt is generated in DMA mode
#0
1
Tout interrupt is generated in DMA mode
#1
LIN_IF
LIN Bus Flag (Read Only)\nNote: This bit is cleared when LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPENR_F and LINS_HERR_F all are cleared
7
1
read-only
LIN_INT
LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN and LIN _IF are both set to 1.\n
15
1
read-only
0
No LIN Bus interrupt is generated
#0
1
The LIN Bus interrupt is generated
#1
MODEM_IF
MODEM Interrupt Flag (Read Only) (Not Available in UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.
3
1
read-only
MODEM_INT
MODEM Status Interrupt Indicator (Read Only) (Not Available in UART2 Channel)\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.\n
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDA_IF
Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
0
1
read-only
RDA_INT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.\n
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLS_IF
Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.
Note: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
2
1
read-only
RLS_INT
Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN and RLS_IF are both set to 1.\n
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
THRE_IF
Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty).
1
1
read-only
THRE_INT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.\n
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TOUT_IF
Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.
4
1
read-only
TOUT_INT
Time-out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and TOUT_IF are both set to 1.\n
12
1
read-only
0
No Tout interrupt is generated
#0
1
Tout interrupt is generated
#1
UA_LCR
UA_LCR
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.
6
1
read-write
EPE
Even Parity Enable\nThis bit has effect only when PBE (UA_LCR[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of STOP Bit
2
1
read-write
0
One STOP bit is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 STOP bit is generated in the transmitted data. When select 6-,7- and 8-bti word length, 2 STOP bit is generated in the transmitted data
#1
PBE
Parity Bit Enable\n
3
1
read-write
0
No parity bit
#0
1
Parity bit is generated on each outgoing character and is checked on each incoming data
#1
SPE
Stick Parity Enable\n
5
1
read-write
0
Stick parity Disabled
#0
1
If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UA_LCR[3]) is 1 and EBE (UA_LCR[4]) is 0 then the parity bit is transmitted and checked as 1
#1
WLS
Word Length Selection\n
0
2
read-write
UA_LIN_CTL
UA_LIN_CTL
UART LIN Control Register
0x34
-1
read-write
n
0x0
0x0
BIT_ERR_EN
Bit Error Detect Enable\n
12
1
read-write
0
Bit error detection function Disabled
#0
1
Bit error detection Enabled
#1
LINS_ARS_EN
LIN Slave Automatic Resynchronization Mode Enable\nNote2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (UA_BAUD [DIV_X_EN] and UA_BAUD [DIV_X_ONE] must be 1).\nNote3: The control and interactions of this field are explained in character 6.12.5.4 (Slave mode with automatic resynchronization).
2
1
read-write
0
LIN automatic resynchronization Disabled
#0
1
LIN automatic resynchronization Enabled
#1
LINS_DUM_EN
LIN Slave Divider Update Method Enable\nNote2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) \nNote3: The control and interactions of this field are explained in character 6.12.5.4 (Slave mode with automatic resynchronization).
3
1
read-write
0
UA_BAUD is updated as soon as UA_BAUD is writing by software (if no automatic resynchronization update occurs at the same time)
#0
1
UA_BAUD is updated at the next received character. User must set the bit before checksum reception
#1
LINS_EN
LIN Slave Mode Enable\n
0
1
read-write
0
LIN slave mode Disabled
#0
1
LIN slave mode Enabled
#1
LINS_HDET_EN
LIN Slave Header Detection Enable\n
1
1
read-write
0
LIN slave header detection Disabled
#0
1
LIN slave header detection Enabled
#1
LIN_BKDET_EN
LIN Break Detection Enable\n
10
1
read-write
0
Disable LIN break detection
#0
1
Enable LIN break detection
#1
LIN_BKFL
LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of UA_ALT_CSR [LIN_BKFL], User can read/write it by setting UA_ALT_CSR [LIN_BKFL] or UA_LIN_CTL [LIN_BKFL].\nNote2: This break field length is LIN_BKFL + 1.\n
16
4
read-write
LIN_BS_LEN
LIN Break/Sync Delimiter Length\n\nNote: This bit used for LIN master to sending header field.
20
2
read-write
0
The LIN break/sync delimiter length is 1 bit time
#00
2
The LIN break/sync delimiter length is 2 bit time.\nThe LIN break/sync delimiter length is 3 bit time
#10
3
The LIN break/sync delimiter length is 4 bit time
#11
LIN_HEAD_SEL
LIN Header Select\n
22
2
read-write
0
The LIN header includes break field
#00
1
The LIN header includes break field and sync field
#01
2
The LIN header includes break field , sync field and frame ID field
#10
3
Reserved
#11
LIN_IDPEN
LIN ID Parity Enable\n
9
1
read-write
0
LIN frame ID parity Disabled
#0
1
LIN frame ID parity Enabled
#1
LIN_MUTE_EN
LIN Mute Mode Enable\nNote: The exit from mute mode condition and each control and interactions of this field are explained in character 6.12.5.4 (LIN slave mode).
4
1
read-write
0
LIN mute mode Disabled
#0
1
LIN mute mode Enabled
#1
LIN_PID
LIN PID Register\nThis field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on UA_LIN_CTL [LIN_IDPEN]. \n\nNote1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first)\nNote2: This field can be used for LIN master mode or slave mode.
24
8
read-write
LIN_RX_DIS
None
11
1
read-write
0
Error detection function Disabled
#0
1
Bit error detection Enabled
#1
LIN_SHD
LIN TX Send Header Enable
The LIN TX header can be break field or break and sync field or break, sync and frame ID field , it is depend on setting LIN_HEAD_SEL register.
Note1: These registers are shadow registers of UA_ALT_CSR [LIN_SHD] user can read/write it by setting UA_ALT_CSR [LIN_SHD] or UA_LIN_CTL [LIN_SHD].
Note2: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by LIN_HEAD_SEL field) transfer operation finished, this bit will be cleared automatically.
8
1
read-write
0
Send LIN TX header Disabled
#0
1
Send LIN TX header Enabled
#1
UA_LIN_SR
UA_LIN_SR
UART LIN Status Register
0x38
read-write
n
0x0
0x0
BIT_ERR_F
Bit Error Detect Status Flag (Read Only)\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BIT_ERR_F will be set.\n
9
1
read-only
LINS_HDET_F
LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\n
0
1
read-only
0
LIN header not detected
#0
1
LIN header detected (break + sync + frame ID)
#1
LINS_HERR_F
LIN Slave Header Error Flag (Read Only)
This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include break delimiter is too short , frame error in sync field or Identifier field , sync field data is not 0x55 in Non-Automatic Resynchronization mode , sync field deviation error with Automatic Resynchronization mode , sync field measure time-out with Automatic Resynchronization mode and LIN header reception time-out .
1
1
read-only
0
LIN header error not detected
#0
1
LIN header error detected
#1
LINS_IDPERR_F
LIN Slave ID Parity Error Flag (Read Only)\nThis bit is set by hardware when receipted frame ID parity is not correct.\n
2
1
read-only
0
No active
#0
1
Receipted frame ID parity is not correct
#1
LINS_SYNC_F
LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit is read only, but it can be cleared by writing 1 to it.\nNote3: When writing 1 to it, hardware will reload the initial baud-rate and re-search a new frame header.
3
1
read-write
0
The current character is not at LIN sync state
#0
1
The current character is at LIN sync state
#1
LIN_BKDET_F
LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: This bit is only valid when enable LIN break detection function (UA_ALT_CSR [LIN_BKDET_EN])
8
1
read-only
0
LIN break not detected
#0
1
LIN break detected
#1
UA_RBR
UA_RBR
UART Receive Buffer Register
0x0
read-only
n
0x0
0x0
RBR
Receive Buffer Register (Read Only)\nBy reading this register, the UART will return an 8-bit data received from UART_RXD pin (LSB first).
0
8
read-only
UA_THR
UA_THR
UART Transmit Holding Register
UA_RBR
0x0
write-only
n
0x0
0x0
THR
Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the UART_TXD pin (LSB first).
0
8
write-only
UA_TOR
UA_TOR
UART Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit.
8
8
read-write
TOIC
Time-out Interrupt Comparator\n
0
8
read-write
USB
USB Register Map
USB
0x0
0x0
0x1C
registers
n
0x20
0x60
registers
n
0x90
0x4
registers
n
ATTR
USB_ATTR
USB Bus Status and Attribution Register
0x10
-1
read-write
n
0x0
0x0
BYTEM
CPU Access USB SRAM Size Mode Selection\n
10
1
read-write
0
Word mode: The size of the transfer from CPU to USB SRAM can be Word only
#0
1
Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only
#1
DPPU_EN
Pull-up Resistor on USB_DP Enable\n
8
1
read-write
0
Pull-up resistor in USB_DP bus Disabled
#0
1
Pull-up resistor in USB_DP bus Active
#1
PHY_EN
PHY Transceiver Function Enable\n
4
1
read-write
0
PHY transceiver function Disabled
#0
1
PHY transceiver function Enabled
#1
PWRDN
Power-down PHY Transceiver, Low Active\n
9
1
read-write
0
Power-down related circuit of PHY transceiver
#0
1
Turn-on related circuit of PHY transceiver
#1
RESUME
Resume Status\nThis bit is read only.
2
1
read-write
0
No bus resume
#0
1
Resume from suspend
#1
RWAKEUP
Remote Wake-up\n
5
1
read-write
0
Release the USB bus from K state
#0
1
Force USB bus to K (USB_DP low, USB_DM: high) state, used for remote wake-up
#1
SUSPEND
Suspend Status\nThis bit is read only.
1
1
read-write
0
Bus no suspend
#0
1
Bus idle more than 3ms, either cable is plugged off or host is sleeping
#1
TIMEOUT
Time-out Status\nThis bit is read only.
3
1
read-write
0
No time-out
#0
1
No Bus response more than 18 bits time
#1
USBRST
USB Reset Status\nThis bit is read only.
0
1
read-write
0
Bus no reset
#0
1
Bus reset when SE0 (single-ended 0) more than 2.5us
#1
USB_EN
USB Controller Enable\n
7
1
read-write
0
USB Controller Disabled
#0
1
USB Controller Enabled
#1
BUFSEG0
USB_BUFSEG0
Endpoint 0 Buffer Segmentation Register
0x20
read-write
n
0x0
0x0
BUFSEG
It Is Used to Indicate the Offset Address for Each Endpoint with the USB SRAM Starting Address The Effective Starting Address of the Endpoint Is\nUSB_SRAM address + { BUFSEG[8:3], 3'b000}\nRefer to the section 5.4.4.7 for the endpoint SRAM structure and its description.
3
6
read-write
BUFSEG1
USB_BUFSEG1
Endpoint 1 Buffer Segmentation Register
0x30
read-write
n
0x0
0x0
BUFSEG2
USB_BUFSEG2
Endpoint 2 Buffer Segmentation Register
0x40
read-write
n
0x0
0x0
BUFSEG3
USB_BUFSEG3
Endpoint 3 Buffer Segmentation Register
0x50
read-write
n
0x0
0x0
BUFSEG4
USB_BUFSEG4
Endpoint 4 Buffer Segmentation Register
0x60
read-write
n
0x0
0x0
BUFSEG5
USB_BUFSEG5
Endpoint 5 Buffer Segmentation Register
0x70
read-write
n
0x0
0x0
CFG0
USB_CFG0
Endpoint 0 Configuration Register
0x28
read-write
n
0x0
0x0
CSTALL
Clear STALL Response\n
9
1
read-write
0
Disable the device to clear the STALL handshake in setup stage
#0
1
Clear the device to response STALL -handshake in setup stage
#1
DSQ_SYNC
Data Sequence Synchronization\nIt is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token based on the bit.
7
1
read-write
0
DATA0 PID
#0
1
DATA1 PID
#1
EP_NUM
Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint
0
4
read-write
ISOCH
Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint, no handshake.\n
4
1
read-write
0
No Isochronous endpoint
#0
1
Isochronous endpoint
#1
STATE
Endpoint STATE\n
5
2
read-write
0
Endpoint is Disabled
#00
1
Out endpoint
#01
2
IN endpoint
#10
3
Undefined
#11
CFG1
USB_CFG1
Endpoint 1 Configuration Register
0x38
read-write
n
0x0
0x0
CFG2
USB_CFG2
Endpoint 2 Configuration Register
0x48
read-write
n
0x0
0x0
CFG3
USB_CFG3
Endpoint 3 Configuration Register
0x58
read-write
n
0x0
0x0
CFG4
USB_CFG4
Endpoint 4 Configuration Register
0x68
read-write
n
0x0
0x0
CFG5
USB_CFG5
Endpoint 5 Configuration Register
0x78
read-write
n
0x0
0x0
CFGP0
USB_CFGP0
Endpoint 0 Set Stall and Clear In/Out Ready Control Register
0x2C
read-write
n
0x0
0x0
CLRRDY
Clear Ready\nWhen the MXPLD register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to turn off this transaction before the transaction start, users can set this bit to 1 to turn it off and it is auto clear to 0.\nFor IN token, write '1' to clear the IN token had ready to transmit the data to USB.\nFor OUT token, write '1' to clear the OUT token had ready to receive the data from USB.\nThis bit is written 1 only and is always 0 when it is read back.
0
1
read-write
SSTALL
Set STALL\n
1
1
read-write
0
Disable the device to response STALL
#0
1
Set the device to respond STALL automatically
#1
CFGP1
USB_CFGP1
Endpoint 1 Set Stall and Clear In/Out Ready Control Register
0x3C
read-write
n
0x0
0x0
CFGP2
USB_CFGP2
Endpoint 2 Set Stall and Clear In/Out Ready Control Register
0x4C
read-write
n
0x0
0x0
CFGP3
USB_CFGP3
Endpoint 3 Set Stall and Clear In/Out Ready Control Register
0x5C
read-write
n
0x0
0x0
CFGP4
USB_CFGP4
Endpoint 4 Set Stall and Clear In/Out Ready Control Register
0x6C
read-write
n
0x0
0x0
CFGP5
USB_CFGP5
Endpoint 5 Set Stall and Clear In/Out Ready Control Register
0x7C
read-write
n
0x0
0x0
DRVSE0
USB_DRVSE0
USB Drive SE0 Control Register
0x90
-1
read-write
n
0x0
0x0
DRVSE0
Drive Single Ended Zero in USB Bus\nThe Single Ended Zero (SE0) is when both lines (USB_DP and USB_DM) are being pulled low.\n
0
1
read-write
0
None
#0
1
Force USB PHY transceiver to drive SE0
#1
EPSTS
USB_EPSTS
USB Endpoint Status Register
0xC
read-only
n
0x0
0x0
EPSTS0
Endpoint 0 Bus Status\nThese bits are used to indicate the current status of this endpoint\n
8
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS1
Endpoint 1 Bus Status\nThese bits are used to indicate the current status of this endpoint\n
11
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS2
Endpoint 2 Bus Status\nThese bits are used to indicate the current status of this endpoint\n
14
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS3
Endpoint 3 Bus Status\nThese bits are used to indicate the current status of this endpoint\n
17
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS4
Endpoint 4 Bus Status\nThese bits are used to indicate the current status of this endpoint\n
20
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
EPSTS5
Endpoint 5 Bus Status\nThese bits are used to indicate the current status of this endpoint\n
23
3
read-only
0
In ACK
#000
1
In NAK
#001
2
Out Packet Data0 ACK
#010
3
Setup ACK
#011
6
Out Packet Data1 ACK
#110
7
Isochronous transfer end
#111
OVERRUN
Overrun\nIt indicates that the received data is over the maximum payload number or not.\n
7
1
read-only
0
No overrun
#0
1
Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes
#1
FADDR
USB_FADDR
USB Device Function Address Register
0x8
read-write
n
0x0
0x0
FADDR
USB Device Function Address
0
7
read-write
FLDET
USB_FLDET
USB Floating Detected Register
0x14
read-only
n
0x0
0x0
FLDET
Device Floating Detected\n
0
1
read-only
0
Controller is not attached into the USB host
#0
1
Controller is attached into the BUS
#1
INTEN
USB_INTEN
USB Interrupt Enable Register
0x0
read-write
n
0x0
0x0
BUS_IE
Bus Event Interrupt Enable\n
0
1
read-write
0
BUS event interrupt Disabled
#0
1
BUS event interrupt Enabled
#1
FLDET_IE
Floating Detected Interrupt Enable\n
2
1
read-write
0
Floating detect Interrupt Disabled
#0
1
Floating detect Interrupt Enabled
#1
INNAK_EN
Active NAK Function and Its Status in IN Token\n
15
1
read-write
0
NAK status is not updated into the endpoint status register when it was set to 0. It also disables the interrupt event when device responds to NAK after receiving IN token
#0
1
NAK status is updated into the endpoint status register, USB_EPSTS, when it is set to 1 and there is NAK response in IN token. It also enables the interrupt event when the device responds NAK after receiving IN token
#1
USB_IE
USB Event Interrupt Enable\n
1
1
read-write
0
USB event interrupt Disabled
#0
1
USB event interrupt Enabled
#1
WAKEUP_EN
Wake-up Function Enable\n
8
1
read-write
0
USB wake-up function Disabled
#0
1
USB wake-up function Enabled
#1
WAKEUP_IE
USB Wake-up Interrupt Enable\n
3
1
read-write
0
Wake-up Interrupt Disabled
#0
1
Wake-up Interrupt Enabled
#1
INTSTS
USB_INTSTS
USB Interrupt Event Status Register
0x4
read-write
n
0x0
0x0
BUS_STS
BUS Interrupt Status\nThe BUS event means that there is one of the suspense or the resume function in the bus.\n
0
1
read-write
0
No BUS event occurred
#0
1
Bus event occurred check USB_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USB_INTSTS[0]
#1
EPEVT0
Endpoint 0's USB Event Status\n
16
1
read-write
0
No event occurred in endpoint 0
#0
1
USB event occurred on Endpoint 0, check USB_EPSTS[10:8] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[16] or USB_INTSTS[1]
#1
EPEVT1
Endpoint 1's USB Event Status\n
17
1
read-write
0
No event occurred in endpoint 1
#0
1
USB event occurred on Endpoint 1, check USB_EPSTS[13:11] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[17] or USB_INTSTS[1]
#1
EPEVT2
Endpoint 2's USB Event Status\n
18
1
read-write
0
No event occurred in endpoint 2
#0
1
USB event occurred on Endpoint 2, check USB_EPSTS[16:14] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[18] or USB_INTSTS[1]
#1
EPEVT3
Endpoint 3's USB Event Status\n
19
1
read-write
0
No event occurred in endpoint 3
#0
1
USB event occurred on Endpoint 3, check USB_EPSTS[19:17] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[19] or USB_INTSTS[1]
#1
EPEVT4
Endpoint 4's USB Event Status\n
20
1
read-write
0
No event occurred in endpoint 4
#0
1
USB event occurred on Endpoint 4, check USB_EPSTS[22:20] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[20] or USB_INTSTS[1]
#1
EPEVT5
Endpoint 5's USB Event Status\n
21
1
read-write
0
No event occurred in endpoint 5
#0
1
USB event occurred on Endpoint 5, check USB_EPSTS[25:23] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[21] or USB_INTSTS[1]
#1
FLDET_STS
Floating Detected Interrupt Status\n
2
1
read-write
0
There is not attached/detached event in the USB
#0
1
There is attached/detached event in the USB bus and it is cleared by write 1 to USB_INTSTS[2]
#1
SETUP
Setup Event Status\n
31
1
read-write
0
No Setup event
#0
1
Setup event occurred, cleared by write 1 to USB_INTSTS[31]
#1
USB_STS
USB Event Interrupt Status\nThe USB event includes the Setup Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.\n
1
1
read-write
0
No USB event occurred
#0
1
USB event occurred, check EPSTS0~5[2:0] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[1] or EPSTS0~5 and SETUP (USB_INTSTS[31])
#1
WAKEUP_STS
Wake-up Interrupt Status\n
3
1
read-write
0
No Wake-up event occurred
#0
1
Wake-up event occurred, cleared by write 1 to USB_INTSTS[3]
#1
MXPLD0
USB_MXPLD0
Endpoint 0 Maximal Payload Register
0x24
read-write
n
0x0
0x0
MXPLD
Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.\n(1) When the register is written by CPU, \nFor IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.\nFor OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.\n(2) When the register is read by CPU,\nFor IN token, the value of MXPLD is indicated by the data length be transmitted to host\nFor OUT token, the value of MXPLD is indicated the actual data length receiving from host.\nNote: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
0
9
read-write
MXPLD1
USB_MXPLD1
Endpoint 1 Maximal Payload Register
0x34
read-write
n
0x0
0x0
MXPLD2
USB_MXPLD2
Endpoint 2 Maximal Payload Register
0x44
read-write
n
0x0
0x0
MXPLD3
USB_MXPLD3
Endpoint 3 Maximal Payload Register
0x54
read-write
n
0x0
0x0
MXPLD4
USB_MXPLD4
Endpoint 4 Maximal Payload Register
0x64
read-write
n
0x0
0x0
MXPLD5
USB_MXPLD5
Endpoint 5 Maximal Payload Register
0x74
read-write
n
0x0
0x0
STBUFSEG
USB_STBUFSEG
Setup Token Buffer Segmentation Register
0x18
read-write
n
0x0
0x0
STBUFSEG
It Is Used to Indicate the Offset Address for the Setup Token with the USB SRAM Starting Address The Effective Starting Address Is\nUSB_SRAM address + {STBUFSEG[8:3], 3'b000} \nNote: It is used for Setup token only.
3
6
read-write
WDT
WDT Register Map
WDT
0x0
0x0
0x8
registers
n
WTCR
WTCR
Watchdog Timer Control Register
0x0
-1
read-write
n
0x0
0x0
DBGACK_WDT
ICE Debug Mode Acknowledge Disable (Write Protected)\nWatchdog Timer counter will keep going no matter CPU is held by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement affects Watchdog Timer counting
#0
1
ICE debug mode acknowledgement Disabled
#1
WTE
Watchdog Timer Enable (Write Protected)\nNote: If CWDTEN (Config0[31] watchdog enable) bit is set to 0, this bit is forced as 1 and software cannot change this bit to 0.
7
1
read-write
0
Watchdog Timer Disabled (This action will reset the internal counter)
#0
1
Watchdog Timer Enabled
#1
WTIE
Watchdog Timer Interrupt Enable (Write Protected)\nIf this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. \n
6
1
read-write
0
Watchdog Timer interrupt Disabled
#0
1
Watchdog Timer interrupt Enabled
#1
WTIF
Watchdog Timer Interrupt Flag\nThis bit will set to 1 while WDT counter value reaches the selected WDT time-out interval\nNote: This bit is cleared by writing 1 to this bit.
3
1
read-write
0
Watchdog Timer time-out interrupt did not occur
#0
1
Watchdog Timer time-out interrupt occurred
#1
WTIS
Watchdog Timer Interval Selection (Write-protection Bits)\n
8
3
read-write
WTR
Reset Watchdog Timer Counter (Write Protected)\nNote: This bit will be automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Reset the internal 18-bit WDT counter
#1
WTRE
Watchdog Timer Reset Enable (Write Protected)\nSetting this bit will enable the Watchdog Timer time-out reset function If the WDT counter value has not been cleared after the specific WDT reset delay period expires..\n
1
1
read-write
0
Watchdog Timer time-out reset function Disabled
#0
1
Watchdog Timer time-out reset function Enabled
#1
WTRF
Watchdog Timer Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to this bit.
2
1
read-write
0
Watchdog Timer time-out reset did not occur
#0
1
Watchdog Timer time-out reset occurred
#1
WTWKE
Watchdog Timer Wake-up Function Enable Bit (Write Protected)\nIf this bit is set to 1, while WDT interrupt flag (WTCR[3] WTIF) is generated to 1 and WTIE (WTCR[6] WDT interrupt enable) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.\nNote: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillator.
4
1
read-write
0
Wake-up trigger event Disabled if WDT time-out interrupt signal generated
#0
1
Wake-up trigger event Enabled if WDT time-out interrupt signal generated
#1
WTWKF
Watchdog Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of WDT\nThis bit is cleared by writing 1 to this bit..
5
1
read-write
0
Watchdog Timer does not cause chip wake-up
#0
1
Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated
#1
WTCRALT
WTCRALT
Watchdog Timer Alternative Control Register
0x4
read-write
n
0x0
0x0
WTRDSEL
Watchdog Timer Reset Delay Select (Write-protection Bits)
When WDT time-out happened, software has a time named WDT reset delay period to clear WDT counter to prevent WDT time-out reset happened. Software can select a suitable value of WDT reset delay period for different WDT time-out period.
These bits are protected bit. It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.
This register will be reset to 0 if WDT time-out reset happened
0
2
read-write
0
Watchdog Timer reset delay period is (1024+2) * WDT_CLK
#00
1
Watchdog Timer reset delay period is (128+2) * WDT_CLK
#01
2
Watchdog Timer reset delay period is (16+2) * WDT_CLK
#10
3
Watchdog Timer reset delay period is (1+2) * WDT_CLK
#11
WWDT
WWDT Register Map
WWDT
0x0
0x0
0x10
registers
n
WWDTCR
WWDTCR
Window Watchdog Timer Control Register
0x4
-1
read-write
n
0x0
0x0
DBGACK_WWDT
ICE Debug Mode Acknowledge Disable\n
31
1
read-write
0
WWDT counter stopped if system is in Debug mode
#0
1
WWDT still counted even system is in Debug mode
#1
PERIODSEL
WWDT Prescale Period Select\n
8
4
read-write
WINCMP
WWDT Window Compare Register\nSet this register to adjust the valid reload window. \nNote: Software can only write WWDTRLD to reload WWDT counter value when current WWDT counter value between 0 and WINCMP. If Software writes WWDTRLD when current WWDT counter value larger than WINCMP, WWDT reset signal will generate immediately.
16
6
read-write
WWDTEN
WWDT Enable\nSet this bit to enable Window Watchdog Timer counter counting.\n
0
1
read-write
0
Window Watchdog Timer counter is stopped
#0
1
Window Watchdog Timer counter is starting counting
#1
WWDTIE
WWDT Interrupt Enable\nSet this bit to enable the Window Watchdog Timer time-out interrupt function.\n
1
1
read-write
0
WWDT time-out interrupt function Disabled if WWDTIF (WWDTSR[0] WWDT compare match interrupt flag) is 1
#0
1
WWDT time-out interrupt function Enabled if WWDTIF (WWDTSR[0] WWDT compare match interrupt flag) is 1
#1
WWDTCVR
WWDTCVR
Window Watchdog Timer Counter Value Register
0xC
-1
read-only
n
0x0
0x0
WWDTCVAL
WWDT Counter Value\nThis register reflects the current WWDT counter value and is read only.
0
6
read-only
WWDTRLD
WWDTRLD
Window Watchdog Timer Reload Counter Register
0x0
write-only
n
0x0
0x0
WWDTRLD
WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F. \nNote: Software can only write WWDTRLD to reload WWDT counter value when current WWDT counter value between 0 and WINCMP. If software writes WWDTRLD when current WWDT counter value is larger than WINCMP, WWDT reset signal will generate immediately.
0
32
write-only
WWDTSR
WWDTSR
Window Watchdog Timer Status Register
0x8
read-write
n
0x0
0x0
WWDTIF
WWDT Compare Match Interrupt Flag\nWhen current WWDT counter value matches WWCMP, this bit is set to 1. This bit will be cleared by writing 1 to itself.
0
1
read-write
WWDTRF
WWDT Reset Flag\nWhen WWDT counter counts down to 0 or writes WWDTRLD during current WWDT counter value being larger than WINCMP, chip will be reset and this bit is set to 1. This bit will be cleared to 0 by writing 1 to itself.
1
1
read-write