nuvoTon
NUC505_v1
2024.05.04
NUC505_v1 SVD file
8
32
ADC
ADC Register Map
ADC
0x0
0x0
0xC
registers
n
CTL
ADC_CTL
ADC Control Register
0x0
-1
read-write
n
0x0
0x0
CHSEL
Analog Input Selection Signals\nNote1: ADC_CH0 is used for battery voltage detection. It includes an inherent resistor divider and a switch.\nNote2: User needs to pay attention to electric leakage with ADC_CH0 because the default CHSEL is selected to ADC_CH0, and ADC_CH0 has an internal resistor divider. If ADC_CH0 is connected to battery, there is a leakage path. Therefore, user can change CHSEL to other channel to cut off this path, when finishing battery detection.
16
3
read-write
0
ADC_CH0
#000
1
ADC_CH1
#001
2
ADC_CH2
#010
3
ADC_CH3
#011
4
ADC_CH4
#100
5
ADC_CH5
#101
6
ADC_CH6
#110
7
ADC_CH7
#111
EXTSMPT
ADC Extend Sampling Time \nWhen A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if the input channel loading is heavy, software can extend A/D sampling time after trigger source is coming to get enough sampling time.\nNote: The unit is ADC clock.
24
8
read-write
PD
Power Down ADC \nNote1: ADC power must be enabled before a trigger to get the data.\nNote2: It needs 100ms to wait analog block stable when setting PD from 1 to 0.
13
1
read-write
0
ADC is in normal state
#0
1
ADC is in power down state
#1
PDKEY
Power Down Keypad Detection\n
15
1
read-write
0
Power down keypad detection Disabled
#0
1
Power down keypad detection Enabled
#1
SWTRG
A/D Conversion Start\nA trigger to start one A/D conversion process.\nNote: This bit will be cleared to '0' automatically.
0
1
read-write
0
A/D conversion enters idle state
#0
1
Start conversion
#1
DAT
ADC_DAT
ADC Data Register
0x8
read-only
n
0x0
0x0
RESULT
A/D Conversion Result\nThis field contains conversion result of ADC. When A/D conversion done, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0].
0
12
read-only
INTCTL
ADC_INTCTL
ADC Interrupt State
0x4
read-write
n
0x0
0x0
ADCIEN
ADC Interrupt Enable Control\n
8
1
read-write
0
ADC conversion done interrupt Disabled
#0
1
ADC conversion done interrupt Enabled
#1
ADCIF
ADC Conversion Done Interrupt Flag\nWhen finishing the sample process, the ADCIF bit will be set. If the ADCIEN is set, the interrupt will be transferred to NVIC.\n
0
1
read-write
0
ADC conversion done flag is not set
#0
1
ADC conversion done flag is set
#1
KEYIEN
Keypad Interrupt Enable Control\n
9
1
read-write
0
Keypad down interrupt Disabled
#0
1
Keypad down interrupt Enabled
#1
KEYIF
Keypad Interrupt Flag\nIn the process of checking keypad, the KEYIF shows the state. ADC_CH2 is used for keypad. When ADC_CH2 is not equal to AVDDADC, the interrupt flag will be raised.\n
1
1
read-write
0
Keypad is not pressing state
#0
1
keypad is pressing state
#1
CLK
CLKCTRL Register Map
CLKCTRL
0x0
0x0
0xC
registers
n
0x10
0x14
registers
n
0x28
0x4
registers
n
0x30
0x8
registers
n
AHBCLK
CLK_AHBCLK
AHB Devices Clock Enable Control Register
0x4
-1
read-write
n
0x0
0x0
ROMCKEN
ROM Clock Enable Control\n
2
1
read-write
0
ROM Clock Disabled
#0
1
ROM Clock Enabled
#1
SDHCKEN
SDH Clock Enable Control\n
5
1
read-write
0
SDH Clock Disabled
#0
1
SDH Clock Enabled
#1
SPIMCKEN
SPIM Clock Enable Control\n
3
1
read-write
0
SPIM Clock Disabled
#0
1
SPIM Clock Enabled
#1
SRAM01CKEN
SRAM#1 Clock Enable Control\n
0
1
read-write
0
SRAM#1 Clock Disabled
#0
1
SRAM#1 Clock Enabled
#1
SRAM23CKEN
SRAM#2 Clock Enable Control\n
1
1
read-write
0
SRAM#2 Clock Disabled
#0
1
SRAM#2 Clock Enabled
#1
USBDCKEN
USB Device Clock Enable Control\n
6
1
read-write
0
USB Device Clock Disabled
#0
1
USB Device Clock Enabled
#1
USBHCKEN
USB Host Clock Enable Control\n
9
1
read-write
0
USB Host Clock Disabled
#0
1
USB Host Clock Enabled
#1
APBCLK
CLK_APBCLK
APB Devices Clock Enable Control Register
0x8
read-write
n
0x0
0x0
ADCCKEN
ADC Clock Enable Control\n
15
1
read-write
0
ADC Clock Disabled
#0
1
ADC Clock Enabled
#1
I2C0CKEN
I2C0 Clock Enable Control\n
5
1
read-write
0
I2C0 Clock Disabled
#0
1
I2C0 Clock Enabled
#1
I2C1CKEN
I2C1 Clock Enable Control\n
6
1
read-write
0
I2C1 Clock Disabled
#0
1
I2C1 Clock Enabled
#1
I2SCKEN
I2S Clock Enable Control\n
14
1
read-write
0
I2S Clock Disabled
#0
1
I2S Clock Enabled
#1
PWMCKEN
PWM Clock Enable Control\n
8
1
read-write
0
PWM Clock Disabled
#0
1
PWM Clock Enabled
#1
RTCCKEN
RTC Clock Enable Control\n
7
1
read-write
0
RTC Clock Disabled
#0
1
RTC Clock Enabled
#1
SPI0CKEN
SPI0 Clock Enable Control\n
9
1
read-write
0
SPI0 Clock Disabled
#0
1
SPI0 Clock Enabled
#1
SPI1CKEN
SPI1 Clock Enable Control\n
10
1
read-write
0
SPI1 Clock Disabled
#0
1
SPI1 Clock Enabled
#1
TMR0CKEN
TIMER0 Clock Enable Control\n
0
1
read-write
0
TIMER0 Clock Disabled
#0
1
TIMER0 Clock Enabled
#1
TMR1CKEN
TIMER1 Clock Enable Control\n
1
1
read-write
0
TIMER1 Clock Disabled
#0
1
TIMER1 Clock Enabled
#1
TMR2CKEN
TIMER2 Clock Enable Control\n
2
1
read-write
0
TIMER2 Clock Disabled
#0
1
TIMER2 Clock Enabled
#1
TMR3CKEN
TIMER3 Clock Enable Control\n
3
1
read-write
0
TIMER3 Clock Disabled
#0
1
TIMER3 Clock Enabled
#1
UART0CKEN
UART0 Clock Enable Control\n
11
1
read-write
0
UART0 Clock Disabled
#0
1
UART0 Clock Enabled
#1
UART1CKEN
UART1 Clock Enable Control\n
12
1
read-write
0
UART1 Clock Disabled
#0
1
UART1 Clock Enabled
#1
UART2CKEN
UART2 Clock Enable Control\n
13
1
read-write
0
UART2 Clock Disabled
#0
1
UART2 Clock Enabled
#1
WDTCKEN
Watchdog Timer Clock Enable Control\n
4
1
read-write
0
Watchdog Timer Clock Disabled
#0
1
Watchdog Timer Clock Enabled
#1
APLLCTL
CLK_APLLCTL
APLL Control Register
0x28
-1
read-write
n
0x0
0x0
FBDIV
Feedback Divider Control \nSet the Feedback divider factor from 1 to 128. \n
6
7
read-write
FRAC
Sigma-delta Modulator Control Pins \nSet the fractional number of the Feedback divider.
20
12
read-write
INDIV
Reference Input Divider Control \nSet the reference divider factor from 1 to 64. \n
0
6
read-write
MODE
Mode Select \n
18
1
read-write
0
Integer mode
#0
1
Fraction mode
#1
OUTDIV
Output Divider Control \nSet the Output divider factor from 1 to 8. \n
13
3
read-write
PD
Power Down Enable Control\n
16
1
read-write
0
Power down Disabled
#0
1
Power down Enabled
#1
CLKDIV0
CLK_CLKDIV0
Clock Divider Number Control Register 0
0x10
-1
read-write
n
0x0
0x0
HCLKDIV
Defines the Clock Divider Number for SYS_CLK\nThe actual clock divider number is (HCLKDIV+1). So,\n
0
4
read-write
HCLKSEL
System Source Clock Select (SYS_SrcCLK)\n
7
1
read-write
0
System Clock source from HXT
#0
1
System Clock source from PLL_FOUT
#1
PCLKDIV
Defines the Clock Divider Number for APB_CLK\nThe actual clock divider number is (PCLKDIV+1). So,\n
8
4
read-write
USBDDIV
Defines the Clock Divider Number for USB Device\nThe actual clock divider number is (USBDDIV+1). So,\n
16
5
read-write
USBDSEL
USB Device Source Clock Select (USBD_SrcCLK)\n
23
1
read-write
0
USB Device Clock source from HXT
#0
1
USB Device Clock source from PLL_FOUT
#1
USBHDIV
Defines the Clock Divider Number for USB Host\nThe actual clock divider number is (USBHDIV+1). So,\n
24
4
read-write
CLKDIV1
CLK_CLKDIV1
Clock Divider Number Control Register 1
0x14
read-write
n
0x0
0x0
ADCDIV
Defines the Clock Divider Number for ADC\nThe actual clock divider number is (ADCDIV+1). So,\n
0
8
read-write
ADCSEL
ADC Clock Select (ADC_SrcCLK)\n
28
1
read-write
0
ADC Clock source from HXT
#0
1
ADC Clock source from PLL_FOUT
#1
SDHDIV
Defines the Clock Divider Number for SDH\nThe actual clock divider number is (SDHDIV+1). So,\n
16
11
read-write
SDHSEL
SDH Clock Select (SDH_SrcCLK)\n
30
1
read-write
0
SDH Clock source from HXT
#0
1
SDH Clock source from PLL_FOUT
#1
STICKDIV
Defines the Clock Divider Number for SYS_TICK\nThe actual clock divider number is (STICKDIV+1). So,\n
8
8
read-write
CLKDIV2
CLK_CLKDIV2
Clock Divider Number Control Register 2
0x18
read-write
n
0x0
0x0
I2SDIV
Defines the Clock Divider Number for I2S\nThe actual clock divider number is (I2SDIV+1). So,\n
0
8
read-write
I2SSEL
I2S Clock Select (I2S_SrcCLK)\n
24
2
read-write
0
I2S Clock source from HXT
#00
1
I2S Clock source from PLL_FOUT
#01
2
Reserved
#10
3
I2S Clock source from APLL_FOUT
#11
SPI0SEL
SPI0 Engine Clock Select (SPI0SEL)\n
28
1
read-write
0
SPI0 Engine Clock source from HXT
#0
1
SPI0 Engine Clock source from PLL_FOUT
#1
SPI1SEL
SPI1 Engine Clock Select (SPI1SEL)\n
29
1
read-write
0
SPI1 Engine Clock source from HXT
#0
1
SPI1 Engine Clock source from PLL_FOUT
#1
CLKDIV3
CLK_CLKDIV3
Clock Divider Number Control Register 3
0x1C
read-write
n
0x0
0x0
UART0DIV
Defines the Clock Divider Number for UART0\nThe actual clock divider number is (UART0DIV +1). So,\n
0
4
read-write
UART0SEL
UART0 Source Clock Select (UART0_SrcCLK)\n
4
1
read-write
0
UART0 Source Clock source from HXT
#0
1
UART0 Source Clock source from PLL_FOUT
#1
UART1DIV
Defines the Clock Divider Number for UART1\nThe actual clock divider number is (UART1DIV +1). So,\n
8
4
read-write
UART1SEL
UART1 Source Clock Select (UART1_SrcCLK)\n
12
1
read-write
0
UART1 Source Clock source from HXT
#0
1
UART1 Source Clock source from PLL_FOUT
#1
UART2DIV
Defines the Clock Divider Number for UART2\nThe actual clock divider number is (UART2DIV +1). So,\n
16
4
read-write
UART2SEL
UART2 Source Clock Select (UART2_SrcCLK)\n
20
1
read-write
0
UART2 Source Clock source from HXT
#0
1
UART2 Source Clock source from PLL_FOUT
#1
CLKDIV4
CLK_CLKDIV4
Clock Divider Number Control Register 4
0x30
read-write
n
0x0
0x0
TMR0DIV
Defines the Clock Divider Number for TMR0\nThe actual clock divider number is (TMR0DIV+1). So,\n
0
8
read-write
TMR0SEL
Timer0 Engine Clock Select (TMR0_SrcCLK)\n
24
1
read-write
0
Timer0 Engine Clock source from RTC_CLK
#0
1
Timer0 Engine Clock source from HXT
#1
TMR1DIV
Defines the Clock Divider Number for TMR1\nThe actual clock divider number is (TMR1DIV+1). So,\n
8
8
read-write
TMR1SEL
Timer1 Engine Clock Select (TMR1_SrcCLK)\n
25
1
read-write
0
Timer1 Engine Clock source from RTC_CLK
#0
1
Timer1 Engine Clock source from HXT
#1
TMR2DIV
Defines the Clock Divider Number for TMR2\nThe actual clock divider number is (TMR2DIV+1). So,\n
16
8
read-write
TMR2SEL
Timer2 Engine Clock Select (TMR2_SrcCLK)\n
26
1
read-write
0
Timer2 Engine Clock source from RTC_CLK
#0
1
Timer2 Engine Clock source from HXT
#1
CLKDIV5
CLK_CLKDIV5
Clock Divider Number Control Register 5
0x34
read-write
n
0x0
0x0
PWMDIV
Define the Clock Divider Number for PWM\nThe actual clock divider number is (PWMDIV+1). So,\n
16
8
read-write
PWMSEL
PWM Engine Clock Select (PWM_SrcCLK)\n
26
1
read-write
0
PWM Engine Clock source from HXT
#0
1
PWM Engine Clock source from PLL_FOUT
#1
TMR3DIV
Define the Clock Divider Number for TMR3\nThe actual clock divider number is (TM3DIV+1). So,\n
0
8
read-write
TMR3SEL
Timer3 Engine Clock Select (TMR3_SrcCLK)\n
24
1
read-write
0
Timer3 Engine Clock source from RTC_CLK
#0
1
Timer3 Engine Clock source from HXT
#1
WDTDIV
Define the Clock Divider Number for WDT\nThe actual clock divider number is (WDTDIV+1). So,\n
8
8
read-write
WDTSEL
WDT Engine Clock Select (WDT_SrcCLK)\n
25
1
read-write
0
WDT Engine Clock source from RTC_CLK
#0
1
WDT Engine Clock source from HXT
#1
PLLCTL
CLK_PLLCTL
PLL Control Register
0x20
-1
read-write
n
0x0
0x0
BP
PLL Bypass Control\n
16
1
read-write
0
PLL at Normal mode
#0
1
Bypass Fin (i.e. Fout = XIN)
#1
FBDIV
Feedback Divider Control (N)\nSet the feedback divider factor from 1 to 128
0
7
read-write
INDIV
Reference Input Divider (M)\nSet the input reference clock divider factor from 1 to 64.
7
6
read-write
OUTDIV
Output Divider Control (P) \nSet the output divider factor from 1 to 8.
13
3
read-write
PD
Power-down Mode\n
17
1
read-write
0
PLL in Normal mode
#0
1
PLL in Power-down mode (Default)
#1
PWRCTL
CLK_PWRCTL
System Power-down Control Register
0x0
-1
read-write
n
0x0
0x0
HXTCTL
Power-down Mode Wake-up Pre-divider Counter Enable Control
The HXT pre-divider controls wake-up time from Power-down mode. The chip will delay (PDWKPSC*256) cycles to wait until the HXT is stable after the reset signal.
1
1
read-write
0
PDWKPSC counter Disabled
#0
1
PDWKPSC counter Enabled
#1
HXTEN
Crystal (Power Down) Control\n
0
1
read-write
0
Crystal off (Power down)
#0
1
Crystal on (Normal operation)
#1
PDWKIEN
Power-down Mode Wake-up Interrupt Enable Control\nNote: The interrupt will occur when both PDWKIF and PDWKIEN are set
3
1
read-write
0
Power-down Mode Wake-up Interrupt Disabled
#0
1
Power-down Mode Wake-up Interrupt Enabled
#1
PDWKIF
Power-down Mode Wake-up Interrupt Flag
Set by power down wake-up event indicates that resume from Power-down mode
The flag is set if the GPIO, USBH, USBD, UART, TIMER, WDT, RTC or I2C wake-up occurred.
Note1: Write 1 to clear the bit to zero.
Note2: This bit works only if PDWKIEN (CLK_PWRCTL[24]) set to 1
2
1
read-write
PDWKPSC
PDWKPSC Counter\nAssuming the HXT is stable after the PDWKPSC x 256 HXT cycles, Clock controller would not output clock to system before the counter reaches (PDWKPSC x 256).
8
16
read-write
PDWTCPU
Control Power-down Entry Condition\n
24
1
read-write
0
Chip enters Power-down mode when the HXTEN bit is set to 1
#0
1
Chip enters Power-down mode when the both PDWTCPU and HXTEN bits are set to 1 and CPU run WFI instruction
#1
GCR
GCR Register Map
GCR
0x0
0x0
0x24
registers
n
0x100
0x8
registers
n
0x30
0x1C
registers
n
0x50
0x10
registers
n
0x6C
0x1C
registers
n
SYS_AHBCTL
SYS_AHBCTL
AHB Bus Control Register
0x20
read-write
n
0x0
0x0
CPUHPRI
Enable Raising the Priority of CPU in IRQ Period\nIt can be used to reduce the interrupt latency in a real-time system. Setting this bit, the CPU will have the highest AHB priority.\n
4
1
read-write
0
No effect
#0
1
The function that CPU has the highest AHB bus priority in IRQ period Enabled
#1
PRISEL
AHB Bus Arbitration Mode Control
The priority mode for fixed priority mode is I2S SDH USBH USBD SPIM M4(S) M4(D) M4(I)
0
1
read-write
0
Fixed priority mode
#0
1
Round-robin priority mode (rotate)
#1
PRISTS
Interrupt Active Status in CPUHPRI Enabled Mode\nIf it is high, the CPU has the highest AHB bus priority. It is set when the CPUHPRI is enabled and the external IRQ is active. This bit is cleared by writing 1 to it. Therefore, if exiting from the IRQ when CPUHPRI is enabled, PRISTS must be cleared. Otherwise, the CPU always has the highest AHB bus priority.\n
5
1
read-write
0
No effect
#0
1
The highest AHB bus priority for CPU is active
#1
SYS_BOOTSET
SYS_BOOTSET
System Power-on Configuration Register
0x4
read-write
n
0x0
0x0
BOOTSET
System Mode Configuration\nNote: If BOOTSET is equal to ICE Mode, the software cannot change BOOTSET to other mode. But other modes don't have this limitation.
0
4
read-write
6
Boot from ICE Mode with external SPI Flash
#0110
7
Boot from ICE Mode with SPI Flash
#0111
11
Boot from ICP Mode
#1011
13
Boot from external SPI Flash
#1101
14
Boot from USB
#1110
15
Boot from SPI Flash
#1111
SYS_EPADPUEN
SYS_EPADPUEN
Embedded SPI Flash Pad Pull-up Enable Control Register
0x6C
-1
read-write
n
0x0
0x0
EPADPUEN
Embedded SPI Flash Pad Pull-up Enable Control\nNote: In Power-down mode, user should set EPADPUEN[4:0] to 0x12.
0
5
read-write
0
All embedded pads are pull-up Disabled
#00000
18
Only SPI Flash MISO pads are pull-up Enabled
#10010
31
All embedded pads are pull-up Enabled
#11111
SYS_GPADS
SYS_GPADS
GPIOA Driving Strength Control Register
0x70
read-write
n
0x0
0x0
PA0DS
PA.0 Driving Strength Control\nSetting driving strength for PA.0 analog / digital combo pin.\n
0
3
read-write
0
2.0 mA (Default)
#000
1
6.5 mA
#001
2
8.7 mA
#010
3
13.0 mA
#011
4
15.2 mA
#100
5
19.5 mA
#101
6
21.7 mA
#110
7
26.1 mA
#111
PA1DS
PA.1 Driving Strength Control\nSetting driving strength for PA.1 analog / digital combo pin.\n
4
3
read-write
0
2.0 mA (Default)
#000
1
6.5 mA
#001
2
8.7 mA
#010
3
13.0 mA
#011
4
15.2 mA
#100
5
19.5 mA
#101
6
21.7 mA
#110
7
26.1 mA
#111
PA2DS
PA.2 Driving Strength Control\nSetting driving strength for PA.2 analog / digital combo pin.\n
8
3
read-write
0
2.0 mA (Default)
#000
1
6.5 mA
#001
2
8.7 mA
#010
3
13.0 mA
#011
4
15.2 mA
#100
5
19.5 mA
#101
6
21.7 mA
#110
7
26.1 mA
#111
PA3DS
PA.3 Driving Strength Control\nSetting driving strength for PA.3 analog / digital combo pin.\n
12
3
read-write
0
2.0 mA (Default)
#000
1
6.5 mA
#001
2
8.7 mA
#010
3
13.0 mA
#011
4
15.2 mA
#100
5
19.5 mA
#101
6
21.7 mA
#110
7
26.1 mA
#111
PA4DS
PA.4 Driving Strength Control\nSetting driving strength for PA.4 analog / digital combo pin.\n
16
3
read-write
0
2.0 mA (Default)
#000
1
6.5 mA
#001
2
8.7 mA
#010
3
13.0 mA
#011
4
15.2 mA
#100
5
19.5 mA
#101
6
21.7 mA
#110
7
26.1 mA
#111
PA5DS
PA.5 Driving Strength Control\nSetting driving strength for PA.5 analog / digital combo pin.\n
20
3
read-write
0
2.0 mA (Default)
#000
1
6.5 mA
#001
2
8.7 mA
#010
3
13.0 mA
#011
4
15.2 mA
#100
5
19.5 mA
#101
6
21.7 mA
#110
7
26.1 mA
#111
PA6DS
PA.6 Driving Strength Control\nSetting driving strength for PA.6 analog / digital combo pin.\n
24
3
read-write
0
2.0 mA (Default)
#000
1
6.5 mA
#001
2
8.7 mA
#010
3
13.0 mA
#011
4
15.2 mA
#100
5
19.5 mA
#101
6
21.7 mA
#110
7
26.1 mA
#111
PA7DS
PA.7 Driving Strength Control\nSetting driving strength for PA.7 analog / digital combo pin.\n
28
3
read-write
0
2.0 mA (Default)
#000
1
6.5 mA
#001
2
8.7 mA
#010
3
13.0 mA
#011
4
15.2 mA
#100
5
19.5 mA
#101
6
21.7 mA
#110
7
26.1 mA
#111
SYS_GPAIBE
SYS_GPAIBE
GPIOA Input Buffer Enable Control Register
0x74
-1
read-write
n
0x0
0x0
CMOSENx
Note: If both Schmitt Trigger and CMOS input buffer are set to 0, the input signal from PAD will always be zero.
8
8
read-write
0
PA.x CMOS Input Buffer Disabled. (Default)
0
1
PA.x CMOS Input Buffer Enabled
1
DINONx
Note1: If setting to 0, the input signal from PAD will always be zero.\nNote2: If using PA.0~PA.7 as analog pads, remember to disable input buffer.
16
8
read-write
0
PA.x Input Buffer Disabled
0
1
PA.x Input Buffer Enabled (Default)
1
IBSELx
None
0
8
read-write
0
PA.x CMOS Input Buffer (Default)
0
1
PA.x Schmitt Trigger Input Buffer
1
SMTENx
Note: If both Schmitt Trigger and CMOS input buffer are set to 0, the input signal from PAD will always be zero.
24
7
read-write
0
PA.x schmitt Trigger Input Buffer Disabled
0
1
PA.x schmitt Trigger Input Buffer Enabled (Default)
1
SYS_GPA_MFPH
SYS_GPA_MFPH
GPIOA High Byte Multi-function Control Register
0x34
read-write
n
0x0
0x0
PA10MFP
PA.10 Multi-function Pin Selection
8
3
read-write
PA11MFP
PA.11 Multi-function Pin Selection
12
3
read-write
PA12MFP
PA.12 Multi-function Pin Selection
16
3
read-write
PA13MFP
PA.13 Multi-function Pin Selection
20
3
read-write
PA14MFP
PA.14 Multi-function Pin Selection
24
3
read-write
PA15MFP
PA.15 Multi-function Pin Selection
28
3
read-write
PA8MFP
PA.8 Multi-function Pin Selection
0
3
read-write
PA9MFP
PA.9 Multi-function Pin Selection
4
3
read-write
SYS_GPA_MFPL
SYS_GPA_MFPL
GPIOA Low Byte Multi-function Control Register
0x30
read-write
n
0x0
0x0
PA0MFP
PA.0 Multi-function Pin Selection
0
3
read-write
PA1MFP
PA.1 Multi-function Pin Selection
4
3
read-write
PA2MFP
PA.2 Multi-function Pin Selection
8
3
read-write
PA3MFP
PA.3 Multi-function Pin Selection
12
3
read-write
PA4MFP
PA.4 Multi-function Pin Selection
16
3
read-write
PA5MFP
PA.5 Multi-function Pin Selection
20
3
read-write
PA6MFP
PA.6 Multi-function Pin Selection
24
3
read-write
PA7MFP
PA.7 Multi-function Pin Selection
28
3
read-write
SYS_GPBIBE
SYS_GPBIBE
GPIOB Input Buffer Enable Control Register
0x78
-1
read-write
n
0x0
0x0
CMOSENx
Note: If both Schmitt Trigger and CMOS input buffer are set to 0, the input signal from PAD will always be zero.
0
16
read-write
0
PB.x CMOS Input Buffer Disabled. (Default)
0
1
PB.x CMOS Input Buffer Enabled
1
SMTENx
Note: If both Schmitt Trigger and CMOS input buffer are set to 0, the input signal from PAD will always be zero.
16
15
read-write
0
PB.x Schmitt Trigger Input Buffer Disabled
0
1
PB.x Schmitt Trigger Input Buffer Enabled (Default)
1
SYS_GPB_MFPH
SYS_GPB_MFPH
GPIOB High Byte Multi-function Control Register
0x3C
read-write
n
0x0
0x0
PB10MFP
PB.10 Multi-function Pin Selection
8
3
read-write
PB11MFP
PB.11 Multi-function Pin Selection
12
3
read-write
PB12MFP
PB.12 Multi-function Pin Selection
16
3
read-write
PB13MFP
PB.13 Multi-function Pin Selection
20
3
read-write
PB14MFP
PB.14 Multi-function Pin Selection
24
3
read-write
PB15MFP
PB.15 Multi-function Pin Selection
28
3
read-write
PB8MFP
PB.8 Multi-function Pin Selection
0
3
read-write
PB9MFP
PB.9 Multi-function Pin Selection
4
3
read-write
SYS_GPB_MFPL
SYS_GPB_MFPL
GPIOB Low Byte Multi-function Control Register
0x38
read-write
n
0x0
0x0
PB0MFP
PB.0 Multi-function Pin Selection
0
3
read-write
PB1MFP
PB.1 Multi-function Pin Selection
4
3
read-write
PB2MFP
PB.2 Multi-function Pin Selection
8
3
read-write
PB3MFP
PB.3 Multi-function Pin Selection
12
3
read-write
PB4MFP
PB.4 Multi-function Pin Selection
16
3
read-write
PB5MFP
PB.5 Multi-function Pin Selection
20
3
read-write
PB6MFP
PB.6 Multi-function Pin Selection
24
3
read-write
PB7MFP
PB.7 Multi-function Pin Selection
28
3
read-write
SYS_GPCIBE
SYS_GPCIBE
GPIOC Input Buffer Enable Control Register
0x7C
-1
read-write
n
0x0
0x0
CMOSENx
Note: If both Schmitt Trigger and CMOS input buffer are set to 0, the input signal from PAD will always be zero.
0
15
read-write
0
PC.x CMOS Input Buffer Disabled. (Default)
0
1
PC.x CMOS Input Buffer Enabled
1
SMTENx
Note: If both Schmitt Trigger and CMOS input buffer are set to 0, the input signal from PAD will always be zero.
16
15
read-write
0
PC.x Schmitt Trigger Input Buffer Disabled
0
1
PC.x Schmitt Trigger Input Buffer Enabled (Default)
1
SYS_GPC_MFPH
SYS_GPC_MFPH
GPIOC High Byte Multi-function Control Register
0x44
read-write
n
0x0
0x0
PC10MFP
PC.10 Multi-function Pin Selection
8
3
read-write
PC11MFP
PC.11 Multi-function Pin Selection
12
3
read-write
PC12MFP
PC.12 Multi-function Pin Selection
16
3
read-write
PC13MFP
PC.13 Multi-function Pin Selection
20
3
read-write
PC14MFP
PC.14 Multi-function Pin Selection
24
3
read-write
PC8MFP
PC.8 Multi-function Pin Selection
0
3
read-write
PC9MFP
PC.9 Multi-function Pin Selection
4
3
read-write
SYS_GPC_MFPL
SYS_GPC_MFPL
GPIOC Low Byte Multi-function Control Register
0x40
read-write
n
0x0
0x0
PC0MFP
PC.0 Multi-function Pin Selection
0
3
read-write
PC1MFP
PC.1 Multi-function Pin Selection
4
3
read-write
PC2MFP
PC.2 Multi-function Pin Selection
8
3
read-write
PC3MFP
PC.3 Multi-function Pin Selection
12
3
read-write
PC4MFP
PC.4 Multi-function Pin Selection
16
3
read-write
PC5MFP
PC.5 Multi-function Pin Selection
20
3
read-write
PC6MFP
PC.6 Multi-function Pin Selection
24
3
read-write
PC7MFP
PC.7 Multi-function Pin Selection
28
3
read-write
SYS_GPDDS
SYS_GPDDS
GPIOD Driving Strength Control Register
0x84
read-write
n
0x0
0x0
PD2DS
PD.2 Driving Strength Control\nSetting driving strength for PD.2 analog / digital combo pin.\n
0
3
read-write
0
2.0 mA (Default)
#000
1
6.5 mA
#001
2
8.7 mA
#010
3
13.0 mA
#011
4
15.2 mA
#100
5
19.5 mA
#101
6
21.7 mA
#110
7
26.1 mA
#111
PD3DS
PD.3 Driving Strength Control\nSetting driving strength for PD.3 analog / digital combo pin.\n
4
3
read-write
0
2.0 mA (Default)
#000
1
6.5 mA
#001
2
8.7 mA
#010
3
13.0 mA
#011
4
15.2 mA
#100
5
19.5 mA
#101
6
21.7 mA
#110
7
26.1 mA
#111
PD4DS
PD.4 Driving Strength Control\nSetting driving strength for PD.4 analog / digital combo pin.\n
8
3
read-write
0
2.0 mA (Default)
#000
1
6.5 mA
#001
2
8.7 mA
#010
3
13.0 mA
#011
4
15.2 mA
#100
5
19.5 mA
#101
6
21.7 mA
#110
7
26.1 mA
#111
SYS_GPDIBE
SYS_GPDIBE
GPIOD Input Buffer Enable Control Register
0x80
-1
read-write
n
0x0
0x0
CMOSENx
Note: If both Schmitt Trigger and CMOS input buffer are set to 0, the input signal from PAD will always be zero.
0
2
read-write
0
PD.x CMOS Input Buffer Disabled (Default)
0
1
PD.x CMOS Input Buffer Enabled
1
DINONx
Note1: If setting to 0, the input signal from PAD will always be zero.\nNote2: If using PD.2, PD.3, and PD.4 as analog pads, user must disable PD.2, PD.3, and PD.4 input buffer.
18
3
read-write
0
PD.x Input Buffer Disabled
0
1
PD.x Input Buffer Enabled (Default)
1
IBSELx
None
2
3
read-write
0
PD.x CMOS Input Buffer (Default)
0
1
PD.x Schmitt Trigger Input Buffer
1
SMTENx
Note: If both Schmitt Trigger and CMOS input buffer are set to 0, the input signal from PAD will always be zero.
16
2
read-write
0
PD.x Schmitt Trigger Input Buffer Disabled
0
1
PD.x Schmitt Trigger Input Buffer Enabled (Default)
1
SYS_GPD_MFPL
SYS_GPD_MFPL
GPIOD Low Byte Multi-function Control Register
0x48
read-write
n
0x0
0x0
PD0MFP
PD.0 Multi-function Pin Selection
0
3
read-write
PD1MFP
PD.1 Multi-function Pin Selection
4
3
read-write
PD2MFP
PD.2 Multi-function Pin Selection
8
3
read-write
PD3MFP
PD.3 Multi-function Pin Selection
12
3
read-write
PD4MFP
PD.4 Multi-function Pin Selection
16
3
read-write
SYS_IPRST0
SYS_IPRST0
Peripheral Reset Control Register 0
0x8
-1
read-write
n
0x0
0x0
CHIPRST
Chip One-shot Reset\nSetting this bit will reset the whole chip, including processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.\n
1
1
read-write
0
Chip normal operation
#0
1
Chip one-shot reset
#1
CPURST
Processor Core One-shot Reset\nSetting this bit will only reset the processor core, and this bit will automatically return to 0 after the 2 clock cycles.\n
0
1
read-write
0
Processor core normal operation
#0
1
Processor core one-shot reset
#1
SYS_IPRST1
SYS_IPRST1
Peripheral Reset Control Register 1
0x14
read-write
n
0x0
0x0
ADCRST
ADC Controller Reset\nSet this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
28
1
read-write
0
ADC controller normal operation
#0
1
ADC controller reset
#1
GPIORST
GPIO Controller Reset\nSet this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
27
1
read-write
0
GPIO controller normal operation
#0
1
GPIO controller reset
#1
I2C0RST
I2C0 Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
8
1
read-write
0
I2C0 controller normal operation
#0
1
I2C0 controller reset
#1
I2C1RST
I2C1 Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
9
1
read-write
0
I2C1 controller normal operation
#0
1
I2C1 controller reset
#1
I2SRST
I2S Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
17
1
read-write
0
I2S controller normal operation
#0
1
I2S controller reset
#1
PWMRST
PWM Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
7
1
read-write
0
PWM controller normal operation
#0
1
PWM controller reset
#1
SDHRST
SDH Controller Reset\nSet this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
24
1
read-write
0
SDH controller normal operation
#0
1
SDH controller reset
#1
SPI0RST
SPI0 Controller Reset\nSet this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
30
1
read-write
0
SPI0 controller normal operation
#0
1
SPI0 controller reset
#1
SPI1RST
SPI1 Controller Reset\nSet this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
31
1
read-write
0
SPI1 controller normal operation
#0
1
SPI1 controller reset
#1
SPIMRST
SPIM Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
10
1
read-write
0
SPIM controller normal operation
#0
1
SPIM controller reset
#1
SRAMRST
SRAM Controller Reset\nSet this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
25
1
read-write
0
SRAM controller normal operation
#0
1
SRAM controller reset
#1
TMR0RST
Timer0 Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
2
1
read-write
0
Timer0 controller normal operation
#0
1
Timer0 controller reset
#1
TMR1RST
Timer1 Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
3
1
read-write
0
Timer1 controller normal operation
#0
1
Timer1 controller reset
#1
TMR2RST
Timer2 Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
5
1
read-write
0
Timer2 controller normal operation
#0
1
Timer2 controller reset
#1
TMR3RST
Timer3 Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
12
1
read-write
0
Timer3 controller normal operation
#0
1
Timer3 controller reset
#1
UART0RST
UART0 Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
0
1
read-write
0
UART0 controller normal operation
#0
1
UART0 controller reset
#1
UART1RST
UART1 Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
1
1
read-write
0
UART1 controller normal operation
#0
1
UART1 controller reset
#1
UART2RST
UART2 Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
6
1
read-write
0
UART2 controller normal operation
#0
1
UART2 controller reset
#1
USBDRST
USB Device Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
11
1
read-write
0
USB Device controller normal operation
#0
1
USB Device controller reset
#1
USBHRST
USB Host Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
18
1
read-write
0
USB Host controller normal operation
#0
1
USB Host controller reset
#1
WDTFRST
WDT Hardware Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
4
1
read-write
0
WDT controller normal operation
#0
1
WDT controller reset
#1
WDTPRST
WDT Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
13
1
read-write
0
WDT controller normal operation
#0
1
WDT controller reset
#1
SYS_LVDCTL
SYS_LVDCTL
Low Voltage Detection Control Register
0xC
-1
read-write
n
0x0
0x0
LVDEN
Low Voltage Detection Enable Control\n
2
1
read-write
0
Detection Disabled
#0
1
Detection Enabled
#1
LVDIF
Low Voltage Detect Flag\nNote: This bit is useful when LVDEN is enabled.
0
1
read-write
0
Low voltage Period
#0
1
Normal voltage Period
#1
LVDSEL
Low Voltage Detection Level Selection\n
1
1
read-write
0
The threshold level is 2.6V
#0
1
The threshold level is 2.8V
#1
LVREN
Low Voltage Reset Enable Control\nNote: The voltage threshold level is 2.4V
3
1
read-write
0
Low Voltage Reset Disabled
#0
1
Low Voltage Reset Enabled. (default)
#1
PORENB
Power on Reset Enable Control\n
4
1
read-write
0
Function Enabled. (Default)
#0
1
Function Disabled
#1
SYS_LVMPADDR
SYS_LVMPADDR
Load VECMAP Address Parameter Control Register
0x50
-1
read-write
n
0x0
0x0
ADDR
Load VECMAP Address Register\nThis is the start address for mapping to the address 0x0000_0000 in VECMAP function. Only when CPU reset or setting RLDVMP to 1, the loading signal will be loaded to the SYS_RVMPADDR register. \nNote: This register can only be reset by CHIPRST and HW Reset.
0
32
read-write
SYS_LVMPLEN
SYS_LVMPLEN
Load VECMAP Length Parameter Control Register
0x54
-1
read-write
n
0x0
0x0
LEN
LD_VECMAP Length\nThis is the memory length loading signal for mapping to the address 0x0000_0000 in VECMAP function. Only when OCPU reset or setting RLDVMP to 1, the loading signal will be loaded to the SYS_RVMPLEN register.\nNote1: The maximum mapping length is 128K bytes\nNote2: This register only can be reset by CHIPRST and HW Reset.
0
8
read-write
SYS_NMICTL
SYS_NMICTL
Non Maskable Interrupt Control Register
0x18
read-write
n
0x0
0x0
EINT0IEN
External GPIO Group 0 NMI Source Enable Control \n
3
1
read-write
0
External GPIO group 0 NMI source Disabled
#0
1
External GPIO group 0 NMI source Enabled
#1
EINT0IF
External GPIO Group 0 Interrupt Flag (Read Only)\n
19
1
read-only
0
External GPIO group 0 interrupt is deasserted
#0
1
External GPIO group 0 interrupt is asserted
#1
EINT1IEN
External GPIO Group 1 NMI Source Enable Control \n
4
1
read-write
0
External GPIO group 1 NMI source Disabled
#0
1
External GPIO group 1 NMI source Enabled
#1
EINT1IF
External GPIO Group 1 Interrupt Flag (Read Only)\n
20
1
read-only
0
External GPIO group 1 interrupt is deasserted
#0
1
External GPIO group 1 interrupt is asserted
#1
EINT2IEN
External GPIO Group 2 NMI Source Enable Control \n
5
1
read-write
0
External GPIO group 2 NMI source Disabled
#0
1
External GPIO group 2 NMI source Enabled
#1
EINT2IF
External GPIO Group 2 Interrupt Flag (Read Only)\n
21
1
read-only
0
External GPIO group 2 interrupt is deasserted
#0
1
External GPIO group 2 interrupt is asserted
#1
EINT3IEN
External GPIO Group 3 NMI Source Enable Control \n
6
1
read-write
0
External GPIO group 3 NMI source Disabled
#0
1
External GPIO group 3 NMI source Enabled
#1
EINT3IF
External GPIO Group 3 Interrupt Flag (Read Only)\n
22
1
read-only
0
External GPIO group 3 interrupt is deasserted
#0
1
External GPIO group 3 interrupt is asserted
#1
LVDIEN
Low Voltage Detect NMI Source Enable Control \n
7
1
read-write
0
LVD NMI source Disabled
#0
1
LVD NMI source Enabled
#1
LVDIF
Low Voltage Detect (LVD) Interrupt Flag (Read Only)\n
23
1
read-only
0
LVD interrupt is deasserted
#0
1
LVD interrupt is asserted
#1
PORIEN
Power on Interrupt NMI Source Enable Control\n
2
1
read-write
0
POR NMI source Disabled
#0
1
POR NMI source Enabled
#1
PORIF
Power on Reset (POR) Interrupt Flag (Read Only)\n
18
1
read-only
0
POR interrupt is deasserted
#0
1
POR interrupt is asserted
#1
RTCIEN
RTC Interrupt NMI Source Enable Control\n
0
1
read-write
0
RTC NMI source Disabled
#0
1
RTC NMI source Enabled
#1
RTCIF
RTC Interrupt Flag (Read Only)\n
16
1
read-only
0
RTC interrupt is deasserted
#0
1
RTC interrupt is asserted
#1
WDTIEN
WDT Interrupt NMI Source Enable Control\n
1
1
read-write
0
WDT NMI source Disabled
#0
1
WDT NMI source Enabled
#1
WDTIF
Watch Dog Timer (WDT) Interrupt Flag (Read Only)\n
17
1
read-only
0
WDT interrupt is deasserted
#0
1
WDT interrupt is asserted
#1
SYS_PDID
SYS_PDID
Part Device Identification Number Register
0x0
-1
read-only
n
0x0
0x0
PDID
Part Device Identification Number (Read Only)\nThis register reflects device part number code. Software can read this register to identify which device is used.
0
24
read-only
SYS_RSTDBCNT
SYS_RSTDBCNT
External NRESET Pin De-bounce Counter Control Register
0x100
-1
read-write
n
0x0
0x0
RSTDBCNT
External NRESET De-bounce Counter \n
0
16
read-write
SYS_RSTDBEN
SYS_RSTDBEN
External NRESET Pin De-bounce Control Register
0x104
read-write
n
0x0
0x0
RSTDBEN
External NRESET De-bounce Control\nThis bit is to enable or disable the external nRESET pin de-bounce process. \n
0
1
read-write
0
De-bounce function Disabled
#0
1
De-bounce function Enabled
#1
SYS_RSTSTS
SYS_RSTSTS
Reset Status Control Register
0x1C
read-write
n
0x0
0x0
CPURF
Reset Status for Software Setting\nNote: Write 1 to clear this bit to 0.
3
1
read-write
0
No effect
#0
1
The CPURST had be triggered to reset the CPU or the CHIPREST had be triggered to reset the system
#1
LVRF
Reset Status for Low Voltage Reset\nNote: Write 1 to clear this bit to 0.
1
1
read-write
0
No effect
#0
1
LVR controller had issued the reset signal to reset the system
#1
PINRF
Reset Status for External NReset Pin\nNote: Write 1 to clear this bit to 0.
0
1
read-write
0
No effect
#0
1
nRESET pin had issued the reset signal to reset the system
#1
PORF
Reset Status for POR Reset
Note: Write 1 to clear this bit to 0.
4
1
read-write
0
No effect
#0
1
Power-on Reset (POR) had issued the reset signal to reset the system
#1
WDTRF
Reset Status for Watch Dog Reset\nNote: Write 1 to clear this bit to 0.
2
1
read-write
0
No effect
#0
1
The watchdog timer or window watchdog timer had issued the reset signal to reset the system
#1
SYS_RVMPADDR
SYS_RVMPADDR
Real VECMAP Address Parameter Register
0x58
-1
read-only
n
0x0
0x0
ADDR
Real VECMAP Address Register Parameter\nThis is the real start address parameter for mapping to the address 0x0000_0000 in VECMAP function. (Default value is mapping to IBR_ROM start address.)\nNote: This register is only loaded from ADDR during CPU Reset process (SYS_IPRST0[0]) or setting RLDVMP.
0
32
read-only
SYS_RVMPLEN
SYS_RVMPLEN
Real VECMAP Length Parameter Control Register
0x5C
-1
read-write
n
0x0
0x0
LEN
Real VECMAP Length\nThis is the real memory length for mapping to the address 0x0000_0000 in VECMAP function. \nNote1: Read Only\nNote2: These bits are only loaded from LEN when setting CPURST (SYS_IPRST0[0]) or setting RLDVMP.
24
8
read-write
RLDVMP
Load VECMAP Parameter Signal\nNote: This bit is auto cleared to 0
0
1
read-write
0
No effect
#0
1
Load VECMAP Address and Length
#1
SYS_WAKEUP
SYS_WAKEUP
Wake-up Control and Status Resister
0x10
read-write
n
0x0
0x0
GPIOWE
GPIO Wake-up Enable Control\n
2
1
read-write
0
GPIO wake-up Disabled
#0
1
GPIO wake-up Enabled
#1
GPIOWF
GPIO Wake-up Flag\nNote: Write 1 to clear this bit
18
1
read-write
0
GPIO wake-up source is deasserted
#0
1
GPIO wake-up source is asserted
#1
I2C0WE
I2C0 Wake-up Enable Control\n
0
1
read-write
0
I2C0 wake-up Disabled
#0
1
I2C0 wake-up Enabled
#1
I2C0WF
I2C0 Wake-up Flag\nNote: Write 1 to clear this bit
16
1
read-write
0
I2C0 wake-up source is deasserted
#0
1
I2C0 wake-up source is asserted
#1
I2C1WE
I2C1 Wake-up Enable Control\n
1
1
read-write
0
I2C1 wake-up Disabled
#0
1
I2C1 wake-up Enabled
#1
I2C1WF
I2C1 Wake-up Flag\nNote: Write 1 to clear this bit
17
1
read-write
0
I2C1 wake-up source is deasserted
#0
1
I2C1 wake-up source is asserted
#1
RTCWE
RTC Wake-up Enable Control\n
3
1
read-write
0
RTC wake-up Disabled
#0
1
RTC wake-up Enabled
#1
RTCWF
RTC Wake-up Flag\nNote: Write 1 to clear this bit
19
1
read-write
0
RTC wake-up source is deasserted
#0
1
RTC wake-up source is asserted
#1
TMR0WE
Timer0 Wake-up Enable Control\n
5
1
read-write
0
Timer0 wake-up Disabled
#0
1
Timer0 wake-up Enabled
#1
TMR0WF
Timer0 Wake-up Flag\nNote: Write 1 to clear this bit
21
1
read-write
0
Timer0 wake-up source is deasserted
#0
1
Timer0 wake-up source is asserted
#1
TMR1WE
Timer1 Wake-up Enable Control\n
6
1
read-write
0
Timer1 wake-up Disabled
#0
1
Timer1 wake-up Enabled
#1
TMR1WF
Timer1 Wake-up Flag\nNote: Write 1 to clear this bit
22
1
read-write
0
Timer1 wake-up source is deasserted
#0
1
Timer1 wake-up source is asserted
#1
TMR2WE
Timer2 Wake-up Enable Control\n
7
1
read-write
0
Timer2 wake-up Disabled
#0
1
Timer2 wake-up Enabled
#1
TMR2WF
Timer2 Wake-up Flag\nNote: Write 1 to clear this bit
23
1
read-write
0
Timer2 wake-up source is deasserted
#0
1
Timer2 wake-up source is asserted
#1
TMR3WE
Timer3 Wake-up Enable Control\n
8
1
read-write
0
Timer3 wake-up Disabled
#0
1
Timer3 wake-up Enabled
#1
TMR3WF
Timer3 Wake-up Flag\nNote: Write 1 to clear this bit
24
1
read-write
0
Timer3 wake-up source is deasserted
#0
1
Timer3 wake-up source is asserted
#1
UART0WE
UART0 Wake-up Enable Control\n
9
1
read-write
0
UART0 wake-up Disabled
#0
1
UART0 wake-up Enabled
#1
UART0WF
UART0 Wake-up Flag\nNote: Write 1 to clear this bit
25
1
read-write
0
UART0 wake-up source is deasserted
#0
1
UART0 wake-up source is asserted
#1
UART1WE
UART1 Wake-up Enable Control\n
10
1
read-write
0
UART1 wake-up Disabled
#0
1
UART1 wake-up Enabled
#1
UART1WF
UART1 Wake-up Flag\nNote: Write 1 to clear this bit
26
1
read-write
0
UART1 wake-up source is deasserted
#0
1
UART1 wake-up source is asserted
#1
UART2WE
UART2 Wake-up Enable Control\n
11
1
read-write
0
UART2 wake-up Disabled
#0
1
UART2 wake-up Enabled
#1
UART2WF
UART2 Wake-up Flag\nNote: Write 1 to clear this bit
27
1
read-write
0
UART2 wake-up source is deasserted
#0
1
UART2 wake-up source is asserted
#1
USBDWE
USB Device Wake-up Enable Control\n
12
1
read-write
0
USB Device wake-up Disabled
#0
1
USB Device wake-up Enabled
#1
USBDWF
USB Device Wake-up Flag\nNote: Write 1 to clear this bit
28
1
read-write
0
USB Device wake-up source is deasserted
#0
1
USB Device wake-up source is asserted
#1
USBHWE
USB Host Wake-up Enable Control\n
13
1
read-write
0
USB Host wake-up Disabled
#0
1
USB Host wake-up Enabled
#1
USBHWF
USB Host Wake-up Flag\nNote: Write 1 to clear this bit
29
1
read-write
0
USB Host wake-up source is deasserted
#0
1
USB Host wake-up source is asserted
#1
WDTWE
WDT Wake-up Enable Control\n
4
1
read-write
0
WDT wake-up Disabled
#0
1
WDT wake-up Enabled
#1
WDTWF
WDT Wake-up Flag\nNote: Write 1 to clear this bit
20
1
read-write
0
WDT wake-up source is deasserted
#0
1
WDT wake-up source is asserted
#1
GPIO
GPIO Register Map
GPIO
0x0
0x0
0x40
registers
n
0x70
0x4
registers
n
0x80
0x3C
registers
n
DBCTL
GPIO_DBCTL
Interrupt Event (EINT) De-bounce Control
0x70
read-write
n
0x0
0x0
DBCLKSEL
De-bounce Sampling Cycle Selection\n
4
4
read-write
0
Sample interrupt input once per 1 APB clocks
#0000
1
Sample interrupt input once per 2 APB clocks
#0001
2
Sample interrupt input once per 4 APB clocks
#0010
3
Sample interrupt input once per 8 APB clocks
#0011
4
Sample interrupt input once per 16 APB clocks
#0100
5
Sample interrupt input once per 32 APB clocks
#0101
6
Sample interrupt input once per 64 APB clocks
#0110
7
Sample interrupt input once per 128 APB clocks
#0111
8
Sample interrupt input once per 256 APB clocks
#1000
9
Sample interrupt input once per 512 APB clocks
#1001
10
Sample interrupt input once per 1024 APB clocks
#1010
11
Sample interrupt input once per 2048 APB clocks
#1011
12
Sample interrupt input once per 4096 APB clocks
#1100
13
Sample interrupt input once per 8192 APB clocks
#1101
14
Sample interrupt input once per 16384 APB clocks
#1110
15
Sample interrupt input once per 32768 APB clocks
#1111
DBEN0
EINT (EINT0~EINT3) De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding EINT. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is regarded as the signal bounce and will not trigger the interrupt. The de- bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [7:4]).\n
0
1
read-write
0
EINTn de-bounce function Disabled
#0
1
EINTn de-bounce function Enabled
#1
DBEN1
EINT (EINT0~EINT3) De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding EINT. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is regarded as the signal bounce and will not trigger the interrupt. The de- bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [7:4]).\n
1
1
read-write
0
EINTn de-bounce function Disabled
#0
1
EINTn de-bounce function Enabled
#1
DBEN2
EINT (EINT0~EINT3) De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding EINT. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is regarded as the signal bounce and will not trigger the interrupt. The de- bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [7:4]).\n
2
1
read-write
0
EINTn de-bounce function Disabled
#0
1
EINTn de-bounce function Enabled
#1
DBEN3
EINT (EINT0~EINT3) De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding EINT. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is regarded as the signal bounce and will not trigger the interrupt. The de- bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [7:4]).\n
3
1
read-write
0
EINTn de-bounce function Disabled
#0
1
EINTn de-bounce function Enabled
#1
INTCTL
GPIO_INTCTL
Interrupt Latch Trigger Selection Register
0xA0
read-write
n
0x0
0x0
INTCTL
Interrupt Request Source Control\n
8
1
read-write
0
When the GPIO interrupt occurs, the GPIO interrupt controller generates 1 APB clock pulse to the NVIC
#0
1
When the GPIO interrupt occurs, the interrupt from GPIO to NVIC will keep till the CPU clear the interrupt trigger source. (GPIO_INTSTSA_B, GPIO_INTSTSC_D)
#1
INTLHEN0
Enable Latch PA.N/PB.N/PC.N/PD.N Value When EINTn Happen\n
0
1
read-write
0
No effect
#0
1
When EINTn interrupt has happened, PA_LATCHDAT, PB_LATCHDAT, PC_LATCHDAT, and PD_LATCHDAT registers will latch PA, PB, PC, and PD port values within EINTn group
#1
INTLHEN1
Enable Latch PA.N/PB.N/PC.N/PD.N Value When EINTn Happen\n
1
1
read-write
0
No effect
#0
1
When EINTn interrupt has happened, PA_LATCHDAT, PB_LATCHDAT, PC_LATCHDAT, and PD_LATCHDAT registers will latch PA, PB, PC, and PD port values within EINTn group
#1
INTLHEN2
Enable Latch PA.N/PB.N/PC.N/PD.N Value When EINTn Happen\n
2
1
read-write
0
No effect
#0
1
When EINTn interrupt has happened, PA_LATCHDAT, PB_LATCHDAT, PC_LATCHDAT, and PD_LATCHDAT registers will latch PA, PB, PC, and PD port values within EINTn group
#1
INTLHEN3
Enable Latch PA.N/PB.N/PC.N/PD.N Value When EINTn Happen\n
3
1
read-write
0
No effect
#0
1
When EINTn interrupt has happened, PA_LATCHDAT, PB_LATCHDAT, PC_LATCHDAT, and PD_LATCHDAT registers will latch PA, PB, PC, and PD port values within EINTn group
#1
WKEN0
GPIO Interrupt Wake Up System Enable Control\n
4
1
read-write
0
No effect
#0
1
EINTn can wake up the chip from Idle and Power-down mode
#1
WKEN1
GPIO Interrupt Wake Up System Enable Control\n
5
1
read-write
0
No effect
#0
1
EINTn can wake up the chip from Idle and Power-down mode
#1
WKEN2
GPIO Interrupt Wake Up System Enable Control\n
6
1
read-write
0
No effect
#0
1
EINTn can wake up the chip from Idle and Power-down mode
#1
WKEN3
GPIO Interrupt Wake Up System Enable Control\n
7
1
read-write
0
No effect
#0
1
EINTn can wake up the chip from Idle and Power-down mode
#1
INTSTSA_B
GPIO_INTSTSA_B
EINT0~3 Interrupt Trigger Source Indicator From PA and PB
0xB4
read-write
n
0x0
0x0
PAIF0
Port a Pin[N] Interrupt Source Flag
Write Operation:
When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt.
Note: Write 1 to clear the correspond interrupt source
0
1
read-write
0
No action.\nNo interrupt at PA.n
#0
1
Clear the corresponding pending interrupt.\nPA.n generates an interrupt
#1
PAIF1
Port a Pin[N] Interrupt Source Flag
Write Operation:
When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt.
Note: Write 1 to clear the correspond interrupt source
1
1
read-write
0
No action.\nNo interrupt at PA.n
#0
1
Clear the corresponding pending interrupt.\nPA.n generates an interrupt
#1
PAIF10
Port a Pin[N] Interrupt Source Flag
Write Operation:
When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt.
Note: Write 1 to clear the correspond interrupt source
10
1
read-write
0
No action.\nNo interrupt at PA.n
#0
1
Clear the corresponding pending interrupt.\nPA.n generates an interrupt
#1
PAIF11
Port a Pin[N] Interrupt Source Flag
Write Operation:
When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt.
Note: Write 1 to clear the correspond interrupt source
11
1
read-write
0
No action.\nNo interrupt at PA.n
#0
1
Clear the corresponding pending interrupt.\nPA.n generates an interrupt
#1
PAIF12
Port a Pin[N] Interrupt Source Flag
Write Operation:
When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt.
Note: Write 1 to clear the correspond interrupt source
12
1
read-write
0
No action.\nNo interrupt at PA.n
#0
1
Clear the corresponding pending interrupt.\nPA.n generates an interrupt
#1
PAIF13
Port a Pin[N] Interrupt Source Flag
Write Operation:
When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt.
Note: Write 1 to clear the correspond interrupt source
13
1
read-write
0
No action.\nNo interrupt at PA.n
#0
1
Clear the corresponding pending interrupt.\nPA.n generates an interrupt
#1
PAIF14
Port a Pin[N] Interrupt Source Flag
Write Operation:
When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt.
Note: Write 1 to clear the correspond interrupt source
14
1
read-write
0
No action.\nNo interrupt at PA.n
#0
1
Clear the corresponding pending interrupt.\nPA.n generates an interrupt
#1
PAIF15
Port a Pin[N] Interrupt Source Flag
Write Operation:
When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt.
Note: Write 1 to clear the correspond interrupt source
15
1
read-write
0
No action.\nNo interrupt at PA.n
#0
1
Clear the corresponding pending interrupt.\nPA.n generates an interrupt
#1
PAIF2
Port a Pin[N] Interrupt Source Flag
Write Operation:
When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt.
Note: Write 1 to clear the correspond interrupt source
2
1
read-write
0
No action.\nNo interrupt at PA.n
#0
1
Clear the corresponding pending interrupt.\nPA.n generates an interrupt
#1
PAIF3
Port a Pin[N] Interrupt Source Flag
Write Operation:
When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt.
Note: Write 1 to clear the correspond interrupt source
3
1
read-write
0
No action.\nNo interrupt at PA.n
#0
1
Clear the corresponding pending interrupt.\nPA.n generates an interrupt
#1
PAIF4
Port a Pin[N] Interrupt Source Flag
Write Operation:
When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt.
Note: Write 1 to clear the correspond interrupt source
4
1
read-write
0
No action.\nNo interrupt at PA.n
#0
1
Clear the corresponding pending interrupt.\nPA.n generates an interrupt
#1
PAIF5
Port a Pin[N] Interrupt Source Flag
Write Operation:
When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt.
Note: Write 1 to clear the correspond interrupt source
5
1
read-write
0
No action.\nNo interrupt at PA.n
#0
1
Clear the corresponding pending interrupt.\nPA.n generates an interrupt
#1
PAIF6
Port a Pin[N] Interrupt Source Flag
Write Operation:
When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt.
Note: Write 1 to clear the correspond interrupt source
6
1
read-write
0
No action.\nNo interrupt at PA.n
#0
1
Clear the corresponding pending interrupt.\nPA.n generates an interrupt
#1
PAIF7
Port a Pin[N] Interrupt Source Flag
Write Operation:
When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt.
Note: Write 1 to clear the correspond interrupt source
7
1
read-write
0
No action.\nNo interrupt at PA.n
#0
1
Clear the corresponding pending interrupt.\nPA.n generates an interrupt
#1
PAIF8
Port a Pin[N] Interrupt Source Flag
Write Operation:
When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt.
Note: Write 1 to clear the correspond interrupt source
8
1
read-write
0
No action.\nNo interrupt at PA.n
#0
1
Clear the corresponding pending interrupt.\nPA.n generates an interrupt
#1
PAIF9
Port a Pin[N] Interrupt Source Flag
Write Operation:
When this bit is read as 1 , it indicates that PA.n is a trigger source to generate the interrupt.
Note: Write 1 to clear the correspond interrupt source
9
1
read-write
0
No action.\nNo interrupt at PA.n
#0
1
Clear the corresponding pending interrupt.\nPA.n generates an interrupt
#1
PBIF0
Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
16
1
read-write
0
No action.\nNo interrupt at PB.n1 = PB.n generates an interrupt
#0
1
Clear the corresponding pending interrupt
#1
PBIF1
Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
17
1
read-write
0
No action.\nNo interrupt at PB.n1 = PB.n generates an interrupt
#0
1
Clear the corresponding pending interrupt
#1
PBIF10
Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
26
1
read-write
0
No action.\nNo interrupt at PB.n1 = PB.n generates an interrupt
#0
1
Clear the corresponding pending interrupt
#1
PBIF11
Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
27
1
read-write
0
No action.\nNo interrupt at PB.n1 = PB.n generates an interrupt
#0
1
Clear the corresponding pending interrupt
#1
PBIF12
Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
28
1
read-write
0
No action.\nNo interrupt at PB.n1 = PB.n generates an interrupt
#0
1
Clear the corresponding pending interrupt
#1
PBIF13
Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
29
1
read-write
0
No action.\nNo interrupt at PB.n1 = PB.n generates an interrupt
#0
1
Clear the corresponding pending interrupt
#1
PBIF14
Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
30
1
read-write
0
No action.\nNo interrupt at PB.n1 = PB.n generates an interrupt
#0
1
Clear the corresponding pending interrupt
#1
PBIF15
Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
31
1
read-write
0
No action.\nNo interrupt at PB.n1 = PB.n generates an interrupt
#0
1
Clear the corresponding pending interrupt
#1
PBIF2
Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
18
1
read-write
0
No action.\nNo interrupt at PB.n1 = PB.n generates an interrupt
#0
1
Clear the corresponding pending interrupt
#1
PBIF3
Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
19
1
read-write
0
No action.\nNo interrupt at PB.n1 = PB.n generates an interrupt
#0
1
Clear the corresponding pending interrupt
#1
PBIF4
Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
20
1
read-write
0
No action.\nNo interrupt at PB.n1 = PB.n generates an interrupt
#0
1
Clear the corresponding pending interrupt
#1
PBIF5
Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
21
1
read-write
0
No action.\nNo interrupt at PB.n1 = PB.n generates an interrupt
#0
1
Clear the corresponding pending interrupt
#1
PBIF6
Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
22
1
read-write
0
No action.\nNo interrupt at PB.n1 = PB.n generates an interrupt
#0
1
Clear the corresponding pending interrupt
#1
PBIF7
Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
23
1
read-write
0
No action.\nNo interrupt at PB.n1 = PB.n generates an interrupt
#0
1
Clear the corresponding pending interrupt
#1
PBIF8
Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
24
1
read-write
0
No action.\nNo interrupt at PB.n1 = PB.n generates an interrupt
#0
1
Clear the corresponding pending interrupt
#1
PBIF9
Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n
25
1
read-write
0
No action.\nNo interrupt at PB.n1 = PB.n generates an interrupt
#0
1
Clear the corresponding pending interrupt
#1
INTSTSC_D
GPIO_INTSTSC_D
EINT0~3 Interrupt Trigger Source Indicator From PC and PD
0xB8
read-write
n
0x0
0x0
PCIF0
Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n
0
1
read-write
0
No action.\nNo interrupt at PC.n
#0
1
Clear the corresponding pending interrupt.\nPC.n generates an interrupt
#1
PCIF1
Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n
1
1
read-write
0
No action.\nNo interrupt at PC.n
#0
1
Clear the corresponding pending interrupt.\nPC.n generates an interrupt
#1
PCIF10
Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n
10
1
read-write
0
No action.\nNo interrupt at PC.n
#0
1
Clear the corresponding pending interrupt.\nPC.n generates an interrupt
#1
PCIF11
Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n
11
1
read-write
0
No action.\nNo interrupt at PC.n
#0
1
Clear the corresponding pending interrupt.\nPC.n generates an interrupt
#1
PCIF12
Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n
12
1
read-write
0
No action.\nNo interrupt at PC.n
#0
1
Clear the corresponding pending interrupt.\nPC.n generates an interrupt
#1
PCIF13
Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n
13
1
read-write
0
No action.\nNo interrupt at PC.n
#0
1
Clear the corresponding pending interrupt.\nPC.n generates an interrupt
#1
PCIF14
Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n
14
1
read-write
0
No action.\nNo interrupt at PC.n
#0
1
Clear the corresponding pending interrupt.\nPC.n generates an interrupt
#1
PCIF2
Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n
2
1
read-write
0
No action.\nNo interrupt at PC.n
#0
1
Clear the corresponding pending interrupt.\nPC.n generates an interrupt
#1
PCIF3
Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n
3
1
read-write
0
No action.\nNo interrupt at PC.n
#0
1
Clear the corresponding pending interrupt.\nPC.n generates an interrupt
#1
PCIF4
Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n
4
1
read-write
0
No action.\nNo interrupt at PC.n
#0
1
Clear the corresponding pending interrupt.\nPC.n generates an interrupt
#1
PCIF5
Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n
5
1
read-write
0
No action.\nNo interrupt at PC.n
#0
1
Clear the corresponding pending interrupt.\nPC.n generates an interrupt
#1
PCIF6
Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n
6
1
read-write
0
No action.\nNo interrupt at PC.n
#0
1
Clear the corresponding pending interrupt.\nPC.n generates an interrupt
#1
PCIF7
Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n
7
1
read-write
0
No action.\nNo interrupt at PC.n
#0
1
Clear the corresponding pending interrupt.\nPC.n generates an interrupt
#1
PCIF8
Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n
8
1
read-write
0
No action.\nNo interrupt at PC.n
#0
1
Clear the corresponding pending interrupt.\nPC.n generates an interrupt
#1
PCIF9
Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n
9
1
read-write
0
No action.\nNo interrupt at PC.n
#0
1
Clear the corresponding pending interrupt.\nPC.n generates an interrupt
#1
PDIF0
Port D Pin[N] Interrupt Source Flag\nWrite Operation:\n
16
1
read-write
0
No action.\nNo interrupt at PD.n
#0
1
Clear the corresponding pending interrupt.\nPD.n generates an interrupt
#1
PDIF1
Port D Pin[N] Interrupt Source Flag\nWrite Operation:\n
17
1
read-write
0
No action.\nNo interrupt at PD.n
#0
1
Clear the corresponding pending interrupt.\nPD.n generates an interrupt
#1
PDIF2
Port D Pin[N] Interrupt Source Flag\nWrite Operation:\n
18
1
read-write
0
No action.\nNo interrupt at PD.n
#0
1
Clear the corresponding pending interrupt.\nPD.n generates an interrupt
#1
PDIF3
Port D Pin[N] Interrupt Source Flag\nWrite Operation:\n
19
1
read-write
0
No action.\nNo interrupt at PD.n
#0
1
Clear the corresponding pending interrupt.\nPD.n generates an interrupt
#1
PDIF4
Port D Pin[N] Interrupt Source Flag\nWrite Operation:\n
20
1
read-write
0
No action.\nNo interrupt at PD.n
#0
1
Clear the corresponding pending interrupt.\nPD.n generates an interrupt
#1
PA_DOUT
PA_DOUT
PA Data Output Value
0x8
read-write
n
0x0
0x0
DOUT0
Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
0
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output mode
#1
DOUT1
Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
1
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output mode
#1
DOUT10
Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
10
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output mode
#1
DOUT11
Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
11
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output mode
#1
DOUT12
Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
12
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output mode
#1
DOUT13
Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
13
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output mode
#1
DOUT14
Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
14
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output mode
#1
DOUT15
Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
15
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output mode
#1
DOUT2
Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
2
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output mode
#1
DOUT3
Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
3
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output mode
#1
DOUT4
Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
4
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output mode
#1
DOUT5
Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
5
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output mode
#1
DOUT6
Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
6
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output mode
#1
DOUT7
Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
7
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output mode
#1
DOUT8
Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
8
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output mode
#1
DOUT9
Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n
9
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output mode
#1
PA_INTEN
PA_INTEN
PA Interrupt Enable Control Register
0x90
read-write
n
0x0
0x0
FEIEN0
Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
0
1
read-write
0
Px.n high to low interrupt Disabled
#0
1
Px.n high to low interrupt Enabled
#1
FEIEN1
Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
1
1
read-write
0
Px.n high to low interrupt Disabled
#0
1
Px.n high to low interrupt Enabled
#1
FEIEN10
Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
10
1
read-write
0
Px.n high to low interrupt Disabled
#0
1
Px.n high to low interrupt Enabled
#1
FEIEN11
Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
11
1
read-write
0
Px.n high to low interrupt Disabled
#0
1
Px.n high to low interrupt Enabled
#1
FEIEN12
Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
12
1
read-write
0
Px.n high to low interrupt Disabled
#0
1
Px.n high to low interrupt Enabled
#1
FEIEN13
Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
13
1
read-write
0
Px.n high to low interrupt Disabled
#0
1
Px.n high to low interrupt Enabled
#1
FEIEN14
Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
14
1
read-write
0
Px.n high to low interrupt Disabled
#0
1
Px.n high to low interrupt Enabled
#1
FEIEN15
Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
15
1
read-write
0
Px.n high to low interrupt Disabled
#0
1
Px.n high to low interrupt Enabled
#1
FEIEN2
Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
2
1
read-write
0
Px.n high to low interrupt Disabled
#0
1
Px.n high to low interrupt Enabled
#1
FEIEN3
Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
3
1
read-write
0
Px.n high to low interrupt Disabled
#0
1
Px.n high to low interrupt Enabled
#1
FEIEN4
Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
4
1
read-write
0
Px.n high to low interrupt Disabled
#0
1
Px.n high to low interrupt Enabled
#1
FEIEN5
Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
5
1
read-write
0
Px.n high to low interrupt Disabled
#0
1
Px.n high to low interrupt Enabled
#1
FEIEN6
Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
6
1
read-write
0
Px.n high to low interrupt Disabled
#0
1
Px.n high to low interrupt Enabled
#1
FEIEN7
Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
7
1
read-write
0
Px.n high to low interrupt Disabled
#0
1
Px.n high to low interrupt Enabled
#1
FEIEN8
Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
8
1
read-write
0
Px.n high to low interrupt Disabled
#0
1
Px.n high to low interrupt Enabled
#1
FEIEN9
Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from high to low.\n
9
1
read-write
0
Px.n high to low interrupt Disabled
#0
1
Px.n high to low interrupt Enabled
#1
REIEN0
Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
16
1
read-write
0
Px.n low to high interrupt Disabled
#0
1
Px.n low to high interrupt Enabled
#1
REIEN1
Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
17
1
read-write
0
Px.n low to high interrupt Disabled
#0
1
Px.n low to high interrupt Enabled
#1
REIEN10
Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
26
1
read-write
0
Px.n low to high interrupt Disabled
#0
1
Px.n low to high interrupt Enabled
#1
REIEN11
Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
27
1
read-write
0
Px.n low to high interrupt Disabled
#0
1
Px.n low to high interrupt Enabled
#1
REIEN12
Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
28
1
read-write
0
Px.n low to high interrupt Disabled
#0
1
Px.n low to high interrupt Enabled
#1
REIEN13
Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
29
1
read-write
0
Px.n low to high interrupt Disabled
#0
1
Px.n low to high interrupt Enabled
#1
REIEN14
Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
30
1
read-write
0
Px.n low to high interrupt Disabled
#0
1
Px.n low to high interrupt Enabled
#1
REIEN15
Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
31
1
read-write
0
Px.n low to high interrupt Disabled
#0
1
Px.n low to high interrupt Enabled
#1
REIEN2
Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
18
1
read-write
0
Px.n low to high interrupt Disabled
#0
1
Px.n low to high interrupt Enabled
#1
REIEN3
Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
19
1
read-write
0
Px.n low to high interrupt Disabled
#0
1
Px.n low to high interrupt Enabled
#1
REIEN4
Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
20
1
read-write
0
Px.n low to high interrupt Disabled
#0
1
Px.n low to high interrupt Enabled
#1
REIEN5
Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
21
1
read-write
0
Px.n low to high interrupt Disabled
#0
1
Px.n low to high interrupt Enabled
#1
REIEN6
Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
22
1
read-write
0
Px.n low to high interrupt Disabled
#0
1
Px.n low to high interrupt Enabled
#1
REIEN7
Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
23
1
read-write
0
Px.n low to high interrupt Disabled
#0
1
Px.n low to high interrupt Enabled
#1
REIEN8
Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
24
1
read-write
0
Px.n low to high interrupt Disabled
#0
1
Px.n low to high interrupt Enabled
#1
REIEN9
Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nThe input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
25
1
read-write
0
Px.n low to high interrupt Disabled
#0
1
Px.n low to high interrupt Enabled
#1
PA_INTSRCGP
PA_INTSRCGP
PA Interrupt Event (EINT) Source Grouping
0x80
read-write
n
0x0
0x0
INTSEL0
Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
0
2
read-write
0
Px.n pin is selected as one of interrupt sources to EINT0
#00
1
Px.n pin is selected as one of interrupt sources to EINT1
#01
2
Px.n pin is selected as one of interrupt sources to EINT2
#10
3
Px.n pin is selected as one of interrupt sources to EINT3
#11
INTSEL1
Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
2
2
read-write
0
Px.n pin is selected as one of interrupt sources to EINT0
#00
1
Px.n pin is selected as one of interrupt sources to EINT1
#01
2
Px.n pin is selected as one of interrupt sources to EINT2
#10
3
Px.n pin is selected as one of interrupt sources to EINT3
#11
INTSEL10
Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
20
2
read-write
0
Px.n pin is selected as one of interrupt sources to EINT0
#00
1
Px.n pin is selected as one of interrupt sources to EINT1
#01
2
Px.n pin is selected as one of interrupt sources to EINT2
#10
3
Px.n pin is selected as one of interrupt sources to EINT3
#11
INTSEL11
Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
22
2
read-write
0
Px.n pin is selected as one of interrupt sources to EINT0
#00
1
Px.n pin is selected as one of interrupt sources to EINT1
#01
2
Px.n pin is selected as one of interrupt sources to EINT2
#10
3
Px.n pin is selected as one of interrupt sources to EINT3
#11
INTSEL12
Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
24
2
read-write
0
Px.n pin is selected as one of interrupt sources to EINT0
#00
1
Px.n pin is selected as one of interrupt sources to EINT1
#01
2
Px.n pin is selected as one of interrupt sources to EINT2
#10
3
Px.n pin is selected as one of interrupt sources to EINT3
#11
INTSEL13
Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
26
2
read-write
0
Px.n pin is selected as one of interrupt sources to EINT0
#00
1
Px.n pin is selected as one of interrupt sources to EINT1
#01
2
Px.n pin is selected as one of interrupt sources to EINT2
#10
3
Px.n pin is selected as one of interrupt sources to EINT3
#11
INTSEL14
Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
28
2
read-write
0
Px.n pin is selected as one of interrupt sources to EINT0
#00
1
Px.n pin is selected as one of interrupt sources to EINT1
#01
2
Px.n pin is selected as one of interrupt sources to EINT2
#10
3
Px.n pin is selected as one of interrupt sources to EINT3
#11
INTSEL15
Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
30
2
read-write
0
Px.n pin is selected as one of interrupt sources to EINT0
#00
1
Px.n pin is selected as one of interrupt sources to EINT1
#01
2
Px.n pin is selected as one of interrupt sources to EINT2
#10
3
Px.n pin is selected as one of interrupt sources to EINT3
#11
INTSEL2
Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
4
2
read-write
0
Px.n pin is selected as one of interrupt sources to EINT0
#00
1
Px.n pin is selected as one of interrupt sources to EINT1
#01
2
Px.n pin is selected as one of interrupt sources to EINT2
#10
3
Px.n pin is selected as one of interrupt sources to EINT3
#11
INTSEL3
Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
6
2
read-write
0
Px.n pin is selected as one of interrupt sources to EINT0
#00
1
Px.n pin is selected as one of interrupt sources to EINT1
#01
2
Px.n pin is selected as one of interrupt sources to EINT2
#10
3
Px.n pin is selected as one of interrupt sources to EINT3
#11
INTSEL4
Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
8
2
read-write
0
Px.n pin is selected as one of interrupt sources to EINT0
#00
1
Px.n pin is selected as one of interrupt sources to EINT1
#01
2
Px.n pin is selected as one of interrupt sources to EINT2
#10
3
Px.n pin is selected as one of interrupt sources to EINT3
#11
INTSEL5
Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
10
2
read-write
0
Px.n pin is selected as one of interrupt sources to EINT0
#00
1
Px.n pin is selected as one of interrupt sources to EINT1
#01
2
Px.n pin is selected as one of interrupt sources to EINT2
#10
3
Px.n pin is selected as one of interrupt sources to EINT3
#11
INTSEL6
Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
12
2
read-write
0
Px.n pin is selected as one of interrupt sources to EINT0
#00
1
Px.n pin is selected as one of interrupt sources to EINT1
#01
2
Px.n pin is selected as one of interrupt sources to EINT2
#10
3
Px.n pin is selected as one of interrupt sources to EINT3
#11
INTSEL7
Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
14
2
read-write
0
Px.n pin is selected as one of interrupt sources to EINT0
#00
1
Px.n pin is selected as one of interrupt sources to EINT1
#01
2
Px.n pin is selected as one of interrupt sources to EINT2
#10
3
Px.n pin is selected as one of interrupt sources to EINT3
#11
INTSEL8
Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
16
2
read-write
0
Px.n pin is selected as one of interrupt sources to EINT0
#00
1
Px.n pin is selected as one of interrupt sources to EINT1
#01
2
Px.n pin is selected as one of interrupt sources to EINT2
#10
3
Px.n pin is selected as one of interrupt sources to EINT3
#11
INTSEL9
Selection for Px.N As One of Interrupt Sources to EINT0, EINT1, EINT2, or EINT3\n
18
2
read-write
0
Px.n pin is selected as one of interrupt sources to EINT0
#00
1
Px.n pin is selected as one of interrupt sources to EINT1
#01
2
Px.n pin is selected as one of interrupt sources to EINT2
#10
3
Px.n pin is selected as one of interrupt sources to EINT3
#11
PA_LATCHDAT
PA_LATCHDAT
PA Interrupt Latch Value
0xA4
read-only
n
0x0
0x0
DAT0
Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
0
1
read-only
DAT1
Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
1
1
read-only
DAT10
Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
10
1
read-only
DAT11
Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
11
1
read-only
DAT12
Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
12
1
read-only
DAT13
Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
13
1
read-only
DAT14
Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
14
1
read-only
DAT15
Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
15
1
read-only
DAT2
Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
2
1
read-only
DAT3
Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
3
1
read-only
DAT4
Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
4
1
read-only
DAT5
Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
5
1
read-only
DAT6
Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
6
1
read-only
DAT7
Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
7
1
read-only
DAT8
Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
8
1
read-only
DAT9
Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n
9
1
read-only
PA_MODE
PA_MODE
PA I/O Mode Control
0x0
read-write
n
0x0
0x0
MODE0
Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
0
1
read-write
0
Px.n is in Input mode
#0
1
Px.n is in Push-pull Output mode
#1
MODE1
Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
1
1
read-write
0
Px.n is in Input mode
#0
1
Px.n is in Push-pull Output mode
#1
MODE10
Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
10
1
read-write
0
Px.n is in Input mode
#0
1
Px.n is in Push-pull Output mode
#1
MODE11
Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
11
1
read-write
0
Px.n is in Input mode
#0
1
Px.n is in Push-pull Output mode
#1
MODE12
Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
12
1
read-write
0
Px.n is in Input mode
#0
1
Px.n is in Push-pull Output mode
#1
MODE13
Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
13
1
read-write
0
Px.n is in Input mode
#0
1
Px.n is in Push-pull Output mode
#1
MODE14
Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
14
1
read-write
0
Px.n is in Input mode
#0
1
Px.n is in Push-pull Output mode
#1
MODE15
Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
15
1
read-write
0
Px.n is in Input mode
#0
1
Px.n is in Push-pull Output mode
#1
MODE2
Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
2
1
read-write
0
Px.n is in Input mode
#0
1
Px.n is in Push-pull Output mode
#1
MODE3
Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
3
1
read-write
0
Px.n is in Input mode
#0
1
Px.n is in Push-pull Output mode
#1
MODE4
Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
4
1
read-write
0
Px.n is in Input mode
#0
1
Px.n is in Push-pull Output mode
#1
MODE5
Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
5
1
read-write
0
Px.n is in Input mode
#0
1
Px.n is in Push-pull Output mode
#1
MODE6
Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
6
1
read-write
0
Px.n is in Input mode
#0
1
Px.n is in Push-pull Output mode
#1
MODE7
Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
7
1
read-write
0
Px.n is in Input mode
#0
1
Px.n is in Push-pull Output mode
#1
MODE8
Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
8
1
read-write
0
Px.n is in Input mode
#0
1
Px.n is in Push-pull Output mode
#1
MODE9
Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n
9
1
read-write
0
Px.n is in Input mode
#0
1
Px.n is in Push-pull Output mode
#1
PA_PIN
PA_PIN
PA Pin Value
0xC
read-only
n
0x0
0x0
PIN0
Port A-d Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
0
1
read-only
PIN1
Port A-d Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
1
1
read-only
PIN10
Port A-d Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
10
1
read-only
PIN11
Port A-d Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
11
1
read-only
PIN12
Port A-d Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
12
1
read-only
PIN13
Port A-d Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
13
1
read-only
PIN14
Port A-d Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
14
1
read-only
PIN15
Port A-d Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
15
1
read-only
PIN2
Port A-d Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
2
1
read-only
PIN3
Port A-d Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
3
1
read-only
PIN4
Port A-d Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
4
1
read-only
PIN5
Port A-d Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
5
1
read-only
PIN6
Port A-d Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
6
1
read-only
PIN7
Port A-d Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
7
1
read-only
PIN8
Port A-d Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
8
1
read-only
PIN9
Port A-d Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note:
9
1
read-only
PA_PUEN
PA_PUEN
PA I/O Pull-up/Down Resistor Control
0x4
read-write
n
0x0
0x0
PULLSEL0
Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
0
2
read-write
0
Px.n pull-up or pull-down resistors are all Disabled
#00
1
Px.n pull-up resistor Enabled
#01
2
Px.n pull-down resistor Enabled
#10
3
Reserved
#11
PULLSEL1
Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
2
2
read-write
0
Px.n pull-up or pull-down resistors are all Disabled
#00
1
Px.n pull-up resistor Enabled
#01
2
Px.n pull-down resistor Enabled
#10
3
Reserved
#11
PULLSEL10
Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
20
2
read-write
0
Px.n pull-up or pull-down resistors are all Disabled
#00
1
Px.n pull-up resistor Enabled
#01
2
Px.n pull-down resistor Enabled
#10
3
Reserved
#11
PULLSEL11
Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
22
2
read-write
0
Px.n pull-up or pull-down resistors are all Disabled
#00
1
Px.n pull-up resistor Enabled
#01
2
Px.n pull-down resistor Enabled
#10
3
Reserved
#11
PULLSEL12
Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
24
2
read-write
0
Px.n pull-up or pull-down resistors are all Disabled
#00
1
Px.n pull-up resistor Enabled
#01
2
Px.n pull-down resistor Enabled
#10
3
Reserved
#11
PULLSEL13
Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
26
2
read-write
0
Px.n pull-up or pull-down resistors are all Disabled
#00
1
Px.n pull-up resistor Enabled
#01
2
Px.n pull-down resistor Enabled
#10
3
Reserved
#11
PULLSEL14
Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
28
2
read-write
0
Px.n pull-up or pull-down resistors are all Disabled
#00
1
Px.n pull-up resistor Enabled
#01
2
Px.n pull-down resistor Enabled
#10
3
Reserved
#11
PULLSEL15
Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
30
2
read-write
0
Px.n pull-up or pull-down resistors are all Disabled
#00
1
Px.n pull-up resistor Enabled
#01
2
Px.n pull-down resistor Enabled
#10
3
Reserved
#11
PULLSEL2
Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
4
2
read-write
0
Px.n pull-up or pull-down resistors are all Disabled
#00
1
Px.n pull-up resistor Enabled
#01
2
Px.n pull-down resistor Enabled
#10
3
Reserved
#11
PULLSEL3
Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
6
2
read-write
0
Px.n pull-up or pull-down resistors are all Disabled
#00
1
Px.n pull-up resistor Enabled
#01
2
Px.n pull-down resistor Enabled
#10
3
Reserved
#11
PULLSEL4
Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
8
2
read-write
0
Px.n pull-up or pull-down resistors are all Disabled
#00
1
Px.n pull-up resistor Enabled
#01
2
Px.n pull-down resistor Enabled
#10
3
Reserved
#11
PULLSEL5
Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
10
2
read-write
0
Px.n pull-up or pull-down resistors are all Disabled
#00
1
Px.n pull-up resistor Enabled
#01
2
Px.n pull-down resistor Enabled
#10
3
Reserved
#11
PULLSEL6
Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
12
2
read-write
0
Px.n pull-up or pull-down resistors are all Disabled
#00
1
Px.n pull-up resistor Enabled
#01
2
Px.n pull-down resistor Enabled
#10
3
Reserved
#11
PULLSEL7
Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
14
2
read-write
0
Px.n pull-up or pull-down resistors are all Disabled
#00
1
Px.n pull-up resistor Enabled
#01
2
Px.n pull-down resistor Enabled
#10
3
Reserved
#11
PULLSEL8
Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
16
2
read-write
0
Px.n pull-up or pull-down resistors are all Disabled
#00
1
Px.n pull-up resistor Enabled
#01
2
Px.n pull-down resistor Enabled
#10
3
Reserved
#11
PULLSEL9
Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41
18
2
read-write
0
Px.n pull-up or pull-down resistors are all Disabled
#00
1
Px.n pull-up resistor Enabled
#01
2
Px.n pull-down resistor Enabled
#10
3
Reserved
#11
PB_DOUT
PB_DOUT
PB Data Output Value
0x18
read-write
n
0x0
0x0
PB_INTEN
PB_INTEN
PB Interrupt Enable Control Register
0x94
read-write
n
0x0
0x0
PB_INTSRCGP
PB_INTSRCGP
PB Interrupt Event (EINT) Source Grouping
0x84
read-write
n
0x0
0x0
PB_LATCHDAT
PB_LATCHDAT
PB Interrupt Latch Value
0xA8
read-write
n
0x0
0x0
PB_MODE
PB_MODE
PB I/O Mode Control
0x10
read-write
n
0x0
0x0
PB_PIN
PB_PIN
PB Pin Value
0x1C
read-write
n
0x0
0x0
PB_PUEN
PB_PUEN
PB I/O Pull-up/Down Resistor Control
0x14
read-write
n
0x0
0x0
PC_DOUT
PC_DOUT
PC Data Output Value
0x28
read-write
n
0x0
0x0
PC_INTEN
PC_INTEN
PC Interrupt Enable Control Register
0x98
read-write
n
0x0
0x0
PC_INTSRCGP
PC_INTSRCGP
PC Interrupt Event (EINT) Source Grouping
0x88
read-write
n
0x0
0x0
PC_LATCHDAT
PC_LATCHDAT
PC Interrupt Latch Value
0xAC
read-write
n
0x0
0x0
PC_MODE
PC_MODE
PC I/O Mode Control
0x20
read-write
n
0x0
0x0
PC_PIN
PC_PIN
PC Pin Value
0x2C
read-write
n
0x0
0x0
PC_PUEN
PC_PUEN
PC I/O Pull-up/Down Resistor Control
0x24
read-write
n
0x0
0x0
PD_DOUT
PD_DOUT
PD Data Output Value
0x38
read-write
n
0x0
0x0
PD_INTEN
PD_INTEN
PD Interrupt Enable Control Register
0x9C
read-write
n
0x0
0x0
PD_INTSRCGP
PD_INTSRCGP
PD Interrupt Event (EINT) Source Grouping
0x8C
read-write
n
0x0
0x0
PD_LATCHDAT
PD_LATCHDAT
PD Interrupt Latch Value
0xB0
read-write
n
0x0
0x0
PD_MODE
PD_MODE
PD I/O Mode Control
0x30
read-write
n
0x0
0x0
PD_PIN
PD_PIN
PD Pin Value
0x3C
read-write
n
0x0
0x0
PD_PUEN
PD_PUEN
PD I/O Pull-up/Down Resistor Control
0x34
read-write
n
0x0
0x0
I2C0
I2C Register Map
I2C
0x0
0x0
0x30
registers
n
0x3C
0x8
registers
n
I2C_ADDR0
I2C_ADDR0
I2C Slave Address Register0
0x4
read-write
n
0x0
0x0
ADDR
I2C Address Bits\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.
1
7
read-write
GC
General Call Function\n
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
I2C_ADDR1
I2C_ADDR1
I2C Slave Address Register1
0x18
read-write
n
0x0
0x0
I2C_ADDR2
I2C_ADDR2
I2C Slave Address Register2
0x1C
read-write
n
0x0
0x0
I2C_ADDR3
I2C_ADDR3
I2C Slave Address Register3
0x20
read-write
n
0x0
0x0
I2C_ADDRMSK0
I2C_ADDRMSK0
I2C Slave Address Mask Register0
0x24
read-write
n
0x0
0x0
ADDRMSK
I2C Address Mask Bits\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
1
7
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
I2C_ADDRMSK1
I2C_ADDRMSK1
I2C Slave Address Mask Register1
0x28
read-write
n
0x0
0x0
I2C_ADDRMSK2
I2C_ADDRMSK2
I2C Slave Address Mask Register2
0x2C
read-write
n
0x0
0x0
I2C_ADDRMSK3
I2C_ADDRMSK3
I2C Slave Address Mask Register3
0x30
read-write
n
0x0
0x0
I2C_CLKDIV
I2C_CLKDIV
I2C Clock Divided Register
0x10
read-write
n
0x0
0x0
DIVIDER
I2C Clock Divided Bits\n The minimum value of DIVIDER is 4.
0
8
read-write
I2C_CTL
I2C_CTL
I2C Control Register
0x0
read-write
n
0x0
0x0
AA
Assert Acknowledge Control\n
2
1
read-write
I2CEN
I2C Controller Enable Control\n
6
1
read-write
0
Disabled
#0
1
Enabled
#1
INTEN
I2C Interrupt Enable Control\n
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
SI
I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware, and if bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.
3
1
read-write
STA
I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control
In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode, setting STO resets I2C hardware to the defined not addressed Slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
4
1
read-write
I2C_DAT
I2C_DAT
I2C Data Register
0x8
read-write
n
0x0
0x0
DAT
I2C Data Bits\nBit [7:0] is located with the 8-bit transferred data of I2C serial port.
0
8
read-write
I2C_STATUS
I2C_STATUS
I2C Status Register
0xC
-1
read-only
n
0x0
0x0
STATUS
I2C Status Bits\nThe status register of I2C:\nThe three least significant bits are always 0. The five most significant bits contain the status code. Refer to section 6.11.6.4 for detail description.
0
8
read-only
I2C_TOCTL
I2C_TOCTL
I2C Time-out Control Register
0x14
read-write
n
0x0
0x0
TOCDIV4
Time-out Counter Input Clock Divided by 4\nNote When Enabled, The time-out period is extend 4 times.
1
1
read-write
0
Disabled
#0
1
Enabled
#1
TOCEN
Time-out Counter Enable Control\nNote: When Enabled, the 14-bit time-out counter will start counting when SI (I2C_CTL[3]) is cleared. Setting flag SI to high will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Disabled
#0
1
Enabled
#1
TOIF
Time-out Flag\nThis bit is set by H/W when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN (I2C_CTL[7])) is set to 1.\nWrite 1 to clear this bit.
0
1
read-write
I2C_WKCTL
I2C_WKCTL
I2C Wake-up Control Register
0x3C
read-write
n
0x0
0x0
WKEN
I2C Wake-up Enable Control\n
0
1
read-write
0
I2C wake-up function Disabled
#0
1
I2C wake-up function Enabled
#1
I2C_WKSTS
I2C_WKSTS
I2C Wake-up Status Register
0x40
read-write
n
0x0
0x0
WKIF
I2C Wake-up Flag\nNote: Software can write 1 to clear this bit.
0
1
read-write
0
No wake up occurred
#0
1
Wake up from Power-down mode
#1
I2C1
I2C Register Map
I2C
0x0
0x0
0x30
registers
n
0x3C
0x8
registers
n
I2C_ADDR0
I2C_ADDR0
I2C Slave Address Register0
0x4
read-write
n
0x0
0x0
ADDR
I2C Address Bits\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.
1
7
read-write
GC
General Call Function\n
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
I2C_ADDR1
I2C_ADDR1
I2C Slave Address Register1
0x18
read-write
n
0x0
0x0
I2C_ADDR2
I2C_ADDR2
I2C Slave Address Register2
0x1C
read-write
n
0x0
0x0
I2C_ADDR3
I2C_ADDR3
I2C Slave Address Register3
0x20
read-write
n
0x0
0x0
I2C_ADDRMSK0
I2C_ADDRMSK0
I2C Slave Address Mask Register0
0x24
read-write
n
0x0
0x0
ADDRMSK
I2C Address Mask Bits\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
1
7
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
I2C_ADDRMSK1
I2C_ADDRMSK1
I2C Slave Address Mask Register1
0x28
read-write
n
0x0
0x0
I2C_ADDRMSK2
I2C_ADDRMSK2
I2C Slave Address Mask Register2
0x2C
read-write
n
0x0
0x0
I2C_ADDRMSK3
I2C_ADDRMSK3
I2C Slave Address Mask Register3
0x30
read-write
n
0x0
0x0
I2C_CLKDIV
I2C_CLKDIV
I2C Clock Divided Register
0x10
read-write
n
0x0
0x0
DIVIDER
I2C Clock Divided Bits\n The minimum value of DIVIDER is 4.
0
8
read-write
I2C_CTL
I2C_CTL
I2C Control Register
0x0
read-write
n
0x0
0x0
AA
Assert Acknowledge Control\n
2
1
read-write
I2CEN
I2C Controller Enable Control\n
6
1
read-write
0
Disabled
#0
1
Enabled
#1
INTEN
I2C Interrupt Enable Control\n
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
SI
I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware, and if bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.
3
1
read-write
STA
I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control
In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode, setting STO resets I2C hardware to the defined not addressed Slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
4
1
read-write
I2C_DAT
I2C_DAT
I2C Data Register
0x8
read-write
n
0x0
0x0
DAT
I2C Data Bits\nBit [7:0] is located with the 8-bit transferred data of I2C serial port.
0
8
read-write
I2C_STATUS
I2C_STATUS
I2C Status Register
0xC
-1
read-only
n
0x0
0x0
STATUS
I2C Status Bits\nThe status register of I2C:\nThe three least significant bits are always 0. The five most significant bits contain the status code. Refer to section 6.11.6.4 for detail description.
0
8
read-only
I2C_TOCTL
I2C_TOCTL
I2C Time-out Control Register
0x14
read-write
n
0x0
0x0
TOCDIV4
Time-out Counter Input Clock Divided by 4\nNote When Enabled, The time-out period is extend 4 times.
1
1
read-write
0
Disabled
#0
1
Enabled
#1
TOCEN
Time-out Counter Enable Control\nNote: When Enabled, the 14-bit time-out counter will start counting when SI (I2C_CTL[3]) is cleared. Setting flag SI to high will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Disabled
#0
1
Enabled
#1
TOIF
Time-out Flag\nThis bit is set by H/W when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN (I2C_CTL[7])) is set to 1.\nWrite 1 to clear this bit.
0
1
read-write
I2C_WKCTL
I2C_WKCTL
I2C Wake-up Control Register
0x3C
read-write
n
0x0
0x0
WKEN
I2C Wake-up Enable Control\n
0
1
read-write
0
I2C wake-up function Disabled
#0
1
I2C wake-up function Enabled
#1
I2C_WKSTS
I2C_WKSTS
I2C Wake-up Status Register
0x40
read-write
n
0x0
0x0
WKIF
I2C Wake-up Flag\nNote: Software can write 1 to clear this bit.
0
1
read-write
0
No wake up occurred
#0
1
Wake up from Power-down mode
#1
I2S
I2S Register Map
I2S
0x0
0x0
0x1C
registers
n
0x20
0x2C
registers
n
CLKDIV
I2S_CLKDIV
I2S Clock Divider Control Register
0x4
read-write
n
0x0
0x0
BCLKDIV
Bit Clock Divider\nUser can program these bits to generate the frequency of BCLK, when I2S operates in master mode. In Slave mode, the frequency of BCLK is controlled by master device.\n
8
9
read-write
MCLKDIV
Master Clock Divider\nIf F_I2SCLK is (2*MCLKDIV)*256*F_LRCLK then software can program these bits to generate 256*F_LRCLK clock frequency as master clock to audio CODEC. But if MCLKDIV is set to 0, MCLK is the same as I2SCLK input.\n
0
6
read-write
CODECCTL
I2S_CODECCTL
I2S Virtual I2C Control Register
0x18
read-write
n
0x0
0x0
ADDR
Address Information\nThis parameter is used to read from the internal audio CODEC or write to the internal audio CODEC.
8
8
read-write
BUSY
Busy Flag\nIf the register 'I2S_CODECCTL' has been written, the HW would change the command to the I2C format because the internal audio CODEC interface is I2C. However, the speed of the I2C is slow. Thus, this bit is used to indicate the end of the I2C command.\n
31
1
read-write
0
I2C command is finished
#0
1
I2C command is not finished
#1
DAT
Data Information\nThis parameter is used to read from the internal audio CODEC or write to the internal audio CODEC.
0
8
read-write
DEVID
Internal Audio CODEC Device ID\nThis parameter should be set to 40H.
17
7
read-write
I2CCKDIV
SCK Clock Divider\nControl the SCK Timing Parameter.\nThe SCK frequency is (F_I2SCLK / (I2CCKDIV * 16)).\nNote: Cannot be zero.\nNote2: F_SCK must be lower than or equal to F_MCLK / 16.
24
7
read-write
RW
Read or Write Command\nControl this command to read data from the internal audio CODEC or write data to.\n
16
1
read-write
0
Read from the internal audio CODEC
#0
1
Write to the internal audio CODEC
#1
CTL
I2S_CTL
I2S Control Register
0x0
-1
read-write
n
0x0
0x0
CODECRST
Internal CODEC Hardware Reset Control\n
29
1
read-write
0
Reset Operation
#0
1
Normal Operation
#1
CODECSEL
Internal CODEC or External CODEC Selection\n
28
1
read-write
0
I2S interface connected to internal CODEC
#0
1
I2S interface connected to external CODEC
#1
FORMAT
Data Format Selection\n
7
1
read-write
0
I2S data format.\nPCM mode A
#0
1
MSB justified data format.\nPCM mode B
#1
I2SEN
I2S Controller Enable Control\n
0
1
read-write
0
Disabled
#0
1
Enabled
#1
LZCEN
Left Channel Zero-cross Detect Enable Control\nIf this bit is set to 1, when left channel data sign bit change or next shift data bits are all zero then LZCIF flag in I2S_STATUS register is set to 1.\n
17
1
read-write
0
Left channel zero-cross detect Disabled
#0
1
Left channel zero-cross detect Enabled
#1
MCLKEN
Master Clock Enable Control\nNote1: I2S_MCLK is always output.\nNote2: I2S_MCLK frequency is controlled by MCLKDIV[5:0].
25
1
read-write
0
I2S master clock output Disabled
#0
1
I2S master clock output Enabled
#1
MONO
Monaural Data\n
6
1
read-write
0
Data is stereo format
#0
1
Data is monaural format
#1
MUTE
Transmit Mute Enable Control\n
3
1
read-write
0
Transmit data is shifted from buffer
#0
1
Transmit data is fixed to zero
#1
PCMEN
PCM Interface Enable Control\n
24
1
read-write
0
I2S Interface
#0
1
PCM Interface
#1
RXCLR
Clear Receive FIFO\nNote: This bit will be cleared to 0 automatically.\nNote2: If clearing the receiver FIFO, RXCNT (I2S_STATUS[27:24]) returns to 0x0 and receiver FIFO becomes empty.
19
1
read-write
0
No effect
#0
1
Receiver FIFO will be cleared
#1
RXDMAEN
RX DMA Enable Control (Record Path)\nNote: The I2S_RXSTADDR will be updated to new setting only when RXDMAEN is from low to high. Therefore, if you want to change I2S_RXSTADDR, you should confirm RXDMAEN is disabled.
21
1
read-write
0
RX DMA mode Disabled
#0
1
RX DMA mode Enabled
#1
RXEN
Receive Enable Control\n
2
1
read-write
0
Data receiving Disabled
#0
1
Data receiving Enabled
#1
RXLCH
Receive Left Channel Enable Control\n
23
1
read-write
0
Receives right channel data when monaural format is selected
#0
1
Receives left channel data when monaural format is selected
#1
RXTH
Receive FIFO Threshold Level\nWhen received data word(s) in buffer is equal to or higher than threshold level then RXTHIF flag is set.\n
12
4
read-write
0
1 word data in receive FIFO
#0000
1
2 word data in receive FIFO
#0001
2
3 word data in receive FIFO
#0010
3
4 word data in receive FIFO
#0011
4
5 word data in receive FIFO
#0100
5
6 word data in receive FIFO
#0101
6
7 word data in receive FIFO
#0110
7
8 word data in receive FIFO
#0111
8
9 word data in receive FIFO
#1000
9
10 word data in receive FIFO
#1001
10
11 word data in receive FIFO
#1010
11
12 word data in receive FIFO
#1011
12
13 word data in receive FIFO
#1100
13
14 word data in receive FIFO
#1101
14
15 word data in receive FIFO
#1110
15
16 word data in receive FIFO
#1111
RZCEN
Right Channel Zero-cross Detection Enable Control\nIf this bit is set to 1, when right channel data sign bit change or next shift data bits are all zero then RZCIF flag in I2S_STATUS register is set to 1.\n
16
1
read-write
0
Right channel zero-cross detect Disabled
#0
1
Right channel zero-cross detect Enabled
#1
SLAVE
Slave Mode
I2S can operate as master or slave. For Master mode, I2S_BCLK and I2S_LRCLK signals are output to CODEC. In Slave mode, I2S_BCLK and I2S_LRCLK pins are received from CODEC.
Note: If using internal CODEC, the I2S must be master mode.
26
1
read-write
0
Master mode
#0
1
Slave mode
#1
TXCLR
Clear Transmit FIFO\nNote: This bit will be cleared to 0 automatically.\nNote2: If clearing the transmit FIFO, TXCNT (I2S_STATUS[31:28]) returns to 0x0 and transmit FIFO becomes empty.
18
1
read-write
0
No effect
#0
1
Transmit FIFO will be cleared
#1
TXDMAEN
TX DMA Enable Control (Transmit Path)\nNote: The I2S_TXSTADDR will be updated to new setting only when TXDMAEN is from low to high. Therefore, if you want to change I2S_TXSTADDR, you should confirm TXDMAEN is disabled.
20
1
read-write
0
TX DMA mode Disabled
#0
1
TX DMA mode Enabled
#1
TXEN
Transmit Enable Control\n
1
1
read-write
0
Data transmission Disabled
#0
1
Data transmission Enabled
#1
TXTH
Transmit FIFO Threshold Level\nIf remain data word (32 bits) in transmit FIFO is the same or less than threshold level then TXTHIF flag is set.\n
8
4
read-write
0
0 word data in transmit FIFO
#0000
1
1 word data in transmit FIFO
#0001
2
2 words data in transmit FIFO
#0010
3
3 words data in transmit FIFO
#0011
4
4 words data in transmit FIFO
#0100
5
5 words data in transmit FIFO
#0101
6
6 words data in transmit FIFO
#0110
7
7 words data in transmit FIFO
#0111
8
8 word data in transmit FIFO
#1000
9
9 word data in transmit FIFO
#1001
10
10 words data in transmit FIFO
#1010
11
11 words data in transmit FIFO
#1011
12
12 words data in transmit FIFO
#1100
13
13 words data in transmit FIFO
#1101
14
14 words data in transmit FIFO
#1110
15
15 words data in transmit FIFO
#1111
WDWIDTH
Word Width\n
4
2
read-write
0
Data is 8-bit
#00
1
Data is 16-bit
#01
2
Data is 24-bit
#10
3
Data is 32-bit
#11
IEN
I2S_IEN
I2S Interrupt Enable Register
0x8
read-write
n
0x0
0x0
LZCIEN
Left Channel Zero-cross Interrupt Enable Control\nInterrupt occurs if this bit is set to 1 and left channel zero-cross is detected.\n
12
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RDMAEIEN
RX DMA End Interrupt Enable Control\nInterrupt occurs if this bit is set to 1 and DMA current address is equal to I2S_RXEADDR register\n
4
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RDMATIEN
RX DMA Threshold Interrupt Enable Control\nInterrupt occurs if this bit is set to 1 and DMA current address is equal to I2S_RXTHADDR register\n
5
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RXOVIEN
Receive FIFO Overflow Interrupt Enable Control\n
1
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RXTHIEN
Receive FIFO Threshold Level Interrupt Enable Control\nWhen data word in receive FIFO is equal to or higher then RXTH[3:0] and the RXTHIF bit is set to 1. If RXTHIEN bit is enabled, interrupt will occur.\n
2
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RXUDIEN
Receive FIFO Underflow Interrupt Enable Control\nIf software reads receive FIFO when it is empty the RXUDIF flag in I2S_STATUS register is set to 1.\n
0
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RZCIEN
Right Channel Zero-cross Interrupt Enable Control\nInterrupt occurs if this bit is set to 1 and right channel zero-cross is detected.\n
11
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TDMAEIEN
TX DMA End Interrupt Enable Control\nInterrupt occurs if this bit is set to 1 and DMA current address is equal to I2S_TXEADDR register\n
6
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TDMATIEN
TX DMA Threshold Interrupt Enable Control\nInterrupt occurs if this bit is set to 1 and DMA current address is equal to I2S_TXTHADDR register\n
7
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TXOVIEN
Transmit FIFO Overflow Interrupt Enable Control\nInterrupt occurs if this bit is set to 1 and transmit FIFO overflow flag is set to 1.\n
9
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TXTHIEN
Transmit FIFO Threshold Level Interrupt Enable Control\nInterrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH[3:0].\n
10
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TXUDIEN
Transmit FIFO Underflow Interrupt Enable Control\nInterrupt occurs if this bit is set to 1 and transmit FIFO underflow flag is set to 1.\n
8
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
RX
I2S_RX
I2S Receive FIFO Register
0x14
read-only
n
0x0
0x0
RX
Receive FIFO Register\nI2S contains 16 words (16x32 bit) data FIFO for data receiving. Read this register to get data in FIFO. The remaining data word number is indicated by RXCNT[3:0] in I2S_STATUS register.
0
32
read-only
RXAVGCTL
I2S_RXAVGCTL
I2S RX Data Average Control Register
0x40
-1
read-write
n
0x0
0x0
WINSEL
RX Data Average Window Select\nNote: Every window size samples will generate one average result.
0
4
read-write
0
Average window is 1 (2^0) sample
#0000
1
Average window is 2 (2^1) samples
#0001
2
Average window is 4 (2^2) samples
#0010
14
Average window is 16384 (2^14) samples
#1110
15
Average window is 32768 (2^15) samples
#1111
RXCADDR
I2S_RXCADDR
I2S RX DMA Current Address Register
0x3C
read-only
n
0x0
0x0
ADDR
RX DMA Current Address Register
0
32
read-only
RXEADDR
I2S_RXEADDR
I2S RX DMA End Address Register
0x38
-1
read-write
n
0x0
0x0
ADDR
RX DMA End Address Register\nNote1: The address is word boundary.\nNote2: If WDWIDTH[1:0] is equal to 0x2 or 0x3, user must set the correct end address to avoid the swap between right channel and left channel in stereo mode.\nNote3: The address can't be set smaller than 0x2000_0000.
0
32
read-write
RXLCHAVG
I2S_RXLCHAVG
I2S RX Left Channel Data Average
0x44
read-only
n
0x0
0x0
RESULT
RX Left Channel Data Average Result\nThe average result of left channel received data.\n
0
32
read-only
RXRCHAVG
I2S_RXRCHAVG
I2S RX Right Channel Data Average
0x48
read-only
n
0x0
0x0
RESULT
RX Right Channel Data Average Result\nThe average result of left channel received data.\nNote: If MONO (I2S_CTL[6]), this register will be useless.
0
32
read-only
RXSTADDR
I2S_RXSTADDR
I2S RX DMA Start Address Register
0x30
-1
read-write
n
0x0
0x0
ADDR
RX DMA Start Address Register\nNote1: The address is word boundary.\nNote2: The address can't be set smaller than 0x2000_0000.
0
32
read-write
RXTHADDR
I2S_RXTHADDR
I2S RX DMA Threshold Address Register
0x34
-1
read-write
n
0x0
0x0
ADDR
RX DMA Threshold Address Register\nNote1: The address is word boundary.\nNote2: The address can't be set smaller than 0x2000_0000.
0
32
read-write
STATUS
I2S_STATUS
I2S Status Register
0xC
-1
read-write
n
0x0
0x0
I2SIF
I2S Interrupt Flag\nNote1: This flag is triggered if any of TXIF and RXIF bits are enabled.\nNote2: This bit is read only.
0
1
read-write
0
No I2S interrupt
#0
1
I2S interrupt
#1
LZCIF
Left Channel Zero-cross Flag\nIt indicates left channel next sample data sign bit is changed or all data bits are zero.\nNote: Write 1 to clear this bit to 0.
23
1
read-write
0
No zero-cross
#0
1
Left channel zero-cross is detected
#1
RDMAEIF
RX DMA Equal End Address Interrupt Flag\nIf RX DMA current address is equal to I2S_RXEADDR register, this interrupt flag will be set. If the RDMAEIEN is set, an interrupt to NVIC will occur.\nNote: Write 1 to clear this bit to zero
4
1
read-write
0
No RX End Interrupt
#0
1
RX End Interrupt
#1
RDMATIF
RX DMA Equal Threshold Address Interrupt Flag\nIf RX DMA current address is equal to I2S_RXTHADDR register, this interrupt flag will be set. If the RDMATIEN is set, an interrupt to NVIC will occur.\nNote: Write 1 to clear this bit to zero
5
1
read-write
0
No RX Threshold Interrupt
#0
1
RX Threshold Interrupt
#1
RIGHT
Right Channel\nIndicates that the current transmit data belongs to right channel\nNote: This bit is read only,
3
1
read-write
0
Left channel
#0
1
Right channel
#1
RXCNT
Receive FIFO Level\nThese bits indicate word number in receive FIFO\n
24
4
read-write
0
No data or 16 words (need to check the RX full flag)
#0000
1
1 word in receive FIFO
#0001
15
15 words in receive FIFO
#1111
RXEMPTY
Receive FIFO Empty\nThis bit reflects data words number in receive FIFO is zero\nNote: This bit is read only.
12
1
read-write
0
FIFO not empty
#0
1
FIFO empty
#1
RXFULL
Receive FIFO Full\nThis bit reflect data words number in receive FIFO is 16\nNote: This bit is read only.
11
1
read-write
0
FIFO not full
#0
1
FIFO full
#1
RXIF
I2S Receive Interrupt\nNote1: This flag is triggered if any of RXTHIF, RXOVIF, RXUDIF, RDMATIF, and RDMAEIF occurs.\nNote2: This bit is read only.
1
1
read-write
0
No receive interrupt
#0
1
Receive interrupt
#1
RXOVIF
Receive FIFO Overflow Flag\nWhen receive FIFO is full and receive hardware attempt write to data into receive FIFO this bit is set to 1, and data in 1st buffer is overwritten.\nNote: Write 1 to clear this bit to 0.
9
1
read-write
0
No overflow occurred
#0
1
Overflow occurred
#1
RXTHIF
Receive FIFO Threshold Flag\nWhen data word(s) in receive FIFO is equal to or higher than the threshold value set in RXTH[3:0] the RXTHIF bit becomes to 1. It keeps at 1 till RXCNT[3:0] is less than RXTH[3:0] after software reads the I2S_RX register.\nNote: This bit is read only.
10
1
read-write
0
Data word(s) in FIFO is lower than threshold level
#0
1
Data word(s) in FIFO is equal or higher than threshold level
#1
RXUDIF
Receive FIFO Underflow Flag\nRead receive FIFO when it is empty. Setting this bit to 1 indicates underflow occurred.\nNote: Write 1 to clear this bit to zero
8
1
read-write
0
No underflow occurred
#0
1
Underflow occurred
#1
RZCIF
Right Channel Zero-cross Flag\nIt indicates right channel next sample data sign bit is changed or all data bits are zero.\nNote: Write 1 to clear this bit to 0.
22
1
read-write
0
No zero-cross
#0
1
Right channel zero-cross is detected
#1
TDMAEIF
TX DMA Equal End Address Interrupt Flag\nIf TX DMA current address is equal to I2S_TXEADDR register, this interrupt flag will be set. If the TDMAEIEN is set, an interrupt to NVIC will occur.\nNote: Write 1 to clear this bit to zero
6
1
read-write
0
No TX End Interrupt
#0
1
TX End Interrupt
#1
TDMATIF
TX DMA Equal Threshold Address Interrupt Flag\nIf TX DMA current address is equal to I2S_TXTHADDR register, this interrupt flag will be set. If the TDMATIEN is set, an interrupt to NVIC will occur.\nNote: Write 1 to clear this bit to zero
7
1
read-write
0
No TX Threshold Interrupt
#0
1
TX Threshold Interrupt
#1
TXBUSY
Transmit Busy\nThis bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out. This bit is set to 1 when the first data is loaded to shift buffer. \nNote: This bit is read only.
21
1
read-write
0
Transmit shift buffer is empty
#0
1
Transmit shift buffer is busy
#1
TXCNT
Transmit FIFO Level\nThese bits indicate word number in transmit FIFO\n
28
4
read-write
0
No data or 16 words ( need to check the TX full flag)
#0000
1
1 word in transmit FIFO
#0001
15
15 words in transmit FIFO
#1111
TXEMPTY
Transmit FIFO Empty\nThis bit reflect data word number in transmit FIFO is zero\nNote: This bit is read only.
20
1
read-write
0
Not empty
#0
1
Empty
#1
TXFULL
Transmit FIFO Full\nThis bit reflect data word number in transmit FIFO is 16\nNote: This bit is read only.
19
1
read-write
0
Not full
#0
1
Full
#1
TXIF
I2S Transmit Interrupt\nNote1: This flag is triggered if any of LZCIF, RZCIF, TXTHIF, TXOIF, TXUDIF, TDMATIF, and TDMAEIF occurs.\nNote2: This bit is read only.
2
1
read-write
0
No transmit interrupt
#0
1
Transmit interrupt
#1
TXOVIF
Transmit FIFO Overflow Flag\nWrite data to transmit FIFO when it is full and this bit set to 1\nNote: Write 1 to clear this bit to 0.
17
1
read-write
0
No overflow
#0
1
Overflow
#1
TXTHIF
Transmit FIFO Threshold Flag\nWhen data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH[3:0] the TXTHIF bit becomes to 1. It keeps at 1 till TXCNT[3:0] is higher than TXTH[3:0] after software write I2S_TX register.\nNote: This bit is read only.
18
1
read-write
0
Data word(s) in FIFO is higher than threshold level
#0
1
Data word(s) in FIFO is equal or lower than threshold level
#1
TXUDIF
Transmit FIFO Underflow Flag\nWhen transmit FIFO is empty and shift logic hardware read data from data FIFO causes this set to 1.\nNote: Write 1 to clear this bit to 0.
16
1
read-write
0
No underflow
#0
1
Underflow
#1
TX
I2S_TX
I2S Transmit FIFO Register
0x10
write-only
n
0x0
0x0
TX
Transmit FIFO Register\nI2S contains 16 words (16x32 bit) data FIFO for data transmssion. Write data to this register to prepare data for transmission. The remaining word number is indicated by TXCNT[3:0] in I2S_STATUS.
0
32
write-only
TXCADDR
I2S_TXCADDR
I2S TX DMA Current Address Register
0x2C
read-only
n
0x0
0x0
ADDR
TX DMA Current Address Register
0
32
read-only
TXEADDR
I2S_TXEADDR
I2S TX DMA End Address Register
0x28
-1
read-write
n
0x0
0x0
ADDR
TX DMA End Address Register\nNote1: The address is word boundary.\nNote2: If WDWIDTH[1:0] is equal to 0x2 or 0x3, user must set the correct end address to avoid the swap between right channel and left channel in stereo mode.\nNote2: The address can't be set smaller than 0x2000_0000.
0
32
read-write
TXSTADDR
I2S_TXSTADDR
I2S TX DMA Start Address Register
0x20
-1
read-write
n
0x0
0x0
ADDR
TX DMA Start Address Register\nNote1: The address is word boundary.\nNote2: The address can't be set smaller than 0x2000_0000.
0
32
read-write
TXTHADDR
I2S_TXTHADDR
I2S TX DMA Threshold Address Register
0x24
-1
read-write
n
0x0
0x0
ADDR
TX DMA Threshold Address Register\nNote1: The address is word boundary.\nNote2: The address can't be set smaller than 0x2000_0000.
0
32
read-write
NVIC_IPR0
SCS Register Map
SCS
0x0
0x0
0x4
registers
n
NVIC_IPRN
NVIC_IPRN
IRQ0 ~ IRQ31 Interrupt Priority Control Register
0x0
read-write
n
0x0
0x0
PRI_4n_0
Priority of IRQ_4n+0
0 denotes the highest priority and 15 denotes the lowest priority
4
4
read-write
PRI_4n_1
Priority of IRQ_4n+1
0 denotes the highest priority and 15 denotes the lowest priority
12
4
read-write
PRI_4n_2
Priority of IRQ_4n+2
0 denotes the highest priority and 15 denotes the lowest priority
20
4
read-write
PRI_4n_3
Priority of IRQ_4n+3
0 denotes the highest priority and 15 denotes the lowest priority
28
4
read-write
NVIC_IPR1
SCS Register Map
SCS
0x0
0x0
0x4
registers
n
NVIC_IPRN
NVIC_IPRN
IRQ0 ~ IRQ31 Interrupt Priority Control Register
0x0
read-write
n
0x0
0x0
PRI_4n_0
Priority of IRQ_4n+0
0 denotes the highest priority and 15 denotes the lowest priority
4
4
read-write
PRI_4n_1
Priority of IRQ_4n+1
0 denotes the highest priority and 15 denotes the lowest priority
12
4
read-write
PRI_4n_2
Priority of IRQ_4n+2
0 denotes the highest priority and 15 denotes the lowest priority
20
4
read-write
PRI_4n_3
Priority of IRQ_4n+3
0 denotes the highest priority and 15 denotes the lowest priority
28
4
read-write
NVIC_IPR2
SCS Register Map
SCS
0x0
0x0
0x4
registers
n
NVIC_IPRN
NVIC_IPRN
IRQ0 ~ IRQ31 Interrupt Priority Control Register
0x0
read-write
n
0x0
0x0
PRI_4n_0
Priority of IRQ_4n+0
0 denotes the highest priority and 15 denotes the lowest priority
4
4
read-write
PRI_4n_1
Priority of IRQ_4n+1
0 denotes the highest priority and 15 denotes the lowest priority
12
4
read-write
PRI_4n_2
Priority of IRQ_4n+2
0 denotes the highest priority and 15 denotes the lowest priority
20
4
read-write
PRI_4n_3
Priority of IRQ_4n+3
0 denotes the highest priority and 15 denotes the lowest priority
28
4
read-write
NVIC_IPR3
SCS Register Map
SCS
0x0
0x0
0x4
registers
n
NVIC_IPRN
NVIC_IPRN
IRQ0 ~ IRQ31 Interrupt Priority Control Register
0x0
read-write
n
0x0
0x0
PRI_4n_0
Priority of IRQ_4n+0
0 denotes the highest priority and 15 denotes the lowest priority
4
4
read-write
PRI_4n_1
Priority of IRQ_4n+1
0 denotes the highest priority and 15 denotes the lowest priority
12
4
read-write
PRI_4n_2
Priority of IRQ_4n+2
0 denotes the highest priority and 15 denotes the lowest priority
20
4
read-write
PRI_4n_3
Priority of IRQ_4n+3
0 denotes the highest priority and 15 denotes the lowest priority
28
4
read-write
NVIC_IPR4
SCS Register Map
SCS
0x0
0x0
0x4
registers
n
NVIC_IPRN
NVIC_IPRN
IRQ0 ~ IRQ31 Interrupt Priority Control Register
0x0
read-write
n
0x0
0x0
PRI_4n_0
Priority of IRQ_4n+0
0 denotes the highest priority and 15 denotes the lowest priority
4
4
read-write
PRI_4n_1
Priority of IRQ_4n+1
0 denotes the highest priority and 15 denotes the lowest priority
12
4
read-write
PRI_4n_2
Priority of IRQ_4n+2
0 denotes the highest priority and 15 denotes the lowest priority
20
4
read-write
PRI_4n_3
Priority of IRQ_4n+3
0 denotes the highest priority and 15 denotes the lowest priority
28
4
read-write
NVIC_IPR5
SCS Register Map
SCS
0x0
0x0
0x4
registers
n
NVIC_IPRN
NVIC_IPRN
IRQ0 ~ IRQ31 Interrupt Priority Control Register
0x0
read-write
n
0x0
0x0
PRI_4n_0
Priority of IRQ_4n+0
0 denotes the highest priority and 15 denotes the lowest priority
4
4
read-write
PRI_4n_1
Priority of IRQ_4n+1
0 denotes the highest priority and 15 denotes the lowest priority
12
4
read-write
PRI_4n_2
Priority of IRQ_4n+2
0 denotes the highest priority and 15 denotes the lowest priority
20
4
read-write
PRI_4n_3
Priority of IRQ_4n+3
0 denotes the highest priority and 15 denotes the lowest priority
28
4
read-write
NVIC_IPR6
SCS Register Map
SCS
0x0
0x0
0x4
registers
n
NVIC_IPRN
NVIC_IPRN
IRQ0 ~ IRQ31 Interrupt Priority Control Register
0x0
read-write
n
0x0
0x0
PRI_4n_0
Priority of IRQ_4n+0
0 denotes the highest priority and 15 denotes the lowest priority
4
4
read-write
PRI_4n_1
Priority of IRQ_4n+1
0 denotes the highest priority and 15 denotes the lowest priority
12
4
read-write
PRI_4n_2
Priority of IRQ_4n+2
0 denotes the highest priority and 15 denotes the lowest priority
20
4
read-write
PRI_4n_3
Priority of IRQ_4n+3
0 denotes the highest priority and 15 denotes the lowest priority
28
4
read-write
NVIC_IPR7
SCS Register Map
SCS
0x0
0x0
0x4
registers
n
NVIC_IPRN
NVIC_IPRN
IRQ0 ~ IRQ31 Interrupt Priority Control Register
0x0
read-write
n
0x0
0x0
PRI_4n_0
Priority of IRQ_4n+0
0 denotes the highest priority and 15 denotes the lowest priority
4
4
read-write
PRI_4n_1
Priority of IRQ_4n+1
0 denotes the highest priority and 15 denotes the lowest priority
12
4
read-write
PRI_4n_2
Priority of IRQ_4n+2
0 denotes the highest priority and 15 denotes the lowest priority
20
4
read-write
PRI_4n_3
Priority of IRQ_4n+3
0 denotes the highest priority and 15 denotes the lowest priority
28
4
read-write
PWM
PWM Register Map
PWM
0x0
0x0
0x3C
registers
n
0x40
0x8
registers
n
0x50
0x30
registers
n
CAPCTL01
PWM_CAPCTL01
Capture Control Register 0
0x50
read-write
n
0x0
0x0
CAPEN0
Capture Channel 0 Function Enable Control\nNote1: When Enabled, Capture latched the PWM-counter value and saved to PWM_RCAPDAT0 (Rising latch) and PWM_FCAPDAT0 (Falling latch).\nNote2: When Disabled, Capture does not update PWM_RCAPDAT0 and PWM_FCAPDAT0, and disable Channel 0 Interrupt.
3
1
read-write
0
Capture function Disabled
#0
1
Capture function Enabled
#1
CAPEN1
Capture Channel 1 Function Enable Control\nNote1: When Enabled, Capture latched the PMW-counter 1 and saved to PWM_RCAPDAT1 (Rising latch) and PWM_FCAPDAT1 (Falling latch).\nNote2: When Disabled, Capture does not update PWM_RCAPDAT1 and PWM_FCAPDAT1, and disable Channel 1 Interrupt.
19
1
read-write
0
Capture function Disabled
#0
1
Capture function Enabled
#1
CAPIF0
Capture 0 Interrupt Indication
Note: If this bit is 1 , PWM-counter 0 will not reload when the next capture interrupt occur. Write 1 clear.
4
1
read-write
0
Interrupt Flag OFF
#0
1
Interrupt Flag ON
#1
CAPIF1
Capture 1 Interrupt Indication
Note: If this bit is 1 , PWM-counter 1 will not reload when the next capture interrupt occurs. Write 1 to clear.
20
1
read-write
0
Interrupt Flag OFF
#0
1
Interrupt Flag ON
#1
CAPINV0
Capture 0 Inverter Enable Control\n
0
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV1
Capture 1 Inverter Enable Control\n
16
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled
#1
CFLIEN0
Channel 0 Falling Interrupt Enable Control\nNote: When Enabled, if Capture detects Channel 0 has falling transition, Capture issues an Interrupt.
2
1
read-write
0
Channel 0 Falling Interrupt Disabled
#0
1
Channel 0 Falling Interrupt Enabled
#1
CFLIEN1
Channel1 Falling Interrupt Enable Control\nNote: When Enabled, if Capture detects Channel 1 has falling transition, Capture issues an Interrupt.
18
1
read-write
0
Channel1 Falling Interrupt Disabled
#0
1
Channel1 Falling Interrupt Enabled
#1
CFLIF0
Capture Falling Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it.
7
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, and this flag will be set to high
#1
CFLIF1
Capture Falling Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it.
23
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, and this flag will be set to high
#1
CRLIEN0
Channel 0 Rising Interrupt Enable Control\nNote: When Enabled, if Capture detects Channel 0 has rising transition, Capture issues an Interrupt.
1
1
read-write
0
Channel 0 Rising Interrupt Enable Disabled
#0
1
Channel 0 Rising Interrupt Enable Enabled
#1
CRLIEN1
Channel 1 Rising Interrupt Enable Control\nNote: When Enabled, if Capture detects Channel 1 has rising transition, Capture issues an Interrupt.
17
1
read-write
0
Channel 1 Rising Interrupt Disabled
#0
1
Channel 1 Rising Interrupt Enabled
#1
CRLIF0
Capture Rising Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it.
6
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, and this flag will be set to high
#1
CRLIF1
Capture Rising Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it.
22
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, and this flag will be set to high
#1
CAPCTL23
PWM_CAPCTL23
Capture Control Register 1
0x54
read-write
n
0x0
0x0
CAPEN2
Capture Channel 2 Function Enable Control\nNote: When Enabled, Capture latched the PMW-counter value and saved to PWM_RCAPDAT2 (Rising latch) and PWM_FCAPDAT2 (Falling latch). When Disabled, Capture does not update PWM_RCAPDAT2 and PWM_FCAPDAT2, and disable Channel 2 Interrupt.
3
1
read-write
0
Capture function Disabled
#0
1
Capture function Enabled
#1
CAPEN3
Capture Channel 3 Function Enable Control\nNote: When Enabled, Capture latched the PMW-counter and saved to PWM_RCAPDAT3 (Rising latch) and PWM_FCAPDAT3 (Falling latch). When Disabled, Capture does not update PWM_RCAPDAT3 and PWM_FCAPDAT3, and disable Channel 3 Interrupt.
19
1
read-write
0
Capture function Disabled
#0
1
Capture function Enabled
#1
CAPIF2
Capture 2 Interrupt Indication
Note: If this bit is 1 , PWM-counter 2 will not reload when next capture interrupt occur.
4
1
read-write
0
Interrupt Flag OFF
#0
1
Interrupt Flag ON
#1
CAPIF3
Capture 3 Interrupt Indication
Note: If this bit is 1 , PWM-counter 3 will not reload when next capture interrupt occur.
20
1
read-write
0
Interrupt Flag OFF
#0
1
Interrupt Flag ON
#1
CAPINV2
Capture 2 Inverter Enable Control\n
0
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV3
Capture 3 Inverter Enable Control\n
16
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CFLIEN2
Channel 2 Falling Interrupt Enable Control\nNote: When Enabled, if Capture detects Channel 2 has falling transition, Capture issues an Interrupt.
2
1
read-write
0
Channel 2 Falling Interrupt Disabled
#0
1
Channel 2 Falling Interrupt Enabled
#1
CFLIEN3
Channel 3 Falling Interrupt Enable Control\nNote: When Enabled, if Capture detects Channel 3 has falling transition, Capture issues an Interrupt.
18
1
read-write
0
Channel 3 Falling Interrupt Disabled
#0
1
Channel 3 Falling Interrupt Enabled
#1
CFLIF2
Capture Falling Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it.
7
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CFLIF3
Capture Falling Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it.
23
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CRLIEN2
Channel 2 Rising Interrupt Enable Control\nNote: When Enabled, if Capture detects Channel 2 has rising transition, Capture issues an Interrupt.
1
1
read-write
0
Channel 2 Rising Interrupt Disabled
#0
1
Channel 2 Rising Interrupt Enabled
#1
CRLIEN3
Channel 3 Rising Interrupt Enable Control\nNote: When Enabled, if Capture detects Channel 3 has rising transition, Capture issues an Interrupt.
17
1
read-write
0
Channel 3 Rising Interrupt Disabled
#0
1
Channel 3 Rising Interrupt Enabled
#1
CRLIF2
Capture Rising Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it.
6
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CRLIF3
Capture Rising Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it.
22
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPINEN
PWM_CAPINEN
Capture Input Enable Register
0x78
read-write
n
0x0
0x0
CAPINEN
Capture Input Enable Control\n
0
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
CLKDIV
PWM_CLKDIV
PWM Clock Select Register
0x4
read-write
n
0x0
0x0
CLKDIV0
PWM Counter 0 Clock Source Selection\nSelect clock input for PWM Counter 0.\n(Table is the same as CLKDIV3)
0
3
read-write
CLKDIV1
PWM Counter 1 Clock Source Selection\nSelect clock input for PWM Counter 1.\n(Table is the same as CLKDIV3)
4
3
read-write
CLKDIV2
PWM Counter 2 Clock Source Selection\nSelect clock input for PWM Counter 2.\n(Table is the same as CLKDIV3)
8
3
read-write
CLKDIV3
PWM Counter 3 Clock Source Selection\nSelect clock input for timer 3.\n
12
3
read-write
0
PWM_CLK/2
#000
1
PWM_CLK/4
#001
2
PWM_CLK/8
#010
3
PWM_CLK/16
#011
4
PWM_CLK/1
#100
CLKPSC
PWM_CLKPSC
PWM Pre-scale Register
0x0
read-write
n
0x0
0x0
CLKPSC01
Clock Pre-scale 0 for PWM Counter 0 1
Clock input is divided by (CLKPSC01+1) before it is fed to the counter 0 1.
0
8
read-write
CLKPSC23
Clock Pre-scale 1 for PWM Counter 2 3
Clock input is divided by (CLKPSC23+1) before it is fed to the counter 2 3.
8
8
read-write
DZCNT01
Dead-time Interval Register 0\nThese 8-bit determine Dead-time length.\n
16
8
read-write
DZCNT23
Dead-time Interval Register 1\nThese 8-bit determine Dead-time length.\n
24
8
read-write
CMPDAT0
PWM_CMPDAT0
PWM Comparator Register 0
0x10
read-write
n
0x0
0x0
CMP
PWM Compare Register\nCMP determines the PWM output duty ratio.\nNote: Any write to CMP will take effect in the next PWM cycle.
0
16
read-write
CMPDAT1
PWM_CMPDAT1
PWM Comparator Register 1
0x1C
read-write
n
0x0
0x0
CMPDAT2
PWM_CMPDAT2
PWM Comparator Register 2
0x28
read-write
n
0x0
0x0
CMPDAT3
PWM_CMPDAT3
PWM Comparator Register 3
0x34
read-write
n
0x0
0x0
CNT0
PWM_CNT0
PWM Data Register 0
0x14
read-only
n
0x0
0x0
CNT
PWM Data Register\nUser can monitor CNT to know current value in 16-bit down counter.
0
16
read-only
CNT1
PWM_CNT1
PWM Data Register 1
0x20
read-write
n
0x0
0x0
CNT2
PWM_CNT2
PWM Data Register 2
0x2C
read-write
n
0x0
0x0
CNT3
PWM_CNT3
PWM Data Register 3
0x38
read-write
n
0x0
0x0
CTL
PWM_CTL
PWM Control Register
0x8
read-write
n
0x0
0x0
CNTEN0
PWM Counter 0 Enable Control\n
0
1
read-write
0
PWM Counter and clock prescaler stops running
#0
1
PWM Counter and clock prescaler starts running
#1
CNTEN1
PWM Counter 1 Enable Control\n
8
1
read-write
0
PWM Counter and clock prescaler stops running
#0
1
PWM Counter and clock prescaler starts running
#1
CNTEN2
PWM Counter 2 Enable Control\n
16
1
read-write
0
PWM Counter and clock prescaler stops running
#0
1
PWM Counter and clock prescaler starts running
#1
CNTEN3
PWM Counter 3 Enable Control\n
24
1
read-write
0
PWM Counter and clock prescaler stops running
#0
1
PWM Counter and clock prescaler starts running
#1
CNTMODE0
PWM Counter 0 Auto-reload Mode/One-shot Mode\n If there is a rising transition at this bit, it will cause PWM_PERIOD0 and PWM_CMPDAT0 be cleared.
3
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CNTMODE1
PWM Counter 1 Auto-reload Mode/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause PWM_PERIOD1 and PWM_CMPDAT1 be cleared.
11
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CNTMODE2
PWM Counter 2 Auto-reload Mode/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause PWM_PERIOD2 and PWM_CMPDAT2 be cleared.
19
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CNTMODE3
PWM Counter 3 Auto-reload Mode/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause PWM_PERIOD3 and PWM_CMPDAT3 be cleared.
27
1
read-write
0
One-Shot mode
#0
1
Auto-Reload mode
#1
DTEN01
Dead-time 0 Generator Enable Control\n
4
1
read-write
0
Dead-time generator stops running
#0
1
Dead-time generator starts running
#1
DTEN23
Dead-time 1 Generator Enable Control\n
5
1
read-write
0
Dead-time generator stops running
#0
1
Dead-time generator starts running
#1
PINV0
PWM Counter 0 Inverter ON/OFF\n
2
1
read-write
0
Inverter OFF
#0
1
Inverter ON
#1
PINV1
PWM Counter 1 Inverter ON/OFF\n
10
1
read-write
0
Inverter OFF
#0
1
Inverter ON
#1
PINV2
PWM Counter 2 Inverter ON/OFF\n
18
1
read-write
0
Inverter OFF
#0
1
Inverter ON
#1
PINV3
PWM Counter 3 Inverter ON/OFF\n
26
1
read-write
0
Inverter OFF
#0
1
Inverter ON
#1
FCAPDAT0
PWM_FCAPDAT0
Capture Falling Latch Register (Channel 0)
0x5C
read-write
n
0x0
0x0
FCAPDAT
Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition.
0
16
read-write
FCAPDAT1
PWM_FCAPDAT1
Capture Falling Latch Register (Channel 1)
0x64
read-write
n
0x0
0x0
FCAPDAT2
PWM_FCAPDAT2
Capture Falling Latch Register (Channel 2)
0x6C
read-write
n
0x0
0x0
FCAPDAT3
PWM_FCAPDAT3
Capture Falling Latch Register (Channel 3)
0x74
read-write
n
0x0
0x0
INTEN
PWM_INTEN
PWM Interrupt Enable Register
0x40
read-write
n
0x0
0x0
PIEN
PWM Period Interrupt Enable Control\nNote: Each bit controls the corresponding PWM channel.
0
4
read-write
0
Period interrupt Disabled
0
1
Period interrupt Enabled
1
INTSTS
PWM_INTSTS
PWM Interrupt Indication Register
0x44
read-write
n
0x0
0x0
PIF
PWM Timer Interrupt Flag\nNote1: Each bit controls the corresponding PWM channel.\nNote2: User can clear each interrupt flag by writing a one to corresponding bit
0
4
read-write
0
Interrupt Flag OFF
0
1
Interrupt Flag ON
1
PERIOD0
PWM_PERIOD0
PWM Period Register 0
0xC
read-write
n
0x0
0x0
PERIOD
PWM Period Register\nPERIOD determines the PWM period.\nNote: Any write to PERIOD will take effect in the next PWM cycle.
0
16
read-write
PERIOD1
PWM_PERIOD1
PWM Period Register 1
0x18
read-write
n
0x0
0x0
PERIOD2
PWM_PERIOD2
PWM Period Register 2
0x24
read-write
n
0x0
0x0
PERIOD3
PWM_PERIOD3
PWM Period Register 3
0x30
read-write
n
0x0
0x0
POEN
PWM_POEN
PWM Output Enable Register
0x7C
read-write
n
0x0
0x0
POEN
PWM Counter Output Enable Control\nNote: Each bit controls the corresponding PWM channel.
0
4
read-write
0
PWM Counter Output Disabled
0
1
PWM Counter Output Enabled
1
RCAPDAT0
PWM_RCAPDAT0
Capture Rising Latch Register (Channel 0)
0x58
read-write
n
0x0
0x0
RCAPDAT
Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition.
0
16
read-write
RCAPDAT1
PWM_RCAPDAT1
Capture Rising Latch Register (Channel 1)
0x60
read-write
n
0x0
0x0
RCAPDAT2
PWM_RCAPDAT2
Capture Rising Latch Register (Channel 2)
0x68
read-write
n
0x0
0x0
RCAPDAT3
PWM_RCAPDAT3
Capture Rising Latch Register (Channel 3)
0x70
read-write
n
0x0
0x0
RTC
RTC Register Map
RTC
0x0
0x0
0x48
registers
n
0x54
0x20
registers
n
CAL
RTC_CAL
RTC Calendar Loading Register
0x10
-1
read-write
n
0x0
0x0
DAY
1-Day Calendar Digit
0
4
read-write
MON
1-Month Calendar Digit
8
4
read-write
TENDAY
10-Day Calendar Digit
4
2
read-write
TENMON
10-Month Calendar Digit
12
1
read-write
TENYEAR
10-Year Calendar Digit
20
4
read-write
YEAR
1-Year Calendar Digit
16
4
read-write
CALCNT
RTC_CALCNT
RC Oscillator Calibration Register
0x40
read-only
n
0x0
0x0
CALCNT
Cycle Number of PCLK During 1Hz\nThat is generated by dividing RTC Clock. This number can be used to deduct the real clock rate of RTC clock.
0
32
read-only
CALM
RTC_CALM
RTC Calendar Alarm Register
0x20
read-write
n
0x0
0x0
DAY
1-Day Calendar Digit of Alarm Setting (0-9)
0
4
read-write
MON
1-Month Calendar Digit of Alarm Setting (0-9)
8
4
read-write
MSKDAY
Mask Alarm by Day\n
7
1
read-write
0
Activate
#0
1
Mask
#1
MSKMON
Mask Alarm by Month\n
15
1
read-write
0
Activate
#0
1
Mask
#1
MSKWEEKDAY
Mask Alarm by Week Day\n
31
1
read-write
0
Activate
#0
1
Mask
#1
MSKYEAR
Mask Alarm by Year\n
24
1
read-write
0
Activate
#0
1
Mask
#1
TENDAY
10-Day Calendar Digit of Alarm Setting (0-3)
4
2
read-write
TENMON
10-Month Calendar Digit of Alarm Setting (0-1)
12
1
read-write
TENYEAR
10-Year Calendar Digit of Alarm Setting (0-9)
20
4
read-write
WEEKDAY
Week Day Alarm Digit
28
3
read-write
YEAR
1-Year Calendar Digit of Alarm Setting (0-9)
16
4
read-write
CLKFMT
RTC_CLKFMT
RTC Time Scale Selection Register
0x14
-1
read-write
n
0x0
0x0
_24HEN
24-hour / 12-hour Mode Selection\nIndicate that RTC_TIME and RTC_TALM are in 24-hour mode or 12-hour mode.\n
0
1
read-write
0
12-hour time scale with AM and PM indication selected
#0
1
24-hour time scale selected
#1
CLKSRC
RTC_CLKSRC
RC Oscillator Setting Register
0x3C
-1
read-write
n
0x0
0x0
CKSRC
Internal RC Oscillator Control\n
0
1
read-write
0
Internal RC oscillator Disabled
#0
1
Internal RC oscillator Enabled
#1
FREQADJ
RTC_FREQADJ
RTC Frequency Compensation Register
0x8
-1
read-write
n
0x0
0x0
ADJTRG
RTC Clock Calibration Control
This bit will be kept at High while the calibration is ongoing and cleared to Low automatically while the calibration is done and the content of RTC_CALCNT register is valid calibration flow as follows.
31
1
read-write
0
RTC Clock calibration mechanism Disabled
#0
1
RTC Clock calibration mechanism Enabled
#1
FRACTION
Fraction Part\nDigit in RTC_FREQADJ must be expressed as hexadecimal number.
0
6
read-write
INTEGER
Integer Part\n
8
16
read-write
PKEYTIME
Minimum Duration That Power Key Must Be Pressed to Turn on Core Power\n
24
4
read-write
INIT
RTC_INIT
RTC Initiation Register
0x0
read-write
n
0x0
0x0
ACTIVE
RTC Active Status (Read Only)\n
0
1
read-only
0
RTC is at reset state
#0
1
RTC is at normal active state
#1
INIT_STS
RTC Initiation (While Writing)
When RTC block is powered on, RTC is at reset state. User has to write a number (0x a5eb1357) to INIT to make RTC exit from reset state. Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
The INIT is a write-only field and read value will be always 0 .
RTC Internal Status (While Reading)
[31:8]: INIT[31:8]
[7:5]: RTC internal state machine of key detection
[4]: Status of power key, 0:pressed and 1:released
[3]: Status of power off request pwr_key_off
[2]: Level shifter reset
[1]: Level shifter enable
1
31
read-write
INTEN
RTC_INTEN
RTC Interrupt Enable Register
0x28
read-write
n
0x0
0x0
ALMIEN
Alarm Interrupt Enable Control\n
0
1
read-write
0
RTC Alarm Interrupt Disabled
#0
1
RTC Alarm Interrupt Enabled
#1
PKEYIEN
Power Switch Interrupt Enable Control\n
2
1
read-write
0
Power Switch Be Pressed Interrupt Disabled
#0
1
Power Switch Be Pressed Interrupt Enabled
#1
RALMIEN
Relative Alarm Interrupt Enable Control\n
3
1
read-write
0
RTC Relative Alarm Interrupt Disabled
#0
1
RTC Relative Alarm Interrupt Enabled
#1
TICKIEN
Time Tick Interrupt Enable Control\n
1
1
read-write
0
RTC Time Tick Interrupt and counter Disabled
#0
1
RTC Time Tick Interrupt and counter Enabled
#1
INTSTS
RTC_INTSTS
RTC Interrupt Indication Register
0x2C
read-write
n
0x0
0x0
ALMIF
RTC Alarm Interrupt Flag\nWhen RTC time counters RTC_TIME and RTC_CAL match the alarm setting time registers RTC_TALM and RTC_CALM, this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled ALMIEN (RTC_INTEN[0]) is set to 1. Chip will be woken up if RTC Alarm Interrupt is enabled when chip is at Power-down mode.\nNote: Write 1 to clear this bit.
0
1
read-write
0
Alarm condition is not matched
#0
1
Alarm condition is matched
#1
POWKEYIF
Power Switch Interrupt Flag\nWhen RTC detect power key (RTC_nRWAKE) is pressed , the POWKEYIF (RTC_INTSYS[2]) is set to 1\nNote: Software can also clear this bit after RTC interrupt has occurred
2
1
read-write
0
The power switch interrupt never occurred
#0
1
The power switch has been activated
#1
RELALMIF
RTC Relative Alarm Interrupt Indication\nNote: Software can also clear this bit after RTC interrupt has occurred
3
1
read-write
0
Relative alarm interrupt never occurred
#0
1
Relative time counter and calendar counter have counted to a specified time recorded in RTC_TALM and RTC_CALM. RTC alarm interrupt has been activated
#1
TICKIF
RTC Time Tick Interrupt Flag\nWhen RTC time tick happened, this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled TICKIEN (RTC_INTEN[1]) is set to 1. Chip will also be woken up if RTC Tick Interrupt is enabled and this bit is set to 1 when chip is running at Power-down mode.\nNote: Write 1 to clear to clear this bit.
1
1
read-write
0
Tick condition does not occur
#0
1
Tick condition occur
#1
LEAPYEAR
RTC_LEAPYEAR
RTC Leap Year Indication Register
0x24
read-only
n
0x0
0x0
LEAPYEAR
Leap Year Indication Register (Read Only)\n
0
1
read-only
0
This year is not a leap year
#0
1
This year is leap year
#1
POWCTL
RTC_POWCTL
RTC Power Time-out Register
0x34
-1
read-write
n
0x0
0x0
ALMIEN
Normal Time Alarm\n
3
1
read-write
0
Normal time alarm control Disabled
#0
1
Normal time alarm control Enabled
#1
EDGE_TRIG
Power Key Trigger Mode \n
5
1
read-write
0
LEVEL TRIGGER, RTC is powered on while power key is pressed longer programmed duration
#0
1
EDGE TRIGE, RTC is powered on while power key is pressed longer than programmed duration and then released
#1
POWEN
Power ON\nRTC_RPWR will change to high state when POWEN value change from 0 to 1.\nNote: The following conditions will make RTC_RPWR low:\nSet POWEN bit to 0\nPOWOFFEN is set to 1 and the power key is pressed over the period of POWOFFT.\nThis bit can be read back after the RTC enable is active.
0
1
read-write
POWKEY
Power Key Status\n
7
1
read-write
0
The power key is pressed to low
#0
1
The power key status is high
#1
POWOFFEN
Hardware Power Clear Enable Control\n
2
1
read-write
0
The RTC_RPWR pin will not be influenced by the pressed time of power key
#0
1
The RTC_RPWR pin will be cleared to low when the power key is pressed over the POWOFFT second
#1
POWOFFT
Power Clear Period\nIndicates that the period of the power core will be cleared after the power key is pressed. Its time scalar is one second so that the default is 5 second.
16
4
read-write
RALMIEN
Relative Time Alarm\n
4
1
read-write
0
The relative time alarm control Disabled
#0
1
The relative time alarm control Enabled
#1
RALMTIME
Relative Time Alarm Period (Second Unit)\nIndicates the period of the relative time alarm. Its maximum value is 1800.\n
20
12
read-write
SWPOWOFF
Software Core Power Disable Control\nIf the power key is pressed, the RTC_RPWR pin can be cleared by setting this bit and this can be cleared to 0 when the pressed power key, RTC_RPWR is released. If the power is not pressed, it is not used to set this bit.\n
1
1
read-write
1
Force the RTC_RPWR to low
#1
RWEN
RTC_RWEN
RTC Access Enable Register
0x4
read-write
n
0x0
0x0
RWEN
RTC Register Access Enable Password (R/W)\n
0
16
read-write
43365
Access Password
0xa965
RWENF
RTC Register Access Enable Flag (Read Only)\nNote: This bit will be set after RTC_RWEN[15:0] register is load a 0xA965, and it will be cleared when RTC_RWEN[15:0] is not 0xA965.
16
1
read-only
0
RTC register access Disabled
#0
1
RTC register access Enabled
#1
SET
RTC_SET
RTC Setting Register
0x38
read-write
n
0x0
0x0
CBEN
32768 Hz (LXT) Crystal Control\n
1
1
read-write
0
Crystal Disabled
#0
1
Crystal Enabled
#1
IOMSEL
X32_IN and X32_OUT PAD Digital Input Mode Control\n
2
1
read-write
0
Digital input mode
#0
1
Crystal mode (default value)
#1
XININDAT
X32_IN PAD Status\n
3
1
read-only
XOUTDAT
X32_OUT PAD Status\n
4
1
read-only
SPR0
RTC_SPR0
RTC Spare Register 0
0x54
read-write
n
0x0
0x0
RTC_SPRn
RTC Spare Register\n
0
32
read-write
SPR1
RTC_SPR1
RTC Spare Register 1
0x58
read-write
n
0x0
0x0
SPR2
RTC_SPR2
RTC Spare Register 2
0x5C
read-write
n
0x0
0x0
SPR3
RTC_SPR3
RTC Spare Register 3
0x60
read-write
n
0x0
0x0
SPR4
RTC_SPR4
RTC Spare Register 4
0x64
read-write
n
0x0
0x0
SPR5
RTC_SPR5
RTC Spare Register 5
0x68
read-write
n
0x0
0x0
SPR6
RTC_SPR6
RTC Spare Register 6
0x6C
read-write
n
0x0
0x0
SPR7
RTC_SPR7
RTC Spare Register 7
0x70
read-write
n
0x0
0x0
SYNC
RTC_SYNC
RTC Register Write Complete
0x44
read-only
n
0x0
0x0
SYNC
Polling the Flag to Detect RTC Register Write Complete\n
0
1
read-only
0
Register cannot be written
#0
1
Register can be written because write complete
#1
TALM
RTC_TALM
RTC Time Alarm Register
0x1C
read-write
n
0x0
0x0
HR
1-Hour Time Digit of Alarm Setting (0-9)
16
4
read-write
MIN
1-Min Time Digit of Alarm Setting (0-9)
8
4
read-write
MSKHR
Mask Alarm by Hour\n
23
1
read-write
0
Activate
#0
1
Mask
#1
MSKMIN
Mask Alarm by Minute\n
15
1
read-write
0
Activate
#0
1
Mask
#1
MSKSEC
Mask Alarm by Second\n
7
1
read-write
0
Activate
#0
1
Mask
#1
SEC
1-Sec Time Digit of Alarm Setting (0-9)
0
4
read-write
TENHR
10-hour Time Digit of Alarm Setting (0-2)\nWhen RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication. (If RTC_TIME[21] is 1, it indicates PM time message.)
20
2
read-write
TENMIN
10-Min Time Digit of Alarm Setting (0-5)
12
3
read-write
TENSEC
10-Sec Time Digit of Alarm Setting (0-5)
4
3
read-write
TICK
RTC_TICK
RTC Time Tick Register
0x30
read-write
n
0x0
0x0
TICKSEL
Time Tick Register\nThese bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. \n
0
3
read-write
0
Time tick is 1 second
#000
1
Time tick is 1/2 second
#001
2
Time tick is 1/4 second
#010
3
Time tick is 1/8 second
#011
4
Time tick is 1/16 second
#100
5
Time tick is 1/32 second
#101
6
Time tick is 1/64 second
#110
7
Time tick is 1/28 second
#111
TIME
RTC_TIME
RTC Time Loading Register
0xC
read-write
n
0x0
0x0
HR
1-Hour Time Digit
16
4
read-write
MIN
1-Min Time Digit
8
4
read-write
SEC
1-Sec Time Digit
0
4
read-write
TENHR
10-Hour Time Digit
20
2
read-write
TENMIN
10-Min Time Digit
12
3
read-write
TENSEC
10-Sec Time Digit
4
3
read-write
WEEKDAY
RTC_WEEKDAY
RTC Day of the Week Register
0x18
-1
read-write
n
0x0
0x0
WEEKDAY
Day of the Week Register \n
0
3
read-write
0
Sunday
0
1
Monday
1
2
Tuesday
2
3
Wednesday
3
4
Thursday
4
5
Friday
5
6
Saturday
6
SCS
SCS Register Map
SCS
0x0
0x10
0xC
registers
n
0x100
0x4
registers
n
0x180
0x4
registers
n
0x200
0x4
registers
n
0x280
0x4
registers
n
0x300
0x4
registers
n
0xD04
0x4
registers
n
0xD0C
0x8
registers
n
0xD18
0xC
registers
n
0xF00
0x4
registers
n
AIRCR
AIRCR
Application Interrupt and Reset Control Register
0xD0C
-1
read-write
n
0x0
0x0
ENDIANNESS
Data Endianness\n
15
1
read-write
0
Little-endian
#0
1
Big-endian
#1
PRIGROUP
Interrupt Priority Grouping\nThis field determines the Split of Group priority from subpriority,
8
3
read-write
SYSRESETREQ
System Reset Request\nWriting this bit to 1 will cause a reset signal to be asserted to the chip and indicate a reset is requested\nNote: This bit is write only and self-cleared as part of the reset sequence.
2
1
read-write
VECTCLRACTIVE
Exception Active Status Clear Bit\nSetting this bit to 1 will clear all active state information for fixed and configurable exceptions\nNote1: This bit is write only and can only be written when the core is halted.\nNote2: It is the debugger's responsibility to re-initialize the stack.
1
1
read-write
VECTORKEY
Register Access Key
When writing this register, this field should be 0x05FA otherwise, the write action will be unpredictable.
The VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status.
16
16
read-write
ICSR
ICSR
Interrupt Control and State Register
0xD04
read-write
n
0x0
0x0
ISRPENDING
Interrupt Pending Flag, Excluding NMI and Faults (Read Only)\n
22
1
read-only
0
Interrupt not pending
#0
1
Interrupt pending
#1
ISRPREEMPT
Interrupt Preempt Bit (Read Only)\nIf set, a pending exception will be serviced on exit from the debug halt state.
23
1
read-only
NMIPENDSET
NMI Set-pending Bit\nWrite Operation:\nNote: Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.
31
1
read-write
0
No effect.\nNMI exception is not pending
#0
1
Changes NMI exception state to pending.\nNMI exception is pending
#1
PENDSTCLR
SysTick Exception Clear-pending Bit
Write Operation:
Note: This is a write only bit. To clear the PENDST bit, you must write 0 to PENDSTSET and write 1 to PENDSTRTC_CAL at the same time.
25
1
read-write
0
No effect
#0
1
Removes the pending state from the SysTick exception
#1
PENDSTSET
SysTick Exception Set-pending Bit\nWrite Operation:\n
26
1
read-write
0
No effect.\nSysTick exception is not pending
#0
1
Change SysTick exception state to pending.\nSysTick exception is pending
#1
PENDSVCLR
PendSV Clear-pending Bit
Write Operation:
Note: This is a write only bit. To clear the PENDSV bit, you must write 0 to PENDSVSET and write 1 to PENDSVRTC_CAL at the same time.
27
1
read-write
0
No effect
#0
1
Removes the pending state from the PendSV exception
#1
PENDSVSET
PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending.
28
1
read-write
0
No effect.\nPendSV exception is not pending
#0
1
Changes PendSV exception state to pending.\nPendSV exception is pending
#1
RETTOBASE
Preempted Active Exceptions Indicator\nIndicate whether there are preempted active exceptions.\n
11
1
read-write
0
There are preempted active exceptions to execute
#0
1
There are no active exceptions, or the currently-executing exception is the only active exception
#1
VECTACTIVE
Number of the Current Active Exception \n
0
6
read-write
0
Thread mode
0
VECTPENDING
Number of the Highest Pended Exception\nIndicates the exception number of the highest priority pending enabled exception.\nNote: The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but does not include any effect of the PRIMASK register.
12
6
read-write
0
No pending exceptions
0
NVIC_IABR0
NVIC_IABR0
IRQ0 ~ IRQ31 Active Bit Register
0x300
read-write
n
0x0
0x0
ACTIVE
Interrupt Active Flags\nThe NVIC_IABR0 registers indicate which interrupts are active. \n
0
32
read-write
0
Interrupt is not active
0
1
Interrupt is active
1
NVIC_ICER0
NVIC_ICER0
IRQ0 ~ IRQ31 Clear-enable Control Register
0x180
read-write
n
0x0
0x0
CLRENA
Interrupt Clear Enable Control\nThe NVIC_ICER0 registers disable interrupts, and show which interrupts are enabled.\nWrite Operation:\n
0
32
read-write
0
No effect.\nInterrupt Disabled
0
1
Interrupt Disabled.\nInterrupt Enabled
1
NVIC_ICPR0
NVIC_ICPR0
IRQ0 ~ IRQ31 Clear-pending Control Register
0x280
read-write
n
0x0
0x0
CLRPEND
Interrupt Clear-pending\nThe NVIC_ICPR0 registers remove the pending state from interrupts, and show which interrupts are pending\nWrite Operation:\n
0
32
read-write
0
No effect.\nInterrupt is not pending
0
1
Removes pending state an interrupt.\nInterrupt is pending
1
NVIC_ISER0
NVIC_ISER0
IRQ0 ~ IRQ31 Set-enable Control Register
0x100
read-write
n
0x0
0x0
SETENA
Interrupt Set Enable Control\nThe NVIC_ISER0 registers enable interrupts, and show which interrupts are enabled\nWrite Operation:\n
0
32
read-write
0
No effect.\nInterrupt Disabled
0
1
Interrupt Enabled
1
NVIC_ISPR0
NVIC_ISPR0
IRQ0 ~ IRQ31 Set-pending Control Register
0x200
read-write
n
0x0
0x0
SETPEND
Interrupt Set-pending \nThe NVIC_ISPR0 registers force interrupts into the pending state, and show which interrupts are pending\nWrite Operation:\n
0
32
read-write
0
No effect.\nInterrupt is not pending
0
1
Changes interrupt state to pending.\nInterrupt is pending
1
NVIC_STIR
NVIC_STIR
Software Trigger Interrupt Registers
0xF00
write-only
n
0x0
0x0
INTID
Write to the STIR to Generate an Interrupt From Software\nWhen the USERSETMPEND bit in the SCR is set to 1, unprivileged software can access the STIR\nInterrupt ID of the interrupt to trigger, in the range 0-47. For example, a value of 0x03 specifies interrupt IRQ3.
0
9
write-only
SCR
SCR
System Control Register
0xD10
read-write
n
0x0
0x0
SEVONPEND
Send Event on Pending\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event.
4
1
read-write
0
Only enabled interrupts or events can wake up the processor, while disabled interrupts are excluded
#0
1
Enabled events and all interrupts, including disabled interrupts, can wake up the processor
#1
SLEEPDEEP
Processor Deep Sleep and Sleep Mode Selection\nControl whether the processor uses Idle mode or Power-down mode as its low power operation.\n
2
1
read-write
0
Idle mode
#0
1
Power-down mode
#1
SLEEPONEXIT
Sleep-on-exit Enable Control\nThis bit indicates Sleep-On-Exit when returning from handler mode to thread mode.\nSetting this bit to 1 will enable an interrupt driven application to avoid returning to an empty main application.
1
1
read-write
0
Do not enter idle mode when returning to Thread mode
#0
1
Enter Idle mode, or Power-down mode, on return from an ISR to Thread mode
#1
SHPR1
SHPR1
System Handler Priority Register 1
0xD18
read-write
n
0x0
0x0
PRI_4
Priority of System Handler 4 - MemManage
0 denotes the highest priority and 3 denotes the lowest priority.
0
8
read-write
PRI_5
Priority of System Handler 5 - BusFault
0 denotes the highest priority and 3 denotes the lowest priority.
8
8
read-write
PRI_6
Priority of System Handler 6 - UsageFault
0 denotes the highest priority and 3 denotes the lowest priority.
16
8
read-write
SHPR2
SHPR2
System Handler Priority Register 2
0xD1C
read-write
n
0x0
0x0
PRI_11
Priority of System Handler 11 - SVCall
0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
SHPR3
SHPR3
System Handler Priority Register 3
0xD20
read-write
n
0x0
0x0
PRI_14
Priority of System Handler 14 - PendSV
0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_15
Priority of System Handler 15 - SysTick
0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
SYST_CSR
SYST_CSR
SysTick Control and Status Register
0x10
read-write
n
0x0
0x0
CLKSRC
SysTick Counting Clock Source Select\n
2
1
read-write
0
Clock source is (optional) external reference clock
#0
1
Core clock used for SysTick
#1
COUNTFLAG
Returns 1 If Timer Counted to 0 Since Last Time this Register Was Read\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register.
16
1
read-write
ENABLE
SysTick Function Enable Control\n
0
1
read-write
0
Counter Disabled
#0
1
Counter will operate in a multi-shot manner
#1
TICKINT
SysTick Interrupt Enable Control\n
1
1
read-write
0
Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred
#0
1
Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTickcurrent value register by a register write in software will not cause SysTick to be pended
#1
SYST_CVR
SYST_CVR
SysTick Current Value Register
0x18
read-write
n
0x0
0x0
CURRENT
Current Counter Value\nThis is the value of the counter at the time it is sampled.The counter does not provide read-modify-write protection.The register is write-clear.A software write of any value will clear the register to 0.Unsupported bits RAZ (See SysTick reload value register).
0
24
read-write
SYST_RVR
SYST_RVR
SysTick Reload Value Register
0x14
read-write
n
0x0
0x0
RELOAD
SysTick Reload Value\nThe value to load into the Current Value register when the counter reaches 0.
0
24
read-write
SDH
SDH Register Map
SDH
0x0
0x0
0x4
registers
n
0x400
0x4
registers
n
0x408
0x10
registers
n
0x800
0xC
registers
n
0x820
0x20
registers
n
BLEN
SDH_BLEN
SD Block Length Register
0x838
-1
read-write
n
0x0
0x0
BLKLEN
SD BLOCK LENGTH in Byte Unit\nAn 11-bit value specifies the SD transfer byte count of a block. The actual byte count is equal to BLKLEN +1.\nNote: The default SD block length is 512 bytes.
0
11
read-write
CMDARG
SDH_CMDARG
SD Command Argument Register
0x824
read-write
n
0x0
0x0
ARGUMENT
SD Command Argument\nThis register contains a 32-bit value specifies the argument of SD command from host controller to SD card. Before triggering SDH_CTL [COEN], software should fill argument in this field.
0
32
read-write
CTL
SDH_CTL
SD Control and Status Register
0x820
-1
read-write
n
0x0
0x0
BLKCNT
Block Counts to Be Transferred or Received\nThis field contains the block counts for data-in and data-out transfer. For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, software can use this function to accelerate data transfer and improve performance. Don't fill 0x0 to this field.\nFor READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the actual total length is BLKCNT * (BLKLEN +1).
16
8
read-write
CLK74OEN
Generating 74 Clock Cycles Output Enable Control\nNote: When operation is finished, this bit will be cleared automatically. Thus, don't write 0 to this bit (the controller will be abnormal).
5
1
read-write
0
No effect. (Please use SDH_CTL[CTLRST] to clear this bit.)
#0
1
Enabled, SD host will output 74 clock cycles to SD card
#1
CLK8OEN
Generating 8 Clock Cycles Output Enable Control\nNote: When operation is finished, this bit will be cleared automatically. Thus, don't write 0 to this bit (the controller will be abnormal).
6
1
read-write
0
No effect. (Please use SDH_CTL[CTLRST] to clear this bit.)
#0
1
Enabled, and SD host will output 8 clock cycles
#1
CLKKEEP0
SD Clock Enable Control for Port 0\n
7
1
read-write
0
SD host decides when to output clock and when to disable clock output automatically
#0
1
SD clock always keeps free running
#1
CMDCODE
SD Command Code\nThis register contains the SD command code (0x00 - 0x3F).
8
6
read-write
COEN
Command Output Enable Control\nNote: When operation is finished, this bit will be cleared automatically. Thus, don't write 0 to this bit (the controller will be abnormal).
0
1
read-write
0
No effect. (Please use SDH_CTL[CTLRST] to clear this bit.)
#0
1
Enabled, SD host will output a command to SD card
#1
CTLRST
Software Engine Reset\n
14
1
read-write
0
No effect
#0
1
Reset the internal state machine and counters. The contents of control register will not be cleared (but RIEN, DIEN, DOEN and R2EN will be cleared). This bit will be auto cleared after few clock cycles
#1
DBW
SD Data Bus Width (for 1-bit / 4-bit Selection)\n
15
1
read-write
0
Data bus width is 1-bit
#0
1
Data bus width is 4-bit
#1
DIEN
Data Input Enable Control\nNote: When operation is finished, this bit will be cleared automatically. Thus, don't write 0 to this bit (the controller will be abnormal).
2
1
read-write
0
No effect. (Please use SDH_CTL[CTLRST] to clear this bit.)
#0
1
Enabled, SD host will wait to receive block data and the CRC-16 value from SD card
#1
DOEN
Data Output Enable Control\nNote: When operation is finished, this bit will be cleared automatically. Thus, don't write 0 to this bit (the controller will be abnormal).
3
1
read-write
0
No effect. (Please use SDH_CTL[CTLRST] to clear this bit.)
#0
1
Enabled, SD host will transfer block data and the CRC-16 value to SD card
#1
R2EN
Response R2 Input Enable Control\nNote: When operation is finished, this bit will be cleared automatically. Thus, don't write 0 to this bit (the controller will be abnormal).
4
1
read-write
0
No effect. (Please use SDH_CTL[CTLRST] to clear this bit.)
#0
1
Enabled, SD host will wait to receive a response R2 from SD card and store the response data into DMAC's flash buffer (exclude CRC-7)
#1
RIEN
Response Input Enable Control\nNote: When operation is finished, this bit will be cleared automatically. Thus, don't write 0 to this bit (the controller will be abnormal).
1
1
read-write
0
No effect. (Please use SDH_CTL[CTLRST] to clear this bit.)
#0
1
Enabled, SD host will wait to receive a response from SD card
#1
SDNWR
NWR Parameter for Block Write Operation\nThis value indicates the NWR parameter for data block write operation in SD clock counts. The actual clock cycle will be SDNWR+1.
24
4
read-write
DMABCNT
SDH_DMABCNT
DMAC Transfer Byte Count Register
0x40C
read-only
n
0x0
0x0
BCNT
DMA Transfer Byte Count (Read Only)
This field indicates the remained byte count of DMAC transfer. The value of this field is valid only when DMAC is busy otherwise, it is 0.
0
26
read-only
DMACTL
SDH_DMACTL
DMAC Control and Status Register
0x400
read-write
n
0x0
0x0
DMABUSY
DMA Transfer in Progress\nThis bit indicates that the DMA is transferred or not.\n
9
1
read-write
0
DMA transfer is not in progress
#0
1
DMA transfer is in progress
#1
DMAEN
DMAC Engine Enable Control\nNote1: If this bit is cleared, DMAC will ignore all DMA request and force Bus Master into IDLE state.\nNote2: If a target abort occurs, DMAEN will be cleared.
0
1
read-write
0
DMAC Disabled
#0
1
DMAC Enabled
#1
DMARST
Software Engine Reset\nNote: Software resets DMA region.
1
1
read-write
0
No effect
#0
1
Reset internal state machine and pointers. The contents of control register will not be cleared. This bit will auto be cleared after few clock cycles
#1
SGEN
Scatter-gather Function Enable Control\n
3
1
read-write
0
Scatter-gather function Disabled (DMAC will treat the starting address in SDH_DMASA as starting pointer of a single block memory)
#0
1
Scatter-gather function Enabled (DMAC will treat the starting address in SDH_DMASA as a starting address of Physical Address Descriptor (PAD) table. The format of these PADs' will be described later)
#1
DMAINTEN
SDH_DMAINTEN
DMAC Interrupt Enable Control Register
0x410
-1
read-write
n
0x0
0x0
ABORTIEN
DMA Read/Write Target Abort Interrupt Enable Control\n
0
1
read-write
0
Target abort interrupt generation Disabled during DMA transfer
#0
1
Target abort interrupt generation Enabled during DMA transfer
#1
WEOTIEN
Wrong EOT Encountered Interrupt Enable Control\n
1
1
read-write
0
Interrupt generation Disabled when wrong EOT is encountered
#0
1
Interrupt generation Enabled when wrong EOT is encountered
#1
DMAINTSTS
SDH_DMAINTSTS
DMAC Interrupt Status Register
0x414
read-write
n
0x0
0x0
ABORTIF
DMA Read/Write Target Abort Interrupt Flag\nNote: This bit is read only, but can be cleared by writing '1' to it.
0
1
read-write
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
WEOTIF
Wrong EOT Encountered Interrupt Flag\nWhen DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of DMAC), this bit will be set.\nNote: This bit is read only, but can be cleared by writing '1' to it.
1
1
read-write
0
No EOT encountered before DMA transfer finished
#0
1
EOT encountered before DMA transfer finished
#1
DMASA
SDH_DMASA
DMAC Transfer Starting Address Register
0x408
read-write
n
0x0
0x0
DMASA
DMA Transfer Starting Address \nThis field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMAC to retrieve or fill in data.\nIf DMAC is not in Normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table.\nNote: The address can't be set smaller than 0x2000_0000.
1
31
read-write
ORDER
Determined to the PAD Table Fetching in Order or Out of Order\n
0
1
read-write
0
PAD table is fetched in order
#0
1
PAD table is fetched out of order
#1
FB_N
SDH_FB_N
SDH Receiving/Transmit Flash Buffer
0x0
read-write
n
0x0
0x0
DATA
SDH Receiving/Transmit Flash Buffer\nThis buffer is used to receive/transmit data. It can be accessed by CPU or DMAC.
0
32
read-write
GCTL
SDH_GCTL
Global Control and Status Register
0x800
read-write
n
0x0
0x0
GCTLRST
Software Engine Reset\n
0
1
read-write
0
No effect
#0
1
Reset all SDH engines. The contents of control registers will not be cleared. This bit will auto cleared after few clock cycles
#1
SDEN
Secure-digital Functionality Enable Control\n
1
1
read-write
0
SD functionality Disabled
#0
1
SD functionality Enabled
#1
GINTEN
SDH_GINTEN
Global Interrupt Control Register
0x804
-1
read-write
n
0x0
0x0
DTAIEN
DMAC READ/WRITE Target Abort Interrupt Enable Control\n
0
1
read-write
0
DMAC READ/WRITE target abort interrupt generation Disabled
#0
1
DMAC READ/WRITE target abort interrupt generation Enabled
#1
GINTSTS
SDH_GINTSTS
Global Interrupt Status Register
0x808
read-write
n
0x0
0x0
DTAIF
DMAC READ/WRITE Target Abort Interrupt Flag (Read Only)\nThis bit indicates DMAC received an ERROR response from internal AHB bus during DMA read/write operation. When Target Abort is occurred, please reset all engines.\nNote: This bit is read only, but can be cleared by writing '1' to it.
0
1
read-only
0
No bus ERROR response received
#0
1
Bus ERROR response received
#1
INTEN
SDH_INTEN
SD Interrupt Control Register
0x828
-1
read-write
n
0x0
0x0
BLKDIEN
Block Transfer Done Interrupt Enable Control\n
0
1
read-write
0
SD host will not generate interrupt when data-in (out) transfer done
#0
1
SD host will generate interrupt when data-in (out) transfer done
#1
CDIEN0
SD0 Card Detection Interrupt Enable Control\nEnable/Disable interrupt generation of SD controller when card 0 is inserted or removed.\n
8
1
read-write
0
SD0 Card Detection Interrupt Disabled
#0
1
SD0 Card Detection Interrupt Enabled
#1
CDSRC0
SD0 Card Detect Source Selection\n
30
1
read-write
0
From SD0 card's DAT3 pin
#0
1
From GPIO pin
#1
CRCIEN
CRC7, CRC16 and CRC Status Error Interrupt Enable Control\n
1
1
read-write
0
SD host will not generate interrupt when CRC7, CRC16 and CRC status is error
#0
1
SD host will generate interrupt when CRC7, CRC16 and CRC status is error
#1
DITOIEN
Data Input Time-out Interrupt Enable Control\nEnable/Disable interrupt generation of SD controller when data input time-out. Time-out value is specified at TOUT.\n
13
1
read-write
0
Data Input Time-out Interrupt Disabled
#0
1
Data Input Time-out Interrupt Enabled
#1
RTOIEN
Response Time-out Interrupt Enable Control\nEnable/Disable interrupt generation of SD controller when receiving response or R2 time-out. Time-out value is specified at TOUT.\n
12
1
read-write
0
Response Time-out Interrupt Disabled
#0
1
Response Time-out Interrupt Enabled
#1
SDHIEN0
SDH Interrupt Enable Control for Port 0\nEnable/Disable interrupt generation of SD host when SDH card 0 issues an interrupt via DAT [1] to host.\n
10
1
read-write
0
SDH Port 0 Interrupt Disabled
#0
1
SDH Port 0 Interrupt Enabled
#1
INTSTS
SDH_INTSTS
SD Interrupt Status Register
0x82C
-1
read-write
n
0x0
0x0
BLKDIF
Block Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that SD host has finished all data-in or data-out block transfer. If there is a CRC16 error or incorrect CRC status during multiple block data transfer, the transfer will be broken and this bit will also be set.\nNote: This bit is read only, but can be cleared by writing '1' to it.
0
1
read-only
0
Not finished yet
#0
1
Done
#1
CDIF0
SD0 Card Detection Interrupt Flag (Read Only)\nThis bit indicates that SD card 0 is inserted or removed. Only when CDIEN0 (SDH_INTEN[8]) is set to 1, this bit is active.\nNote: This bit is read only, but can be cleared by writing '1' to it.
8
1
read-only
0
No card is inserted or removed
#0
1
There is a card inserted in or removed from SD0
#1
CDSTS0
Card Detect Status of SD0 (Read Only)\nThis bit indicates the card detect pin status of SD0, and is used for card detection. When there is a card inserted in or removed from SD0, software should check this bit to confirm if there is really a card insertion or removal.\n
16
1
read-only
0
Card removed.\nCard inserted
#0
1
Card inserted.\nCard removed
#1
CRC16
CRC-16 Check Status of Data-in Transfer (Read Only)\nSD host will check CRC-16 correctness after data-in transfer.\n
3
1
read-only
0
CRC-16 Transfer incorrectness
#0
1
CRC-16 Transfer correctness
#1
CRC7
CRC-7 Check Status (Read Only)\nSD host will check CRC-7 correctness during each response in. If that response does not contain CRC-7 information (e.g. R3), then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit.\n
2
1
read-only
0
CRC-7 Transfer incorrectness
#0
1
CRC-7 Transfer correctness
#1
CRCIF
CRC7, CRC16 and CRC Status Error Interrupt Flag (Read Only)
This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer. When CRC error occurred, software should reset SD engine. Some responses (e.g. R3) do not have CRC-7 information with it the SD host will still calculate CRC-7, get CRC error and set this flag. In this condition, software should ignore CRC error and clear this bit manually.
Note: This bit is read only, but can be cleared by writing '1' to it.
1
1
read-only
0
No CRC error is occurred
#0
1
CRC error is occurred
#1
CRCSTS
CRC Status Value of Data-out Transfer (Read Only)\nSD host will record CRC status of data-out transfer. Software could use this value to identify what type of error is during data-out transfer.\n
4
3
read-only
2
Positive CRC status
#010
5
Negative CRC status
#101
7
SD card programming error occurs
#111
DAT0STS
DAT0 Pin Status of Current Selected SD Port (Read Only)\nThis bit is the DAT0 pin status of current selected SD port.
7
1
read-only
DAT1STS
DAT1 Pin Status of SD Port (Read Only)\nThis bit indicates the DAT1 pin status of SD port.
18
1
read-only
DITOIF
Data Input Time-out Interrupt Flag (Read Only)\nThis bit indicates that SD host counts to time-out value when receiving data (waiting start bit).\nNote: This bit is read only, but can be cleared by writing '1' to it.
13
1
read-only
0
No time-out
#0
1
Data input time-out
#1
RTOIF
Response Time-out Interrupt Flag (Read Only)\nThis bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit).\nNote: This bit is read only, but can be cleared by writing '1' to it.
12
1
read-only
0
No time-out
#0
1
Response time-out
#1
SDHIF0
SDH 0 Interrupt Flag (Read Only)\nThis bit indicates that SDH card 0 issues an interrupt to host. This interrupt is designed to level sensitive. Before clearing it, turn off SDHIEN0 (SDH_INTEN[10]) first.\nNote: This bit is read only, but can be cleared by writing '1' to it.
10
1
read-only
0
No interrupt is issued by SDH card 0
#0
1
an interrupt is issued by SDH card 0
#1
RESP0
SDH_RESP0
SD Receiving Response Token Register 0
0x830
read-only
n
0x0
0x0
RESPTK0
SD Receiving Response Token 0\nSD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set. This field contains response bit 47-16 of the response token.
0
32
read-only
RESP1
SDH_RESP1
SD Receiving Response Token Register 1
0x834
read-only
n
0x0
0x0
RESPTK1
SD Receiving Response Token 1\nSD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set. This register contains the bit 15-8 of the response token.
0
8
read-only
TOUT
SDH_TOUT
SD Response/Data-in Time-out Register
0x83C
read-write
n
0x0
0x0
TOUT
SD Response/Data-in Time-out Value\nA 24-bit value specifies the time-out count of response and data input. SD host controller will wait the start bit of response or data-in until this value reached. The time period depends on SD engine clock frequency. Do not write a small number into this field, or you may never get response or data due to time-out.\nNote: Filling 0x0 into this field will disable hardware time-out function.
0
24
read-write
SPI0
SPI Register Map
SPI
0x0
0x0
0xC
registers
n
0x10
0x8
registers
n
0x20
0x4
registers
n
0x30
0x4
registers
n
SPI_CLKDIV
SPI_CLKDIV
SPI Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI engine clock, fspi_eclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. \n\nwhere \n is the SPI engine clock source, which is defined in the clock control, clock control register.
0
8
read-write
SPI_CTL
SPI_CTL
SPI Control Register
0x0
-1
read-write
n
0x0
0x0
CLKPOL
Clock Polarity\n
3
1
read-write
0
SPICLK is idle low
#0
1
SPICLK is idle high
#1
DWIDTH
Data Transmit Bit Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n
8
5
read-write
LSB
Send LSB First\n
13
1
read-write
0
The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX)
#1
REORDER
Byte Reorder Function Enable Control\nNote: Byte reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
19
1
read-write
0
Byte reorder function Disabled
#0
1
Byte reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4])
#1
RXNEG
Receive on Negative Edge\n
1
1
read-write
0
Received data input signal is latched on the rising edge of SPICLK
#0
1
Received data input signal is latched on the falling edge of SPICLK
#1
SLAVE
Slave Mode Enable Control\n
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SPIEN
SPI Transfer Control Enable Bit\nNote1: In Master mode, the transfer will start when there is data in the FIFO buffer after this is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1. \nNote2: The byte reorder function is not supported when the Quad or Dual I/O mode is enabled.
0
1
read-write
0
Transfer control bit Disabled
#0
1
Transfer control bit Enabled
#1
SUSPITV
Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0]+0.5) * period of SPICLK clock cycle\nExample:\n
4
4
read-write
TXNEG
Transmit on Negative Edge\n
2
1
read-write
0
Transmitted data output signal is changed on the rising edge of SPICLK
#0
1
Transmitted data output signal is changed on the falling edge of SPICLK
#1
UNITIEN
Unit Transfer Interrupt Enable Control\n
17
1
read-write
0
SPI unit transfer interrupt Disabled
#0
1
SPI unit transfer interrupt Enabled
#1
SPI_FIFOCTL
SPI_FIFOCTL
SPI FIFO Control Register
0x10
-1
read-write
n
0x0
0x0
RXFBCLR
Clear Receive FIFO\n Note: Auto cleared by Hardware.
8
1
read-write
0
No effect
#0
1
Clear receive FIFO only
#1
RXOVIEN
Receive FIFO Overrun Interrupt Enable Control\n
5
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RXRST
Clear Receive FIFO Control\nNote: If there is slave receive time-out event, the RXRST will be set 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
0
1
read-write
0
No effect
#0
1
Clear receive FIFO control. The RXFULL (SPI_STATUS[9]) will be cleared to 0 and the RXEMPTY (SPI_STATUS[8]) will be set to 1. This bit will be cleared to 0 by hardware about 3 system clocks+3 SPI engine clock after it is set to 1
#1
RXTH
Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF (SPI_STATUS[10]) will be set to 1, else the RXTHIF (SPI_STATUS[10]) will be cleared to 0.
24
3
read-write
RXTHIEN
Receive FIFO Threshold Interrupt Enable Control\n
2
1
read-write
0
RX FIFO threshold interrupt Disabled
#0
1
RX FIFO threshold interrupt Enabled
#1
RXTOIEN
Slave Receive Time-out Interrupt Enable Control\n
4
1
read-write
0
Receive time-out interrupt Disabled
#0
1
Receive time-out interrupt Enabled
#1
TXFBCLR
Clear Transmit FIFO\n Note: Auto cleared by Hardware.
9
1
read-write
0
No effect
#0
1
Clear transmit FIFO only
#1
TXRST
Clear Transmit FIFO Control\nNote: If there is slave receive time-out event, the TXRST will be set 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
1
1
read-write
0
No effect
#0
1
Clear transmit FIFO control. The TXFULL (SPI_STATUS[17]) will be cleared to 0 and the TXEMPTY (SPI_STATUS[16]) will be set to 1. This bit will be cleared to 0 by hardware about 3 system clocks+3 SPI engine clock after it is set to 1
#1
TXTH
Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF (SPI_STATUS[18]) will be set to 1, else the TXTHIF (SPI_STATUS[18]) will be cleared to 0.
28
3
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable Control\n
3
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
TXUFIEN
Slave Transmit Under Run Interrupt Enable Control\n
7
1
read-write
0
Slave Transmit FIFO under-run interrupt Disabled
#0
1
Slave Transmit FIFO under-run interrupt Enabled
#1
TXUFPOL
Transmit Under-run Data Out\nNote1: The under run event is active after the serial clock input and the hardware synchronous, so that the first 1~3 bit (depending on the relation between system clock and the engine clock) data out will be the last transaction data.\nNote2: If the frequency of system clock approach to engine clock, they may need 3-bit time to report the transmit under-run data out.
6
1
read-write
0
The SPI data out is keep 0 if there is transmit under-run event in Slave mode
#0
1
The SPI data out is keep 1 if there is transmit under-run event in Slave mode
#1
SPI_RX
SPI_RX
SPI Data Receive Register
0x30
read-only
n
0x0
0x0
RX
Data Receive Register\nThere is 8-level FIFO buffer in this controller. The data receive register holds the earliest datum received from SPI data input pin. If the RXEMPTY (SPI_STATUS[8]) is not set to 1, the receive FIFO buffer can be accessed through software by reading this register. This is a read-only register.
0
32
read-only
SPI_SSCTL
SPI_SSCTL
SPI Slave Select Control Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select Function Enable (Master Only)\n
3
1
read-write
0
If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bit of SPI_SSCTL[0]
#0
1
If this bit is set, SS signal will be generated automatically. It means that device/slave select signal, which is set in SPI_SSCTL[0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
#1
SLV3WIRE
Slave 3-wire Mode Enable Control\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI.\n
4
1
read-write
0
2-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLVBEIEN
Slave Mode Error 0 Interrupt Enable Control\n
8
1
read-write
0
Slave mode error 0 interrupt Disable
#0
1
Slave mode error 0 interrupt Enable
#1
SLVTOCNT
Slave Mode Time-out Period \nIn Slave mode, these bits indicate the time-out period when there is serial clock input during slave select active. The clock source of the time-out counter is Slave engine clock. If the value is 0, it indicates the slave mode time-out function is disabled.
16
16
read-write
SLVTOIEN
Slave Mode Time-out Interrupt Enable Control\n
5
1
read-write
0
Slave mode time-out interrupt Disabled
#0
1
Slave mode time-out interrupt Enabled
#1
SLVTORST
Slave Mode Time-out FIFO Clear\nNote: Both the FIFO clear function, TX_CLK and RXRST, active automatically when there is a slave mode time-out event.
6
1
read-write
0
Slave mode Time-out FIFO Clear Disable
#0
1
Slave mode Time-out FIFO Clear Enable
#1
SLVURIEN
Slave Mode Error 1 Interrupt Enable Control\n
9
1
read-write
0
Slave mode error 1 interrupt Disable
#0
1
Slave mode error 1 interrupt Enable
#1
SS
Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0,\n
0
1
read-write
0
set the SPIn_SS line to inactive state.\nKeep the SPIn_SS line at inactive state
#0
1
set the SPIn_SS line to active state.\nSPIn_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIn_SS is specified in SSACTPOL (SPI_SSCTL[2])
#1
SSACTIEN
Slave Select Active Interrupt Enable Control\n
12
1
read-write
0
Slave select active interrupt Disable
#0
1
Slave select active interrupt Enable
#1
SSACTPOL
Slave Select Active Level\nThis bit defines the active status of slave select signal (SS).\n
2
1
read-write
0
The slave select signal SS is active on low-level
#0
1
The slave select signal SS is active on high-level
#1
SSINAIEN
Slave Select Inactive Interrupt Enable Control\n
13
1
read-write
0
Slave select inactive interrupt Disable
#0
1
Slave select inactive interrupt Enable
#1
SPI_STATUS
SPI_STATUS
SPI Status Register
0x14
-1
read-write
n
0x0
0x0
BUSY
SPI Unit Bus Status (Read Only)\n
0
1
read-only
0
No transaction in the SPI bus
#0
1
SPI controller unit in busy state
#1
RXCNT
Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
24
4
read-only
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\n
8
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RXFULL
Receive FIFO Buffer Empty Indicator (Read Only)\n
9
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RXOVIF
Receive FIFO Overrun Status\nNote: This bit will be cleared by writing 1 to itself.
11
1
read-write
0
No receiver FIFO overrun status
#0
1
Receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1
#1
RXTHIF
Receive FIFO Threshold Interrupt Status (Read Only)\n
10
1
read-only
0
The valid data count within the RX FIFO buffer is smaller than or equal to the setting value of RXTH (SPI_FIFOCTL[26:24])
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RXTH (SPI_FIFOCTL[26:24])
#1
RXTOIF
Receive Time-out Interrupt Status\nNote: This bit will be cleared by writing 1 to itself.
12
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI engine clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
SLVBEIF
Slave Mode Error 0 Interrupt Status (Read Only)\nIn Slave mode, there is bit counter mismatch with DWIDTH (SPI_CTL[12:8]) when the slave select line goes to inactive state.\nNote: If the slave select active but there is no any serial clock input, the SLVBEIF (SPI_STATUS[6]) also active when the slave select goes to inactive state.
6
1
read-only
0
No Slave mode error 0 event
#0
1
Slave mode error 0 occurs
#1
SLVTOIF
Slave Time-out Interrupt Status (Read Only)\nWhen the Slave Select is active and the value of SLVTOCNT (SPI_SSCTL[31:16]) is not 0 and the serial clock input, the slave time-out counter in SPI controller logic will be start. When the value of time-out counter greater or equal than the value of SLVTOCNT (SPI_SSCTL[31:16]) during before one transaction done, the slave time-out interrupt event will active.\nNote: If the DWIDTH (SPI_CTL[12:8]) is set 0x10, one transaction is equal 16 bits serial clock period.
5
1
read-only
0
Slave time-out is not active
#0
1
Slave time-out is active
#1
SLVURIF
Slave Mode Error 1 Interrupt Status (Read Only)\nIn Slave mode, transmit under-run occurs when the slave select line goes to inactive state.\n
7
1
read-only
0
No Slave mode error 1 event
#0
1
Slave mode error 1 occurs
#1
SPIENSTS
SPI Enable Bit Status (Read Only)\nThe clock source of SPI controller logic is engine clock, it is asynchronous with the system clock. In order to make sure the function is disabled in SPI controller logic, this bit indicates the real status of SPIEN (SPI_CTL[0]) in SPI controller logic for user.
15
1
read-only
0
Indicate the transmit control bit is disabled
#0
1
Indicate the transfer control bit is active
#1
SSACTIF
Slave Select Active Interrupt Status\nNote: This bit will be cleared by writing 1 to itself.
2
1
read-write
0
Slave select active interrupt is cleared or did not occur
#0
1
Slave select active interrupt event has occurred
#1
SSINAIF
Slave Select Inactive Interrupt Status\nNote: This bit will be cleared by writing 1 to itself.
3
1
read-write
0
Slave select inactive interrupt is cleared or did not occur
#0
1
Slave select inactive interrupt event has occurred
#1
SSLINE
Slave Select Line Bus Status (Read Only)\nNote: If SSACTPOL (SPI_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
4
1
read-only
0
Indicates the slave select line bus status is 0
#0
1
Indicates the slave select line bus status is 1
#1
TXCNT
Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\n
16
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TXFULL
Transmit FIFO Buffer Full Indicator (Read Only)\n
17
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TXRXRST
FIFO CLR Status (Read Only)\nNote: Both the TXRST (SPI_FIFOCTL[1]), RXRST (SPI_FIFOCTL[0]), need 3 system clock+3 engine clock , the status of this bit support the user to monitor the clear function is doing or done.
23
1
read-only
0
Done the FIFO buffer clear function of TXRST (SPI_FIFOCTL[1]) or RXRST (SPI_FIFOCTL[0])
#0
1
Doing the FIFO buffer clear function of TXRST (SPI_FIFOCTL[1])or RXRST (SPI_FIFOCTL[0])
#1
TXTHIF
Transmit FIFO Threshold Interrupt Status (Read Only)\n
18
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH (SPI_FIFOCTL[30:28])
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH (SPI_FIFOCTL[30:28])
#1
TXUFIF
TX Underflow Interrupt Flag\nWhen the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 3 system clock cycles + 2 peripheral clock cycles since the reset operation is done.
19
1
read-write
0
No effect
#0
1
No data in Transmit FIFO and TX shift register when the slave selection signal is active
#1
UNITIF
Unit Transfer Interrupt Status\nNote: This bit will be cleared by writing 1 to itself.
1
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
SPI_TX
SPI_TX
SPI Data Transmit Register
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffer. The number of valid bits depends on the setting of transmit bit width field of the SPI_CTL register.\nFor example, if DWIDTH (SPI_CTL[12:8]) is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH (SPI_CTL[12:8]) is set to 0x00, the SPI controller will perform a 32-bit transfer.
0
32
write-only
SPI1
SPI Register Map
SPI
0x0
0x0
0xC
registers
n
0x10
0x8
registers
n
0x20
0x4
registers
n
0x30
0x4
registers
n
SPI_CLKDIV
SPI_CLKDIV
SPI Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI engine clock, fspi_eclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. \n\nwhere \n is the SPI engine clock source, which is defined in the clock control, clock control register.
0
8
read-write
SPI_CTL
SPI_CTL
SPI Control Register
0x0
-1
read-write
n
0x0
0x0
CLKPOL
Clock Polarity\n
3
1
read-write
0
SPICLK is idle low
#0
1
SPICLK is idle high
#1
DWIDTH
Data Transmit Bit Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n
8
5
read-write
LSB
Send LSB First\n
13
1
read-write
0
The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX)
#1
REORDER
Byte Reorder Function Enable Control\nNote: Byte reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
19
1
read-write
0
Byte reorder function Disabled
#0
1
Byte reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4])
#1
RXNEG
Receive on Negative Edge\n
1
1
read-write
0
Received data input signal is latched on the rising edge of SPICLK
#0
1
Received data input signal is latched on the falling edge of SPICLK
#1
SLAVE
Slave Mode Enable Control\n
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SPIEN
SPI Transfer Control Enable Bit\nNote1: In Master mode, the transfer will start when there is data in the FIFO buffer after this is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1. \nNote2: The byte reorder function is not supported when the Quad or Dual I/O mode is enabled.
0
1
read-write
0
Transfer control bit Disabled
#0
1
Transfer control bit Enabled
#1
SUSPITV
Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0]+0.5) * period of SPICLK clock cycle\nExample:\n
4
4
read-write
TXNEG
Transmit on Negative Edge\n
2
1
read-write
0
Transmitted data output signal is changed on the rising edge of SPICLK
#0
1
Transmitted data output signal is changed on the falling edge of SPICLK
#1
UNITIEN
Unit Transfer Interrupt Enable Control\n
17
1
read-write
0
SPI unit transfer interrupt Disabled
#0
1
SPI unit transfer interrupt Enabled
#1
SPI_FIFOCTL
SPI_FIFOCTL
SPI FIFO Control Register
0x10
-1
read-write
n
0x0
0x0
RXFBCLR
Clear Receive FIFO\n Note: Auto cleared by Hardware.
8
1
read-write
0
No effect
#0
1
Clear receive FIFO only
#1
RXOVIEN
Receive FIFO Overrun Interrupt Enable Control\n
5
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RXRST
Clear Receive FIFO Control\nNote: If there is slave receive time-out event, the RXRST will be set 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
0
1
read-write
0
No effect
#0
1
Clear receive FIFO control. The RXFULL (SPI_STATUS[9]) will be cleared to 0 and the RXEMPTY (SPI_STATUS[8]) will be set to 1. This bit will be cleared to 0 by hardware about 3 system clocks+3 SPI engine clock after it is set to 1
#1
RXTH
Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF (SPI_STATUS[10]) will be set to 1, else the RXTHIF (SPI_STATUS[10]) will be cleared to 0.
24
3
read-write
RXTHIEN
Receive FIFO Threshold Interrupt Enable Control\n
2
1
read-write
0
RX FIFO threshold interrupt Disabled
#0
1
RX FIFO threshold interrupt Enabled
#1
RXTOIEN
Slave Receive Time-out Interrupt Enable Control\n
4
1
read-write
0
Receive time-out interrupt Disabled
#0
1
Receive time-out interrupt Enabled
#1
TXFBCLR
Clear Transmit FIFO\n Note: Auto cleared by Hardware.
9
1
read-write
0
No effect
#0
1
Clear transmit FIFO only
#1
TXRST
Clear Transmit FIFO Control\nNote: If there is slave receive time-out event, the TXRST will be set 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
1
1
read-write
0
No effect
#0
1
Clear transmit FIFO control. The TXFULL (SPI_STATUS[17]) will be cleared to 0 and the TXEMPTY (SPI_STATUS[16]) will be set to 1. This bit will be cleared to 0 by hardware about 3 system clocks+3 SPI engine clock after it is set to 1
#1
TXTH
Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF (SPI_STATUS[18]) will be set to 1, else the TXTHIF (SPI_STATUS[18]) will be cleared to 0.
28
3
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable Control\n
3
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
TXUFIEN
Slave Transmit Under Run Interrupt Enable Control\n
7
1
read-write
0
Slave Transmit FIFO under-run interrupt Disabled
#0
1
Slave Transmit FIFO under-run interrupt Enabled
#1
TXUFPOL
Transmit Under-run Data Out\nNote1: The under run event is active after the serial clock input and the hardware synchronous, so that the first 1~3 bit (depending on the relation between system clock and the engine clock) data out will be the last transaction data.\nNote2: If the frequency of system clock approach to engine clock, they may need 3-bit time to report the transmit under-run data out.
6
1
read-write
0
The SPI data out is keep 0 if there is transmit under-run event in Slave mode
#0
1
The SPI data out is keep 1 if there is transmit under-run event in Slave mode
#1
SPI_RX
SPI_RX
SPI Data Receive Register
0x30
read-only
n
0x0
0x0
RX
Data Receive Register\nThere is 8-level FIFO buffer in this controller. The data receive register holds the earliest datum received from SPI data input pin. If the RXEMPTY (SPI_STATUS[8]) is not set to 1, the receive FIFO buffer can be accessed through software by reading this register. This is a read-only register.
0
32
read-only
SPI_SSCTL
SPI_SSCTL
SPI Slave Select Control Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select Function Enable (Master Only)\n
3
1
read-write
0
If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bit of SPI_SSCTL[0]
#0
1
If this bit is set, SS signal will be generated automatically. It means that device/slave select signal, which is set in SPI_SSCTL[0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
#1
SLV3WIRE
Slave 3-wire Mode Enable Control\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI.\n
4
1
read-write
0
2-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLVBEIEN
Slave Mode Error 0 Interrupt Enable Control\n
8
1
read-write
0
Slave mode error 0 interrupt Disable
#0
1
Slave mode error 0 interrupt Enable
#1
SLVTOCNT
Slave Mode Time-out Period \nIn Slave mode, these bits indicate the time-out period when there is serial clock input during slave select active. The clock source of the time-out counter is Slave engine clock. If the value is 0, it indicates the slave mode time-out function is disabled.
16
16
read-write
SLVTOIEN
Slave Mode Time-out Interrupt Enable Control\n
5
1
read-write
0
Slave mode time-out interrupt Disabled
#0
1
Slave mode time-out interrupt Enabled
#1
SLVTORST
Slave Mode Time-out FIFO Clear\nNote: Both the FIFO clear function, TX_CLK and RXRST, active automatically when there is a slave mode time-out event.
6
1
read-write
0
Slave mode Time-out FIFO Clear Disable
#0
1
Slave mode Time-out FIFO Clear Enable
#1
SLVURIEN
Slave Mode Error 1 Interrupt Enable Control\n
9
1
read-write
0
Slave mode error 1 interrupt Disable
#0
1
Slave mode error 1 interrupt Enable
#1
SS
Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0,\n
0
1
read-write
0
set the SPIn_SS line to inactive state.\nKeep the SPIn_SS line at inactive state
#0
1
set the SPIn_SS line to active state.\nSPIn_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIn_SS is specified in SSACTPOL (SPI_SSCTL[2])
#1
SSACTIEN
Slave Select Active Interrupt Enable Control\n
12
1
read-write
0
Slave select active interrupt Disable
#0
1
Slave select active interrupt Enable
#1
SSACTPOL
Slave Select Active Level\nThis bit defines the active status of slave select signal (SS).\n
2
1
read-write
0
The slave select signal SS is active on low-level
#0
1
The slave select signal SS is active on high-level
#1
SSINAIEN
Slave Select Inactive Interrupt Enable Control\n
13
1
read-write
0
Slave select inactive interrupt Disable
#0
1
Slave select inactive interrupt Enable
#1
SPI_STATUS
SPI_STATUS
SPI Status Register
0x14
-1
read-write
n
0x0
0x0
BUSY
SPI Unit Bus Status (Read Only)\n
0
1
read-only
0
No transaction in the SPI bus
#0
1
SPI controller unit in busy state
#1
RXCNT
Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
24
4
read-only
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\n
8
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RXFULL
Receive FIFO Buffer Empty Indicator (Read Only)\n
9
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RXOVIF
Receive FIFO Overrun Status\nNote: This bit will be cleared by writing 1 to itself.
11
1
read-write
0
No receiver FIFO overrun status
#0
1
Receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1
#1
RXTHIF
Receive FIFO Threshold Interrupt Status (Read Only)\n
10
1
read-only
0
The valid data count within the RX FIFO buffer is smaller than or equal to the setting value of RXTH (SPI_FIFOCTL[26:24])
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RXTH (SPI_FIFOCTL[26:24])
#1
RXTOIF
Receive Time-out Interrupt Status\nNote: This bit will be cleared by writing 1 to itself.
12
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI engine clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
SLVBEIF
Slave Mode Error 0 Interrupt Status (Read Only)\nIn Slave mode, there is bit counter mismatch with DWIDTH (SPI_CTL[12:8]) when the slave select line goes to inactive state.\nNote: If the slave select active but there is no any serial clock input, the SLVBEIF (SPI_STATUS[6]) also active when the slave select goes to inactive state.
6
1
read-only
0
No Slave mode error 0 event
#0
1
Slave mode error 0 occurs
#1
SLVTOIF
Slave Time-out Interrupt Status (Read Only)\nWhen the Slave Select is active and the value of SLVTOCNT (SPI_SSCTL[31:16]) is not 0 and the serial clock input, the slave time-out counter in SPI controller logic will be start. When the value of time-out counter greater or equal than the value of SLVTOCNT (SPI_SSCTL[31:16]) during before one transaction done, the slave time-out interrupt event will active.\nNote: If the DWIDTH (SPI_CTL[12:8]) is set 0x10, one transaction is equal 16 bits serial clock period.
5
1
read-only
0
Slave time-out is not active
#0
1
Slave time-out is active
#1
SLVURIF
Slave Mode Error 1 Interrupt Status (Read Only)\nIn Slave mode, transmit under-run occurs when the slave select line goes to inactive state.\n
7
1
read-only
0
No Slave mode error 1 event
#0
1
Slave mode error 1 occurs
#1
SPIENSTS
SPI Enable Bit Status (Read Only)\nThe clock source of SPI controller logic is engine clock, it is asynchronous with the system clock. In order to make sure the function is disabled in SPI controller logic, this bit indicates the real status of SPIEN (SPI_CTL[0]) in SPI controller logic for user.
15
1
read-only
0
Indicate the transmit control bit is disabled
#0
1
Indicate the transfer control bit is active
#1
SSACTIF
Slave Select Active Interrupt Status\nNote: This bit will be cleared by writing 1 to itself.
2
1
read-write
0
Slave select active interrupt is cleared or did not occur
#0
1
Slave select active interrupt event has occurred
#1
SSINAIF
Slave Select Inactive Interrupt Status\nNote: This bit will be cleared by writing 1 to itself.
3
1
read-write
0
Slave select inactive interrupt is cleared or did not occur
#0
1
Slave select inactive interrupt event has occurred
#1
SSLINE
Slave Select Line Bus Status (Read Only)\nNote: If SSACTPOL (SPI_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
4
1
read-only
0
Indicates the slave select line bus status is 0
#0
1
Indicates the slave select line bus status is 1
#1
TXCNT
Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\n
16
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TXFULL
Transmit FIFO Buffer Full Indicator (Read Only)\n
17
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TXRXRST
FIFO CLR Status (Read Only)\nNote: Both the TXRST (SPI_FIFOCTL[1]), RXRST (SPI_FIFOCTL[0]), need 3 system clock+3 engine clock , the status of this bit support the user to monitor the clear function is doing or done.
23
1
read-only
0
Done the FIFO buffer clear function of TXRST (SPI_FIFOCTL[1]) or RXRST (SPI_FIFOCTL[0])
#0
1
Doing the FIFO buffer clear function of TXRST (SPI_FIFOCTL[1])or RXRST (SPI_FIFOCTL[0])
#1
TXTHIF
Transmit FIFO Threshold Interrupt Status (Read Only)\n
18
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH (SPI_FIFOCTL[30:28])
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH (SPI_FIFOCTL[30:28])
#1
TXUFIF
TX Underflow Interrupt Flag\nWhen the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 3 system clock cycles + 2 peripheral clock cycles since the reset operation is done.
19
1
read-write
0
No effect
#0
1
No data in Transmit FIFO and TX shift register when the slave selection signal is active
#1
UNITIF
Unit Transfer Interrupt Status\nNote: This bit will be cleared by writing 1 to itself.
1
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
SPI_TX
SPI_TX
SPI Data Transmit Register
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffer. The number of valid bits depends on the setting of transmit bit width field of the SPI_CTL register.\nFor example, if DWIDTH (SPI_CTL[12:8]) is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH (SPI_CTL[12:8]) is set to 0x00, the SPI controller will perform a 32-bit transfer.
0
32
write-only
SPIM
SPIM Register Map
SPIM
0x0
0x0
0x3C
registers
n
CTL0
SPIM_CTL0
Control and Status Register 0
0x0
-1
read-write
n
0x0
0x0
B4ADDREN
4-byte Address Mode Enable Control\nNote: Used for DMA Write/DMA Read/DMM mode.
5
1
read-write
0
4-byte address mode Disabled
#0
1
4-byte address mode Enabled
#1
BALEN
Balance the AHB Control Time Between Cipher Enable and Disable Control\nWhen cipher is enabled, the AHB control signal will delay some time caused by the encoding or decoding calculation. Therefore, if set BALEN to 1, it will make the AHB signal processing time with cipher disabled be equal to that with cipher enabled.\nNote: Only useful when cipher is disabled.
2
1
read-write
BITMODE
SPI Interface Bit Mode\nNote: Only used for I/O mode.
20
2
read-write
0
Standard mode
#00
1
Dual mode
#01
2
Quad mode
#10
3
Reserved
#11
BURSTNUM
Transmit/Receive Burst Number\nThis field specifies how many transmit/receive transactions should be executed continuously in one transfer.\nNote: Only used for I/O Mode.
13
2
read-write
0
Only one transmit/receive transaction will be executed in one transfer
#00
1
Two successive transmit/receive transactions will be executed in one transfer
#01
2
Three successive transmit/receive transactions will be executed in one transfer
#10
3
Four successive transmit/receive transactions will be executed in one transfer
#11
CIPHOFF
Cipher Disable Control\nNote1: Cipher function only can be disabled. If user wants to enable cipher function after disabled processing, the chip must be reset again.\nNote2: If there is not any key in the chip, the cipher will be disabled automatically.\nNote3: In ICE mode, the cipher will be disabled automatically.
0
1
read-write
0
Cipher function Enabled
#0
1
Cipher function Disabled
#1
CMDCODE
Page Program Command Code\nNote1: Quad mode of SPI Flash must be enabled first by I/O mode before using quad page program/quad read commands.\nNote2: See support list for SPI Flash which support these command codes.\nNote3: For TYPE_1, TYPE_2, and TYPE_3 program flows, refer to Figure 6.133, Figure 6.134, and Figure 6.135.
24
8
read-write
2
Page program (Used for DMA Write mode)
0x02
3
Standard read (Used for DMA Read/DMM mode)
0x03
11
Fast read (Used for DMA Read/DMM mode)
0x0b
50
Quad page program with TYPE_1 program flow (Used for DMA Write mode)
0x32
56
Quad page program with TYPE_2 program flow (Used for DMA Write mode)
0x38
59
Fast dual read (Used for DMA Read/DMM mode)
0x3b
64
Quad page program with TYPE_3 program flow (Used for DMA Write mode)
0x40
235
Quad read (Used for DMA Read/DMM mode)
0xeb
DWIDTH
Transmit/Receive Bit Length\nThis field specifies how many bits are transmitted/received in one transmit/receive transaction.\nNote1: Only used for I/O mode.\nNote2: Only 8-, 16-, 24-, and 32-bit are allowed. Other bit length will result in incorrect transfer.
8
5
read-write
23
24 bits
0x17
31
32 bits
0x1f
7
8 bits
0x7
15
16 bits
0xf
IEN
Interrupt Enable Control\n
6
1
read-write
0
SPIM Interrupt Disabled
#0
1
SPIM Interrupt Enabled
#1
IF
Interrupt Flag\nWrite Operation:\n
7
1
read-write
0
No effect.\nThe transfer has not finished yet
#0
1
Write 1 to clear.\nThe transfer has done
#1
OPMODE
SPI Function Operation Mode\nNote: In DMA Write mode, hardware will send just one page program command per operation. Users must take care of cross-page cases.
22
2
read-write
0
I/O mode
#00
1
DMA Write mode
#01
2
DMA Read mode
#10
3
Direct Memory Map (DMM) mode (Default)
#11
QDIODIR
SPI Interface Direction Select for Quad/Dual Mode\nNote: Only used for I/O mode.
15
1
read-write
0
Interface signals are input
#0
1
Interface signals are output
#1
SUSPITV
Suspend Interval\nNote: Only used for I/O mode.
16
4
read-write
0
2 SCLK clock cycles
0x0
1
3 SCLK clock cycles
0x1
14
16 SCLK clock cycles
0xe
15
17 SCLK clock cycles
0xf
CTL1
SPIM_CTL1
Control Register 1
0x4
-1
read-write
n
0x0
0x0
DIVIDER
Clock Divider Register\nThe value in this field is the frequency divider of the system clock to generate the serial clock on the output SPIM_CLK pin. The desired frequency is obtained according to the following equation:\n\nNote: When set DIVIDER to zero, the frequency of SPIM_CLK will be equal to the frequency of SYS_CLK.
16
16
read-write
IDLECNT
Idle Interval\nIn DMM mode, IDLECNT is set to control the minimum idle time between two SPI Flash accesses. \nNote: Only used for DMM mode.
8
4
read-write
IFSEL
Device/Slave Interface Select\nNote: MCP and MCP64 only can be referenced by MCP SPI Flash pad location.
6
2
read-write
0
SPI Interface from GPIO
#00
1
SPI Interface from MCP
#01
2
SPI Interface from MCP64
#10
3
Reserved
#11
SPIMEN
Go and Busy Status\nWrite Operation:\nNote: All registers should be set before writing 1 to the SPIMEN bit. When a transfer is in progress, you should not write to any register of this peripheral.
0
1
read-write
0
No effect.\nThe transfer has done
#0
1
Start the transfer. This bit remains set during the transfer and is automatically cleared after transfer finished.\nThe transfer has not finished yet
#1
SS
Slave Select Active Enable Control\nNote: This interface can only drive one device/slave at a given time. Therefore, the slave selects of the selected device must be set to its active level before starting any read or write transfer.
4
1
read-write
0
SPIM_SS is in active level
#0
1
SPIM_SS is in inactive level
#1
SSACTPOL
Slave Select Active Level\nIt defines the active level of device/slave select signal (SPIM_SS).\n
5
1
read-write
0
The SPIM_SS slave select signal is Active Low
#0
1
The SPIM_SS slave select signal is Active High
#1
DMATBCNT
SPIM_DMATBCNT
DMA Transfer Byte Count Register
0x34
read-write
n
0x0
0x0
CNT
DMA Transfer Byte Count Register\nIt indicates the transfer length for DMA process. \nNote: The unit for counting is byte.\nNote2: The number must be the multiple of 4.
0
24
read-write
FADDR
SPIM_FADDR
SPI Flash Address Register
0x38
read-write
n
0x0
0x0
ADDR
SPI Flash Address Register\nFor DMA Read mode, this is the source address for DMA transfer.\nFor DMA Write mode, this is the destination address for DMA transfer.\nNote: This address must be word-aligned.
0
32
read-write
RX0
SPIM_RX0
Data Receive Register 0
0x10
read-only
n
0x0
0x0
RX
Data Receive Register
The Data Receive Registers hold the received data of the last executed transfer.
Number of valid RX registers is specified in SPIM_CTL0[BURSTNUM]. If BURSTNUM 0, received data are held in the most significant RX register first.
Number of valid-bit is specified in SPIM_CTL0[DWIDTH]. If DWIDTH is 16, 24, or 32, received data are held in the least significant byte of RX register first.
In a byte, received data are held in the most significant bit of RX register first.
0
32
read-only
RX1
SPIM_RX1
Data Receive Register 1
0x14
read-write
n
0x0
0x0
RX2
SPIM_RX2
Data Receive Register 2
0x18
read-write
n
0x0
0x0
RX3
SPIM_RX3
Data Receive Register 3
0x1C
read-write
n
0x0
0x0
RXCLKDLY
SPIM_RXCLKDLY
Rx Clock Delay Control Register
0xC
read-write
n
0x0
0x0
DLYSEL
Rx Sample Clock Source Delay Chain Select\n
29
3
read-write
0
Not Delay
#000
1
Select sample clock through 2 Delay Cell
#001
2
Select sample clock through 4 Delay Cell
#010
3
Select sample clock through 6 Delay Cell
#011
7
Select sample clock through 14 Delay Cell
#111
SRAMADDR
SPIM_SRAMADDR
SRAM Memory Address Register
0x30
read-write
n
0x0
0x0
ADDR
SRAM Memory Address\nFor DMA Read mode, this is the destination address for DMA transfer.\nFor DMA Write mode, this is the source address for DMA transfer.\nNote: This address must be word-aligned.
0
32
read-write
TX0
SPIM_TX0
Data Transmit Register 0
0x20
read-write
n
0x0
0x0
TX
Data Transmit Register
The Data Transmit Registers hold the data to be transmitted in next transfer.
Number of valid TX registers is specified in SPIM_CTL0[BURSTNUM]. If BURSTNUM 0, data are transmitted in the most significant TX register first.
Number of valid-bit is specified in SPIM_CTL0[DWIDTH]. If DWIDTH is 16, 24, or 32, data are transmitted in the least significant byte of TX register first.
In a byte, data are transmitted in the most significant bit of TX register first.
0
32
read-write
TX1
SPIM_TX1
Data Transmit Register 1
0x24
read-write
n
0x0
0x0
TX2
SPIM_TX2
Data Transmit Register 2
0x28
read-write
n
0x0
0x0
TX3
SPIM_TX3
Data Transmit Register 3
0x2C
read-write
n
0x0
0x0
VALIDCTL
SPIM_VALIDCTL
Validation Check Register
0x8
read-write
n
0x0
0x0
VALIDEN
Validation Enable Bit\nSetting this bit to enable the validation function. The function can check whether the code in SPI Flash is valid or not.\n
16
1
read-write
0
1 (Rising Edge) = Enable the validation and clear the VALIDSTS bit
#0
1
0 (Falling Edge) = Disable the validation and update the VALIDSTS bit
#1
VALIDSTS
Validation Status Bit\nThis bit will be updated when the VALIDEN bit changes.\nNote: Write 0 to clear it to 0.
0
1
read-write
0
Code in SPI Flash is not valid
#0
1
Code in SPI Flash is valid
#1
TIMER01
TIMER Register Map
TIMER
0x0
0x0
0x1C
registers
n
0x20
0x1C
registers
n
TIMER0_CAP
TIMER0_CAP
Timer0 Capture Data Register
0x10
read-only
n
0x0
0x0
CAPDAT
Timer Capture Data Register\nWhen the CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will be set to 1 and the current timer counter value (TIMERx_CNT value) will be auto-loaded into the CAPDAT field.
0
24
read-only
TIMER0_CMP
TIMER0_CMP
Timer0 Compare Register
0x4
read-write
n
0x0
0x0
CMPDAT
Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] timer interrupt flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in the CMPDAT field, or the timer will run into unknown state.\nNote2: When timer is operating in Continuous Counting mode, the 24-bit up counter will keep counting continuously even if software writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting and using the newest CMPDAT value to be the timer compared value if software writes a new value to the CMPDAT field.
0
24
read-write
TIMER0_CNT
TIMER0_CNT
Timer0 Data Register
0xC
read-only
n
0x0
0x0
CNT
Timer Data Register\nNote: User can read CNT for getting the current 24- bit event counter value if TIMERx_CTL[24] is 1
0
24
read-only
TIMER0_CTL
TIMER0_CTL
Timer0 Control and Status Register
0x0
-1
read-write
n
0x0
0x0
ACTSTS
Timer Active Status Control (Read Only)\nThis bit indicates the 24-bit up counter status.\n
25
1
read-only
0
24-bit up counter is not active
#0
1
24-bit up counter is active
#1
CNTDATEN
Data Load Enable Control\nWhen this bit is set, timer counter value (TIMERx_CNT) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n
16
1
read-write
0
Timer Data Register update Disabled
#0
1
Timer Data Register update Enabled while timer counter is active
#1
CNTEN
Timer Enable Control\n
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
EXTCNTEN
Counter Mode Enable Control\nThis bit is for external counting pin function to be enabled. When timer is used as an event counter, this bit should be set to 1 and HXT selected as timer clock source.\n
24
1
read-write
0
External counter mode Disabled
#0
1
External counter mode Enabled
#1
ICEDEBUG
ICE Debug Mode Acknowledge Disable Control\nTimer counter will keep going no matter CPU is held by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
Interrupt Enable Control\nNote: If this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
29
1
read-write
0
Timer Interrupt Disabled
#0
1
Timer Interrupt Enabled
#1
OPMODE
Timer Operation Mode\n
27
2
read-write
0
Timer controller is operated in One-shot mode
#00
1
Timer controller is operated in Periodic mode
#01
2
Timer controller is operated in Toggle-output mode
#10
3
Timer controller is operated in Continuous Counting mode
#11
PSC
PSC Counter\n
0
8
read-write
RSTCNT
Timer Reset Control\nSetting this bit will reset the 24-bit up counter value (TIMERx_CNT) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\n
26
1
read-write
0
No effect
#0
1
Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit
#1
WKEN
Wake-up Enable Control\nIf this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.\n
23
1
read-write
0
Wake-up trigger event Disabled if timer interrupt signal generated
#0
1
Wake-up trigger event Enabled if timer interrupt signal generated
#1
TIMER0_EINTSTS
TIMER0_EINTSTS
Timer0 External Interrupt Status Register
0x18
read-write
n
0x0
0x0
CAPIF
Timer External Interrupt Flag\nThis bit indicates the timer external interrupt flag status.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
TMx_EXT (x= 0~3) pin interrupt did not occur
#0
1
TMx_EXT (x= 0~3) pin interrupt occurred
#1
TIMER0_EXTCTL
TIMER0_EXTCTL
Timer0 External Control Register
0x14
read-write
n
0x0
0x0
CAPDBEN
Timer External Capture Pin De-bounce Enable Control\nNote: If this bit is enabled, the edge detection of TMx_EXT pin is detected with de-bounce circuit.
6
1
read-write
0
TMx_EXT (x= 0~3) pin de-bounce Disabled
#0
1
TMx_EXT (x= 0~3) pin de-bounce Enabled
#1
CAPEDGE
Timer External Pin Edge Detect\n
1
2
read-write
0
A 1 to 0 transition on TMx_EXT (x= 0~3) pin will be detected
#00
1
A 0 to 1 transition on TMx_EXT (x= 0~3) pin will be detected
#01
2
Either 1 to 0 or 0 to 1 transition on TMx_EXT (x= 0~3) pin will be detected
#10
3
Reserved
#11
CAPEN
Timer External Pin Enable Control\nThis bit enables the CAPFUNCS (TIMERx_EXTCTL[4]) function on the TMx_EXT pin. \n
3
1
read-write
0
CAPFUNCS function of TMx_EXT (x= 0~3) pin will be ignored
#0
1
CAPFUNCS function of TMx_EXT (x= 0~3) pin is active
#1
CAPFUNCS
Timer External Reset Counter / Capture Mode Select\n
4
1
read-write
0
Transition on TMx_EXT (x= 0~3) pin is using to save the 24-bit timer counter value
#0
1
Transition on TMx_EXT (x= 0~3) pin is using to reset the 24-bit timer counter value
#1
CAPIEN
Timer External Interrupt Enable Control\n
5
1
read-write
0
TMx_EXT (x= 0~3) pin detection Interrupt Disabled
#0
1
TMx_EXT (x= 0~3) pin detection Interrupt Enabled
#1
CNTDBEN
Timer Counter Pin De-bounce Enable Control\nNote: If this bit is enabled, the edge detection of TMx_CNT_OUT pin is detected with de-bounce circuit.
7
1
read-write
0
TMx_CNT_OUT (x= 0~3) pin de-bounce Disabled
#0
1
TMx_CNT_OUT (x= 0~3) pin de-bounce Enabled
#1
CNTPHASE
Timer External Count Phase \nThis bit indicates the detection phase of external counting pin.\n
0
1
read-write
0
A falling edge of external counting pin will be counted
#0
1
A rising edge of external counting pin will be counted
#1
TIMER0_INTSTS
TIMER0_INTSTS
Timer0 Interrupt Status Register
0x8
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TIMERx_CNT value reaches to CMPDAT value.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
TIMERx_CNT value matches the CMPDAT value
#1
TWKF
Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it.
1
1
read-write
0
Timer does not cause CPU wake-up
#0
1
CPU wake-up from Power-down mode and Deep Power-down mode, if timer time-out interrupt signal generated
#1
TIMER1_CAP
TIMER1_CAP
Timer1 Capture Data Register
0x30
read-write
n
0x0
0x0
TIMER1_CMP
TIMER1_CMP
Timer1 Compare Register
0x24
read-write
n
0x0
0x0
TIMER1_CNT
TIMER1_CNT
Timer1 Data Register
0x2C
read-write
n
0x0
0x0
TIMER1_CTL
TIMER1_CTL
Timer1 Control and Status Register
0x20
read-write
n
0x0
0x0
TIMER1_EINTSTS
TIMER1_EINTSTS
Timer1 External Interrupt Status Register
0x38
read-write
n
0x0
0x0
TIMER1_EXTCTL
TIMER1_EXTCTL
Timer1 External Control Register
0x34
read-write
n
0x0
0x0
TIMER1_INTSTS
TIMER1_INTSTS
Timer1 Interrupt Status Register
0x28
read-write
n
0x0
0x0
TIMER23
TIMER Register Map
TIMER
0x0
0x0
0x1C
registers
n
0x20
0x1C
registers
n
TIMER2_CAP
TIMER2_CAP
Timer2 Capture Data Register
0x10
read-only
n
0x0
0x0
CAPDAT
Timer Capture Data Register\nWhen the CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will be set to 1 and the current timer counter value (TIMERx_CNT value) will be auto-loaded into the CAPDAT field.
0
24
read-only
TIMER2_CMP
TIMER2_CMP
Timer2 Compare Register
0x4
read-write
n
0x0
0x0
CMPDAT
Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] timer interrupt flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in the CMPDAT field, or the timer will run into unknown state.\nNote2: When timer is operating in Continuous Counting mode, the 24-bit up counter will keep counting continuously even if software writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting and using the newest CMPDAT value to be the timer compared value if software writes a new value to the CMPDAT field.
0
24
read-write
TIMER2_CNT
TIMER2_CNT
Timer2 Data Register
0xC
read-only
n
0x0
0x0
CNT
Timer Data Register\nNote: User can read CNT for getting the current 24- bit event counter value if TIMERx_CTL[24] is 1
0
24
read-only
TIMER2_CTL
TIMER2_CTL
Timer2 Control and Status Register
0x0
-1
read-write
n
0x0
0x0
ACTSTS
Timer Active Status Control (Read Only)\nThis bit indicates the 24-bit up counter status.\n
25
1
read-only
0
24-bit up counter is not active
#0
1
24-bit up counter is active
#1
CNTDATEN
Data Load Enable Control\nWhen this bit is set, timer counter value (TIMERx_CNT) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n
16
1
read-write
0
Timer Data Register update Disabled
#0
1
Timer Data Register update Enabled while timer counter is active
#1
CNTEN
Timer Enable Control\n
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
EXTCNTEN
Counter Mode Enable Control\nThis bit is for external counting pin function to be enabled. When timer is used as an event counter, this bit should be set to 1 and HXT selected as timer clock source.\n
24
1
read-write
0
External counter mode Disabled
#0
1
External counter mode Enabled
#1
ICEDEBUG
ICE Debug Mode Acknowledge Disable Control\nTimer counter will keep going no matter CPU is held by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
Interrupt Enable Control\nNote: If this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
29
1
read-write
0
Timer Interrupt Disabled
#0
1
Timer Interrupt Enabled
#1
OPMODE
Timer Operation Mode\n
27
2
read-write
0
Timer controller is operated in One-shot mode
#00
1
Timer controller is operated in Periodic mode
#01
2
Timer controller is operated in Toggle-output mode
#10
3
Timer controller is operated in Continuous Counting mode
#11
PSC
PSC Counter\n
0
8
read-write
RSTCNT
Timer Reset Control\nSetting this bit will reset the 24-bit up counter value (TIMERx_CNT) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\n
26
1
read-write
0
No effect
#0
1
Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit
#1
WKEN
Wake-up Enable Control\nIf this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.\n
23
1
read-write
0
Wake-up trigger event Disabled if timer interrupt signal generated
#0
1
Wake-up trigger event Enabled if timer interrupt signal generated
#1
TIMER2_EINTSTS
TIMER2_EINTSTS
Timer2 External Interrupt Status Register
0x18
read-write
n
0x0
0x0
CAPIF
Timer External Interrupt Flag\nThis bit indicates the timer external interrupt flag status.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
TMx_EXT (x= 0~3) pin interrupt did not occur
#0
1
TMx_EXT (x= 0~3) pin interrupt occurred
#1
TIMER2_EXTCTL
TIMER2_EXTCTL
Timer2 External Control Register
0x14
read-write
n
0x0
0x0
CAPDBEN
Timer External Capture Pin De-bounce Enable Control\nNote: If this bit is enabled, the edge detection of TMx_EXT pin is detected with de-bounce circuit.
6
1
read-write
0
TMx_EXT (x= 0~3) pin de-bounce Disabled
#0
1
TMx_EXT (x= 0~3) pin de-bounce Enabled
#1
CAPEDGE
Timer External Pin Edge Detect\n
1
2
read-write
0
A 1 to 0 transition on TMx_EXT (x= 0~3) pin will be detected
#00
1
A 0 to 1 transition on TMx_EXT (x= 0~3) pin will be detected
#01
2
Either 1 to 0 or 0 to 1 transition on TMx_EXT (x= 0~3) pin will be detected
#10
3
Reserved
#11
CAPEN
Timer External Pin Enable Control\nThis bit enables the CAPFUNCS (TIMERx_EXTCTL[4]) function on the TMx_EXT pin. \n
3
1
read-write
0
CAPFUNCS function of TMx_EXT (x= 0~3) pin will be ignored
#0
1
CAPFUNCS function of TMx_EXT (x= 0~3) pin is active
#1
CAPFUNCS
Timer External Reset Counter / Capture Mode Select\n
4
1
read-write
0
Transition on TMx_EXT (x= 0~3) pin is using to save the 24-bit timer counter value
#0
1
Transition on TMx_EXT (x= 0~3) pin is using to reset the 24-bit timer counter value
#1
CAPIEN
Timer External Interrupt Enable Control\n
5
1
read-write
0
TMx_EXT (x= 0~3) pin detection Interrupt Disabled
#0
1
TMx_EXT (x= 0~3) pin detection Interrupt Enabled
#1
CNTDBEN
Timer Counter Pin De-bounce Enable Control\nNote: If this bit is enabled, the edge detection of TMx_CNT_OUT pin is detected with de-bounce circuit.
7
1
read-write
0
TMx_CNT_OUT (x= 0~3) pin de-bounce Disabled
#0
1
TMx_CNT_OUT (x= 0~3) pin de-bounce Enabled
#1
CNTPHASE
Timer External Count Phase \nThis bit indicates the detection phase of external counting pin.\n
0
1
read-write
0
A falling edge of external counting pin will be counted
#0
1
A rising edge of external counting pin will be counted
#1
TIMER2_INTSTS
TIMER2_INTSTS
Timer2 Interrupt Status Register
0x8
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TIMERx_CNT value reaches to CMPDAT value.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
TIMERx_CNT value matches the CMPDAT value
#1
TWKF
Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it.
1
1
read-write
0
Timer does not cause CPU wake-up
#0
1
CPU wake-up from Power-down mode and Deep Power-down mode, if timer time-out interrupt signal generated
#1
TIMER3_CAP
TIMER3_CAP
Timer3 Capture Data Register
0x30
read-write
n
0x0
0x0
TIMER3_CMP
TIMER3_CMP
Timer3 Compare Register
0x24
read-write
n
0x0
0x0
TIMER3_CNT
TIMER3_CNT
Timer3 Data Register
0x2C
read-write
n
0x0
0x0
TIMER3_CTL
TIMER3_CTL
Timer3 Control and Status Register
0x20
read-write
n
0x0
0x0
TIMER3_EINTSTS
TIMER3_EINTSTS
Timer3 External Interrupt Status Register
0x38
read-write
n
0x0
0x0
TIMER3_EXTCTL
TIMER3_EXTCTL
Timer3 External Control Register
0x34
read-write
n
0x0
0x0
TIMER3_INTSTS
TIMER3_INTSTS
Timer3 Interrupt Status Register
0x28
read-write
n
0x0
0x0
UART0
UART Register Map
UART
0x0
0x0
0x3C
registers
n
UART_ALTCTL
UART_ALTCTL
UART Alternate Control/Status Register
0x2C
-1
read-write
n
0x0
0x0
ABRDBITS
Auto-baud Rate Detect Bit Length \nNote: The calculation of bit number includes the START bit.
19
2
read-write
0
1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01
#00
1
2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02
#01
2
4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08
#10
3
8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80
#11
ABRDEN
Auto-baud Rate Detect Enable Control\nNote: This bit is cleared automatically after auto-baud detection is finished.
18
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
ABRIF
Auto-baud Rate Interrupt Flag (Read Only)
This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated.
Note: This bit is read only, but it can be cleared by writing 1 to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).
17
1
read-only
ADDRDEN
RS-485 Address Detection Enable Control\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value \nThis field contains the RS-485 address match values.\n This field is used for RS-485 auto address detection mode.
24
8
read-write
BRKFL
UART LIN Break Field Length (Only Available in UART1/UART2 Channel)\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1\n
0
4
read-write
LINRXEN
LIN RX Enable Control (Only Available in UART1/UART2 Channel)\n
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LINTXEN
LIN TX Break Mode Enable Control (Only Available in UART1/UART2 Channel)\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
LIN TX Break mode Disabled
#0
1
LIN TX Break mode Enabled
#1
RS485AAD
RS-485 Auto Address Detection Operation Mode (AAD)\n It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485AUD
RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation function (AUD) Disabled
#0
1
RS-485 Auto Direction Operation function (AUD) Enabled
#1
RS485NMM
RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UART Baud Rate Divisor Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.102.
28
1
read-write
BAUDM1
BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.102.\n In IrDA mode must be operated in mode 0.
29
1
read-write
BRD
Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.102.
0
16
read-write
EDIVM1
Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.102.
24
4
read-write
UART_DAT
UART_DAT
UART Receive/Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Receiving/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD. \nRead Operation:\nBy reading this register, the UART will return an 8-bit data received from receiving FIFO.
0
8
read-write
UART_FIFO
UART_FIFO
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).\n
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
4
RX FIFO Interrupt Trigger Level is 30/14 (64 FIFO/16 FIFO)
#0100
5
RX FIFO Interrupt Trigger Level is 46/14 (64 FIFO/16 FIFO)
#0101
6
RX FIFO Interrupt Trigger Level is 62/14 (64 FIFO/16 FIFO)
#0110
RTSTRGLV
nRTS Trigger Level for Auto-flow Control Use\nNote: This field is used for automatic nRTS flow control.
16
4
read-write
0
nRTS Trigger Level is 1 bytes
#0000
1
nRTS Trigger Level is 4bytes
#0001
2
nRTS Trigger Level is 8 bytes
#0010
3
nRTS Trigger Level is 14 bytes
#0011
4
nRTS Trigger Level is 30/14 (64 FIFO/16 FIFO)
#0100
5
nRTS Trigger Level is 46/14 (64 FIFO/16 FIFO)
#0101
6
nRTS Trigger Level is 62/14 (64 FIFO/16 FIFO)
#0110
RXOFF
Receiver Disable Control\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset Control\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset Control\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ABRDIF
Auto-baud Rate Detect Interrupt (Read Only)
Note1: This bit is set to logic 1 when auto-baud rate detect function is finished.
Note2: This bit is read only, but can be cleared by writing 1 to it.
1
1
read-only
0
Auto-baud rate detect function is not finished
#0
1
Auto-baud rate detect function is finished
#1
ABRDTOIF
Auto-baud Rate Time-out Interrupt (Read Only)
Note1: This bit is set to logic 1 in Auto-baud Rate Detect mode and the baud rate counter is overflow.
Note2: This bit is read only, but can be cleared by writing 1 to it.
2
1
read-only
0
Auto-baud rate counter is underflow
#0
1
Auto-baud rate counter is overflow
#1
ADDRDETF
RS-485 Address Byte Detect Flag (Read Only) \nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit is read only, but can be cleared by writing '1' to it.
3
1
read-only
0
Receiver detects a data that is not an address bit (bit 9 ='0')
#0
1
Receiver detects a data that is an address bit (bit 9 ='1')
#1
BIF
Break Interrupt Flag (Read Only)
This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits).
Note: This bit is read only, but can be cleared by writing '1' to it.
6
1
read-only
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
Note: This bit is read only, but can be cleared by writing '1' to it.
5
1
read-only
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit .
Note: This bit is read only, but can be cleared by writing '1' to it.
4
1
read-only
0
No parity error is generated
#0
1
Parity error is generated
#1
RXEMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RXFULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16/64, otherwise is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RXOVIF
RX Overflow Error Interrupt Flag (Read Only)
This bit is set when RX FIFO overflow.
If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 16/64 bytes this bit will be set.
Note: This bit is read only, but can be cleared by writing 1 to it.
0
1
read-only
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RXPTR
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15/63. When the using level of RX FIFO Buffer equal to 16/64, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15/63.
8
6
read-only
TXEMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into DAT (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXEMPTYF
Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXFULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16/64, otherwise is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TXOVIF
TX Overflow Error Interrupt Flag (Read Only)
If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.
Note: This bit is read only, but can be cleared by writing 1 to it.
24
1
read-only
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TXPTR
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15/63. When the using level of TX FIFO Buffer equal to 16/64, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15/63.
16
6
read-only
UART_FUNCSEL
UART_FUNCSEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUNCSEL
Function Select\n
0
2
read-write
0
UART function
#00
1
LIN function (Only Available in UART1/UART2 Channel)
#01
2
IrDA function
#10
3
RS-485 function
#11
UART_INTEN
UART_INTEN
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Control\n
18
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
ATOCTSEN
nCTS Auto-flow Control Enable Control\n When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
ATORTSEN
nRTS Auto-flow Control Enable Control\n When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Control\n
5
1
read-write
0
Buffer error interrupt Disabled
#0
1
Buffer error interrupt Enabled
#1
LINIEN
LIN Bus Interrupt Enable Control (Not Available in UART1/UART2)\n This bit is used for LIN function mode.
8
1
read-write
0
LIN bus interrupt Disabled
#0
1
LIN bus interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Control\n
3
1
read-write
0
Modem status interrupt Disabled
#0
1
Modem status interrupt Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Control\n
0
1
read-write
0
Receive data available interrupt Disabled
#0
1
Receive data available interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Control\n
2
1
read-write
0
Receive Line Status interrupt Disabled
#0
1
Receive Line Status interrupt Enabled
#1
RXTOIEN
RX Time-out Interrupt Enable Control\n
4
1
read-write
0
RX time-out interrupt Disabled
#0
1
RX time-out interrupt Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Control\n
1
1
read-write
0
Transmit holding register empty interrupt Disabled
#0
1
Transmit holding register empty interrupt Enabled
#1
TOCNTEN
Time-out Counter Enable Control\n
11
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
WKCTSIEN
nCTS Wake-up Interrupt Enable Control\n
9
1
read-write
0
nCTS wake-up system function Disabled
#0
1
Wake-up system function Enabled. When the system is in Power-down mode, an external nCTS change will wake up system from Power-down mode
#1
WKDATIEN
Incoming Data Wake-up Interrupt Enable Control
Hardware will clear this bit when the incoming data wake-up operation finishes and system clock work stable.
10
1
read-write
0
Incoming data wake-up system function Disabled
#0
1
Incoming data wake-up system function Enabled. When the system is in Power-down mode, incoming data will wake up system from Power-down mode.
#1
UART_INTSTS
UART_INTSTS
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
BUFERRIF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5])is set, the transfer is not correct. If BFERRIEN (UART_INTEN [8]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is read only. This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BFERRIEN(UART_INTEN[5] and BUFERRIF(UART_INTSTS[5]) are both set to 1.\n
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
CTSWKIF
nCTS Wake-up Interrupt Flag (Read Only)\nNote1: If WKCTSIEN (UART_INTEN[9])is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it.
16
1
read-only
0
Chip stays in Power-down state
#0
1
Chip wake-up from Power-down state by nCTS wake-up
#1
DATWKIF
Data Wake-up Interrupt Flag (Read Only)\nThis bit is set if chip wake-up from Power-down state by data wake-up.\nNote1: If WKDATIEN (UART_INTEN[10]) is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it.
17
1
read-only
0
Chip stays in Power-down state
#0
1
Chip wake-up from Power-down state by data wake-up
#1
LINIF
LIN Bus Interrupt Flag (Read Only) (Not Available in UART0 Channel)\nNote: This bit is read only. This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]), SLVHEF(UART_LINSTS[1]) and SLVSYNCF(UART_LINSTS[3]) all are cleared.
7
1
read-only
0
None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated
#0
1
At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated
#1
LININT
LIN Bus Interrupt Indicator (Read Only)(Not Available in UART0 Channel)\nThis bit is set if LINIEN (UART_INTEN[8]) and LIN IF(UART_INTSTS[7]) are both set to 1.\n
15
1
read-only
0
No LIN Bus interrupt is generated
#0
1
The LIN Bus interrupt is generated
#1
MODEMIF
MODEM Interrupt Flag (Read Only) Channel \nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3] and MODEMIF(UART_INTSTS[4]) are both set to 1\n
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated.
#1
RDAIF
Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
0
1
read-only
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDAINT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.\n
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.\nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLSINT
Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.\n
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
0
No Time-out interrupt flag is generated
#0
1
Time-out interrupt flag is generated
#1
RXTOINT
Time-out Interrupt Indicator (Read Only)\nThis bit is set if TOUTIEN(UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.\n
12
1
read-only
0
No Tout interrupt is generated
#0
1
Tout interrupt is generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
1
1
read-only
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1])and THREIF(UART_INTSTS[1]) are both set to 1.\n
9
1
read-only
0
No DATE interrupt is generated
#0
1
DATE interrupt is generated
#1
WKIF
UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.\nNote: This bit is read only. This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF(UART_INTSTS[16]) are cleared to 0 by writing 1 to DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[17]).
6
1
read-only
0
No DATWKIF and CTSWKIF are generated
#0
1
DATWKIF or CTSWKIF
#1
WKINT
UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set when DATWKIF or CTSWKIF is set to 1.\n
14
1
read-only
0
NO data or nCTS wake-up interrupt are generated
#0
1
Data or nCTS wake-up interrupt are generated
#1
UART_IRDA
UART_IRDA
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
RXINV
IrDA Inverse Receive Input Signal \n
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Control\n
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal \n
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINCTL
UART_LINCTL
UART LIN Control Register *
0x34
-1
read-write
n
0x0
0x0
BITERREN
Bit Error Detect Enable Control\n
12
1
read-write
0
Bit error detection function Disabled
#0
1
Bit error detection Enabled
#1
BRKDETEN
LIN Break Detection Enable Control\n
10
1
read-write
0
LIN break detection Disabled
#0
1
LIN break detection Enabled
#1
BRKFL
LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of BRKFL, User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]).\nNote2: This break field length is BRKFL + 1.\n
16
4
read-write
BSL
LIN Break/Sync Delimiter Length \nNote: This bit is used for LIN master to send header field.
20
2
read-write
0
The LIN break/sync delimiter length is 1-bit time
#00
1
The LIN break/sync delimiter length is 2-bit time
#01
2
The LIN break/sync delimiter length is 3-bit time
#10
3
The LIN break/sync delimiter length is 4-bit time
#11
HSEL
LIN Header Select \n
22
2
read-write
0
The LIN header includes break field
#00
1
The LIN header includes break field and sync field
#01
2
The LIN header includes break field , sync field and frame ID field
#10
3
Reserved
#11
IDPEN
LIN ID Parity Enable Control\n
9
1
read-write
0
LIN frame ID parity Disabled
#0
1
LIN frame ID parity Enabled
#1
MUTE
LIN Mute Mode Enable Control\nNote: The exit from mute mode condition and each control and interactions of this field are explained in 6.10.5.9 (LIN Slave mode).
4
1
read-write
0
LIN mute mode Disabled
#0
1
LIN mute mode Enabled
#1
PID
LIN PID Bits\nIf the parity generated by hardware, and user fills in ID0~ID5, (PID [29:24]), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must fill a frame ID and parity in this field.\nNote1: User can fill in any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).\nNote2: This field can be used for LIN Master mode or Slave mode.
24
8
read-write
RXOFF
LIN Receiver Disable Control\n
11
1
read-write
0
LIN receiver Enabled
#0
1
LIN receiver Disabled
#1
SENDH
LIN TX Send Header Enable Control
The LIN TX header can be break field or break and sync field or break, sync and frame ID field , it is depend on setting HSEL (UART_LINCTL[23:22]).
Note1: These registers are shadow registers of LINTXEN (UART_ALTCTL [7]) user can read/write it by setting LINTXEN (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]).
Note2: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically.
8
1
read-write
0
Send LIN TX header Disabled
#0
1
Send LIN TX header Enabled
#1
SLVAREN
LIN Slave Automatic Resynchronization Mode Enable Control\nNote2: When operating in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).\nNote3: The control and interactions of this field are explained in 6.10.5.9(Slave mode with automatic resynchronization).
2
1
read-write
0
LIN automatic resynchronization Disabled
#0
1
LIN automatic resynchronization Enabled
#1
SLVDUEN
LIN Slave Divider Update Method Enable Control\nNote2: This bit is used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) \nNote3: The control and interactions of this field are explained in 6.10.5.9 (Slave mode with automatic resynchronization).
3
1
read-write
0
UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time)
#0
1
UART_BAUD is updated at the next received character. User must set the bit before checksum reception
#1
SLVEN
LIN Slave Mode Enable Control\n
0
1
read-write
0
LIN Slave mode Disabled
#0
1
LIN Slave mode Enabled
#1
SLVHDEN
LIN Slave Header Detection Enable Control\n
1
1
read-write
0
LIN slave header detection Disabled
#0
1
LIN slave header detection Enabled
#1
UART_LINE
UART_LINE
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control\nNote: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
6
1
read-write
0
Break Control Disabled
#0
1
Break Control Enabled
#1
EPE
Even Parity Enable Control\nNote: This bit is effective only when PBE (UART_LINE[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of STOP Bit
2
1
read-write
0
One STOP bit is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 STOP bit is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 STOP bit is generated in the transmitted data
#1
PBE
Parity Bit Enable Control\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data.
3
1
read-write
0
No parity bit generated Disabled
#0
1
Parity bit generated Enabled
#1
SPE
Stick Parity Enable Control\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
5
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
WLS
Word Length Selection\nThis field sets UART word length.\n
0
2
read-write
0
5 bits
#00
1
6 bits
#01
2
7 bits
#10
3
8 bits
#11
UART_LINSTS
UART_LINSTS
UART LIN Status Register *
0x38
read-write
n
0x0
0x0
BITEF
Bit Error Detect Status Flag (Read Only) \nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BITEF (UART_LINSTS[9]) will be set.\n
9
1
read-only
BRKDETF
LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.\n
8
1
read-only
0
LIN break not detected
#0
1
LIN break detected
#1
SLVHDETF
LIN Slave Header Detection Flag (Read Only)
This bit is set by hardware when a LIN header is detected in LIN Slave mode and be cleared by writing 1 to it.
Note3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header ( break + sync + frame ID ), the SLVHDETF will be set whether the frame ID correct or not.
0
1
read-only
0
LIN header not detected
#0
1
LIN header detected (break + sync + frame ID)
#1
SLVHEF
LIN Slave Header Error Flag (Read Only)
This bit is set by hardware when a LIN header error is detected in LIN Slave mode and be cleared by writing 1 to it. The header errors include break delimiter is too short (less than 0.5 bit time) , frame error in sync field or Identifier field , sync field data is not 0x55 in Non-Automatic Resynchronization mode , sync field deviation error with Automatic Resynchronization mode , sync field measure time-out with Automatic Resynchronization mode and LIN header reception time-out .
1
1
read-only
0
LIN header error not detected
#0
1
LIN header error detected
#1
SLVIDPEF
LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct.\n
2
1
read-write
0
No active
#0
1
Receipted frame ID parity is not correct
#1
SLVSYNCF
LIN Slave Sync Field (Read Only)\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit is read only, but it can be cleared by writing 1 to it.\nNote3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header.
3
1
read-only
0
The current character is not at LIN sync state
#0
1
The current character is at LIN sync state
#1
UART_MODEM
UART_MODEM
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
RTS
nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
1
1
read-write
0
nRTS signal is active
#0
1
nRTS signal is inactive
#1
RTSACTLV
nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1010 and Figure 6.1011 for UART function mode.\nNote2: Refer to Figure 6.1021 and Figure 6.1022 for RS-485 function mode.
9
1
read-write
0
nRTS pin output is high level active
#0
1
nRTS pin output is low level active. (Default)
#1
RTSSTS
nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status.\n
13
1
read-only
0
nRTS pin output is low level voltage logic state
#0
1
nRTS pin output is high level voltage logic state
#1
UART_MODEMSTS
UART_MODEMSTS
UART Modem Status Register
0x14
-1
read-write
n
0x0
0x0
CTSACTLV
nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\n
8
1
read-write
0
nCTS pin input is high level active
#0
1
nCTS pin input is low level active. (Default)
#1
CTSDETF
Detect nCTS State Change Flag (Read Only)
This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.
Note: This bit is read only, but can be cleared by writing 1 to it.
0
1
read-only
0
nCTS input has not change state
#0
1
nCTS input has change state
#1
CTSSTS
nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled, and nCTS multi-function port is selected.
4
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
UART_TOUT
UART_TOUT
UART Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time.
8
8
read-write
TOIC
Time-out Interrupt Comparator\n
0
8
read-write
UART1
UART Register Map
UART
0x0
0x0
0x3C
registers
n
UART_ALTCTL
UART_ALTCTL
UART Alternate Control/Status Register
0x2C
-1
read-write
n
0x0
0x0
ABRDBITS
Auto-baud Rate Detect Bit Length \nNote: The calculation of bit number includes the START bit.
19
2
read-write
0
1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01
#00
1
2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02
#01
2
4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08
#10
3
8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80
#11
ABRDEN
Auto-baud Rate Detect Enable Control\nNote: This bit is cleared automatically after auto-baud detection is finished.
18
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
ABRIF
Auto-baud Rate Interrupt Flag (Read Only)
This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated.
Note: This bit is read only, but it can be cleared by writing 1 to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).
17
1
read-only
ADDRDEN
RS-485 Address Detection Enable Control\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value \nThis field contains the RS-485 address match values.\n This field is used for RS-485 auto address detection mode.
24
8
read-write
BRKFL
UART LIN Break Field Length (Only Available in UART1/UART2 Channel)\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1\n
0
4
read-write
LINRXEN
LIN RX Enable Control (Only Available in UART1/UART2 Channel)\n
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LINTXEN
LIN TX Break Mode Enable Control (Only Available in UART1/UART2 Channel)\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
LIN TX Break mode Disabled
#0
1
LIN TX Break mode Enabled
#1
RS485AAD
RS-485 Auto Address Detection Operation Mode (AAD)\n It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485AUD
RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation function (AUD) Disabled
#0
1
RS-485 Auto Direction Operation function (AUD) Enabled
#1
RS485NMM
RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UART Baud Rate Divisor Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.102.
28
1
read-write
BAUDM1
BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.102.\n In IrDA mode must be operated in mode 0.
29
1
read-write
BRD
Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.102.
0
16
read-write
EDIVM1
Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.102.
24
4
read-write
UART_DAT
UART_DAT
UART Receive/Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Receiving/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD. \nRead Operation:\nBy reading this register, the UART will return an 8-bit data received from receiving FIFO.
0
8
read-write
UART_FIFO
UART_FIFO
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).\n
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
4
RX FIFO Interrupt Trigger Level is 30/14 (64 FIFO/16 FIFO)
#0100
5
RX FIFO Interrupt Trigger Level is 46/14 (64 FIFO/16 FIFO)
#0101
6
RX FIFO Interrupt Trigger Level is 62/14 (64 FIFO/16 FIFO)
#0110
RTSTRGLV
nRTS Trigger Level for Auto-flow Control Use\nNote: This field is used for automatic nRTS flow control.
16
4
read-write
0
nRTS Trigger Level is 1 bytes
#0000
1
nRTS Trigger Level is 4bytes
#0001
2
nRTS Trigger Level is 8 bytes
#0010
3
nRTS Trigger Level is 14 bytes
#0011
4
nRTS Trigger Level is 30/14 (64 FIFO/16 FIFO)
#0100
5
nRTS Trigger Level is 46/14 (64 FIFO/16 FIFO)
#0101
6
nRTS Trigger Level is 62/14 (64 FIFO/16 FIFO)
#0110
RXOFF
Receiver Disable Control\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset Control\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset Control\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ABRDIF
Auto-baud Rate Detect Interrupt (Read Only)
Note1: This bit is set to logic 1 when auto-baud rate detect function is finished.
Note2: This bit is read only, but can be cleared by writing 1 to it.
1
1
read-only
0
Auto-baud rate detect function is not finished
#0
1
Auto-baud rate detect function is finished
#1
ABRDTOIF
Auto-baud Rate Time-out Interrupt (Read Only)
Note1: This bit is set to logic 1 in Auto-baud Rate Detect mode and the baud rate counter is overflow.
Note2: This bit is read only, but can be cleared by writing 1 to it.
2
1
read-only
0
Auto-baud rate counter is underflow
#0
1
Auto-baud rate counter is overflow
#1
ADDRDETF
RS-485 Address Byte Detect Flag (Read Only) \nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit is read only, but can be cleared by writing '1' to it.
3
1
read-only
0
Receiver detects a data that is not an address bit (bit 9 ='0')
#0
1
Receiver detects a data that is an address bit (bit 9 ='1')
#1
BIF
Break Interrupt Flag (Read Only)
This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits).
Note: This bit is read only, but can be cleared by writing '1' to it.
6
1
read-only
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
Note: This bit is read only, but can be cleared by writing '1' to it.
5
1
read-only
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit .
Note: This bit is read only, but can be cleared by writing '1' to it.
4
1
read-only
0
No parity error is generated
#0
1
Parity error is generated
#1
RXEMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RXFULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16/64, otherwise is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RXOVIF
RX Overflow Error Interrupt Flag (Read Only)
This bit is set when RX FIFO overflow.
If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 16/64 bytes this bit will be set.
Note: This bit is read only, but can be cleared by writing 1 to it.
0
1
read-only
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RXPTR
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15/63. When the using level of RX FIFO Buffer equal to 16/64, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15/63.
8
6
read-only
TXEMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into DAT (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXEMPTYF
Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXFULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16/64, otherwise is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TXOVIF
TX Overflow Error Interrupt Flag (Read Only)
If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.
Note: This bit is read only, but can be cleared by writing 1 to it.
24
1
read-only
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TXPTR
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15/63. When the using level of TX FIFO Buffer equal to 16/64, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15/63.
16
6
read-only
UART_FUNCSEL
UART_FUNCSEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUNCSEL
Function Select\n
0
2
read-write
0
UART function
#00
1
LIN function (Only Available in UART1/UART2 Channel)
#01
2
IrDA function
#10
3
RS-485 function
#11
UART_INTEN
UART_INTEN
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Control\n
18
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
ATOCTSEN
nCTS Auto-flow Control Enable Control\n When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
ATORTSEN
nRTS Auto-flow Control Enable Control\n When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Control\n
5
1
read-write
0
Buffer error interrupt Disabled
#0
1
Buffer error interrupt Enabled
#1
LINIEN
LIN Bus Interrupt Enable Control (Not Available in UART1/UART2)\n This bit is used for LIN function mode.
8
1
read-write
0
LIN bus interrupt Disabled
#0
1
LIN bus interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Control\n
3
1
read-write
0
Modem status interrupt Disabled
#0
1
Modem status interrupt Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Control\n
0
1
read-write
0
Receive data available interrupt Disabled
#0
1
Receive data available interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Control\n
2
1
read-write
0
Receive Line Status interrupt Disabled
#0
1
Receive Line Status interrupt Enabled
#1
RXTOIEN
RX Time-out Interrupt Enable Control\n
4
1
read-write
0
RX time-out interrupt Disabled
#0
1
RX time-out interrupt Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Control\n
1
1
read-write
0
Transmit holding register empty interrupt Disabled
#0
1
Transmit holding register empty interrupt Enabled
#1
TOCNTEN
Time-out Counter Enable Control\n
11
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
WKCTSIEN
nCTS Wake-up Interrupt Enable Control\n
9
1
read-write
0
nCTS wake-up system function Disabled
#0
1
Wake-up system function Enabled. When the system is in Power-down mode, an external nCTS change will wake up system from Power-down mode
#1
WKDATIEN
Incoming Data Wake-up Interrupt Enable Control
Hardware will clear this bit when the incoming data wake-up operation finishes and system clock work stable.
10
1
read-write
0
Incoming data wake-up system function Disabled
#0
1
Incoming data wake-up system function Enabled. When the system is in Power-down mode, incoming data will wake up system from Power-down mode
#1
UART_INTSTS
UART_INTSTS
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
BUFERRIF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5])is set, the transfer is not correct. If BFERRIEN (UART_INTEN [8]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is read only. This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BFERRIEN(UART_INTEN[5] and BUFERRIF(UART_INTSTS[5]) are both set to 1.\n
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
CTSWKIF
nCTS Wake-up Interrupt Flag (Read Only)\nNote1: If WKCTSIEN (UART_INTEN[9])is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it.
16
1
read-only
0
Chip stays in Power-down state
#0
1
Chip wake-up from Power-down state by nCTS wake-up
#1
DATWKIF
Data Wake-up Interrupt Flag (Read Only)\nThis bit is set if chip wake-up from Power-down state by data wake-up.\nNote1: If WKDATIEN (UART_INTEN[10]) is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it.
17
1
read-only
0
Chip stays in Power-down state
#0
1
Chip wake-up from Power-down state by data wake-up
#1
LINIF
LIN Bus Interrupt Flag (Read Only) (Not Available in UART0 Channel)\nNote: This bit is read only. This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]), SLVHEF(UART_LINSTS[1]) and SLVSYNCF(UART_LINSTS[3]) all are cleared.
7
1
read-only
0
None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated
#0
1
At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated
#1
LININT
LIN Bus Interrupt Indicator (Read Only)(Not Available in UART0 Channel)\nThis bit is set if LINIEN (UART_INTEN[8]) and LIN IF(UART_INTSTS[7]) are both set to 1.\n
15
1
read-only
0
No LIN Bus interrupt is generated
#0
1
The LIN Bus interrupt is generated
#1
MODEMIF
MODEM Interrupt Flag (Read Only) Channel \nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3] and MODEMIF(UART_INTSTS[4]) are both set to 1\n
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDAIF
Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
0
1
read-only
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDAINT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.\n
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.\nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLSINT
Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.\n
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
0
No Time-out interrupt flag is generated
#0
1
Time-out interrupt flag is generated
#1
RXTOINT
Time-out Interrupt Indicator (Read Only)\nThis bit is set if TOUTIEN(UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.\n
12
1
read-only
0
No Tout interrupt is generated
#0
1
Tout interrupt is generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
1
1
read-only
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1])and THREIF(UART_INTSTS[1]) are both set to 1.\n
9
1
read-only
0
No DATE interrupt is generated
#0
1
DATE interrupt is generated
#1
WKIF
UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.\nNote: This bit is read only. This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF(UART_INTSTS[16]) are cleared to 0 by writing 1 to DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[17]).
6
1
read-only
0
No DATWKIF and CTSWKIF are generated
#0
1
DATWKIF or CTSWKIF
#1
WKINT
UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set when DATWKIF or CTSWKIF is set to 1.\n
14
1
read-only
0
NO data or nCTS wake-up interrupt are generated
#0
1
Data or nCTS wake-up interrupt are generated
#1
UART_IRDA
UART_IRDA
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
RXINV
IrDA Inverse Receive Input Signal \n
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Control\n
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal \n
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINCTL
UART_LINCTL
UART LIN Control Register *
0x34
-1
read-write
n
0x0
0x0
BITERREN
Bit Error Detect Enable Control\n
12
1
read-write
0
Bit error detection function Disabled
#0
1
Bit error detection Enabled
#1
BRKDETEN
LIN Break Detection Enable Control\n
10
1
read-write
0
LIN break detection Disabled
#0
1
LIN break detection Enabled
#1
BRKFL
LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of BRKFL, User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]).\nNote2: This break field length is BRKFL + 1.\n
16
4
read-write
BSL
LIN Break/Sync Delimiter Length \nNote: This bit is used for LIN master to send header field.
20
2
read-write
0
The LIN break/sync delimiter length is 1-bit time
#00
1
The LIN break/sync delimiter length is 2-bit time
#01
2
The LIN break/sync delimiter length is 3-bit time
#10
3
The LIN break/sync delimiter length is 4-bit time
#11
HSEL
LIN Header Select \n
22
2
read-write
0
The LIN header includes break field
#00
1
The LIN header includes break field and sync field
#01
2
The LIN header includes break field , sync field and frame ID field
#10
3
Reserved
#11
IDPEN
LIN ID Parity Enable Control\n
9
1
read-write
0
LIN frame ID parity Disabled
#0
1
LIN frame ID parity Enabled
#1
MUTE
LIN Mute Mode Enable Control\nNote: The exit from mute mode condition and each control and interactions of this field are explained in 6.10.5.9 (LIN Slave mode).
4
1
read-write
0
LIN mute mode Disabled
#0
1
LIN mute mode Enabled
#1
PID
LIN PID Bits\nIf the parity generated by hardware, and user fills in ID0~ID5, (PID [29:24]), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must fill a frame ID and parity in this field.\nNote1: User can fill in any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).\nNote2: This field can be used for LIN Master mode or Slave mode.
24
8
read-write
RXOFF
LIN Receiver Disable Control\n
11
1
read-write
0
LIN receiver Enabled
#0
1
LIN receiver Disabled
#1
SENDH
LIN TX Send Header Enable Control
The LIN TX header can be break field or break and sync field or break, sync and frame ID field , it is depend on setting HSEL (UART_LINCTL[23:22]).
Note1: These registers are shadow registers of LINTXEN (UART_ALTCTL [7]) user can read/write it by setting LINTXEN (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]).
Note2: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically.
8
1
read-write
0
Send LIN TX header Disabled
#0
1
Send LIN TX header Enabled
#1
SLVAREN
LIN Slave Automatic Resynchronization Mode Enable Control\nNote2: When operating in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).\nNote3: The control and interactions of this field are explained in 6.10.5.9(Slave mode with automatic resynchronization).
2
1
read-write
0
LIN automatic resynchronization Disabled
#0
1
LIN automatic resynchronization Enabled
#1
SLVDUEN
LIN Slave Divider Update Method Enable Control\nNote2: This bit is used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) \nNote3: The control and interactions of this field are explained in 6.10.5.9 (Slave mode with automatic resynchronization).
3
1
read-write
0
UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time)
#0
1
UART_BAUD is updated at the next received character. User must set the bit before checksum reception
#1
SLVEN
LIN Slave Mode Enable Control\n
0
1
read-write
0
LIN Slave mode Disabled
#0
1
LIN Slave mode Enabled
#1
SLVHDEN
LIN Slave Header Detection Enable Control\n
1
1
read-write
0
LIN slave header detection Disabled
#0
1
LIN slave header detection Enabled
#1
UART_LINE
UART_LINE
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control\nNote: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
6
1
read-write
0
Break Control Disabled
#0
1
Break Control Enabled
#1
EPE
Even Parity Enable Control\nNote: This bit is effective only when PBE (UART_LINE[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of STOP Bit
2
1
read-write
0
One STOP bit is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 STOP bit is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 STOP bit is generated in the transmitted data
#1
PBE
Parity Bit Enable Control\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data.
3
1
read-write
0
No parity bit generated Disabled
#0
1
Parity bit generated Enabled
#1
SPE
Stick Parity Enable Control\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
5
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
WLS
Word Length Selection\nThis field sets UART word length.\n
0
2
read-write
0
5 bits
#00
1
6 bits
#01
2
7 bits
#10
3
8 bits
#11
UART_LINSTS
UART_LINSTS
UART LIN Status Register *
0x38
read-write
n
0x0
0x0
BITEF
Bit Error Detect Status Flag (Read Only) \nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BITEF (UART_LINSTS[9]) will be set.\n
9
1
read-only
BRKDETF
LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.\n
8
1
read-only
0
LIN break not detected
#0
1
LIN break detected
#1
SLVHDETF
LIN Slave Header Detection Flag (Read Only)
This bit is set by hardware when a LIN header is detected in LIN Slave mode and be cleared by writing 1 to it.
Note3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header ( break + sync + frame ID ), the SLVHDETF will be set whether the frame ID correct or not.
0
1
read-only
0
LIN header not detected
#0
1
LIN header detected (break + sync + frame ID)
#1
SLVHEF
LIN Slave Header Error Flag (Read Only)
This bit is set by hardware when a LIN header error is detected in LIN Slave mode and be cleared by writing 1 to it. The header errors include break delimiter is too short (less than 0.5 bit time) , frame error in sync field or Identifier field , sync field data is not 0x55 in Non-Automatic Resynchronization mode , sync field deviation error with Automatic Resynchronization mode , sync field measure time-out with Automatic Resynchronization mode and LIN header reception time-out .
1
1
read-only
0
LIN header error not detected
#0
1
LIN header error detected
#1
SLVIDPEF
LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct.\n
2
1
read-write
0
No active
#0
1
Receipted frame ID parity is not correct
#1
SLVSYNCF
LIN Slave Sync Field (Read Only)\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit is read only, but it can be cleared by writing 1 to it.\nNote3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header.
3
1
read-only
0
The current character is not at LIN sync state
#0
1
The current character is at LIN sync state
#1
UART_MODEM
UART_MODEM
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
RTS
nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
1
1
read-write
0
nRTS signal is active
#0
1
nRTS signal is inactive
#1
RTSACTLV
nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1010 and Figure 6.1011 for UART function mode.\nNote2: Refer to Figure 6.1021 and Figure 6.1022 for RS-485 function mode.
9
1
read-write
0
nRTS pin output is high level active
#0
1
nRTS pin output is low level active. (Default)
#1
RTSSTS
nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status.\n
13
1
read-only
0
nRTS pin output is low level voltage logic state
#0
1
nRTS pin output is high level voltage logic state
#1
UART_MODEMSTS
UART_MODEMSTS
UART Modem Status Register
0x14
-1
read-write
n
0x0
0x0
CTSACTLV
nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\n
8
1
read-write
0
nCTS pin input is high level active
#0
1
nCTS pin input is low level active. (Default)
#1
CTSDETF
Detect nCTS State Change Flag (Read Only)
This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.
Note: This bit is read only, but can be cleared by writing 1 to it.
0
1
read-only
0
nCTS input has not change state
#0
1
nCTS input has change state
#1
CTSSTS
nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled, and nCTS multi-function port is selected.
4
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
UART_TOUT
UART_TOUT
UART Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time.
8
8
read-write
TOIC
Time-out Interrupt Comparator\n
0
8
read-write
UART2
UART Register Map
UART
0x0
0x0
0x3C
registers
n
UART_ALTCTL
UART_ALTCTL
UART Alternate Control/Status Register
0x2C
-1
read-write
n
0x0
0x0
ABRDBITS
Auto-baud Rate Detect Bit Length \nNote: The calculation of bit number includes the START bit.
19
2
read-write
0
1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01
#00
1
2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02
#01
2
4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08
#10
3
8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80
#11
ABRDEN
Auto-baud Rate Detect Enable Control\nNote: This bit is cleared automatically after auto-baud detection is finished.
18
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
ABRIF
Auto-baud Rate Interrupt Flag (Read Only)
This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated.
Note: This bit is read only, but it can be cleared by writing 1 to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).
17
1
read-only
ADDRDEN
RS-485 Address Detection Enable Control\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value \nThis field contains the RS-485 address match values.\n This field is used for RS-485 auto address detection mode.
24
8
read-write
BRKFL
UART LIN Break Field Length (Only Available in UART1/UART2 Channel)\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1\n
0
4
read-write
LINRXEN
LIN RX Enable Control (Only Available in UART1/UART2 Channel)\n
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LINTXEN
LIN TX Break Mode Enable Control (Only Available in UART1/UART2 Channel)\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
LIN TX Break mode Disabled
#0
1
LIN TX Break mode Enabled
#1
RS485AAD
RS-485 Auto Address Detection Operation Mode (AAD)\n It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485AUD
RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation function (AUD) Disabled
#0
1
RS-485 Auto Direction Operation function (AUD) Enabled
#1
RS485NMM
RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UART Baud Rate Divisor Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.102.
28
1
read-write
BAUDM1
BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.102.\n In IrDA mode must be operated in mode 0.
29
1
read-write
BRD
Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.102.
0
16
read-write
EDIVM1
Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.102.
24
4
read-write
UART_DAT
UART_DAT
UART Receive/Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Receiving/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD. \nRead Operation:\nBy reading this register, the UART will return an 8-bit data received from receiving FIFO.
0
8
read-write
UART_FIFO
UART_FIFO
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).\n
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
4
RX FIFO Interrupt Trigger Level is 30/14 (64 FIFO/16 FIFO)
#0100
5
RX FIFO Interrupt Trigger Level is 46/14 (64 FIFO/16 FIFO)
#0101
6
RX FIFO Interrupt Trigger Level is 62/14 (64 FIFO/16 FIFO)
#0110
RTSTRGLV
nRTS Trigger Level for Auto-flow Control Use\nNote: This field is used for automatic nRTS flow control.
16
4
read-write
0
nRTS Trigger Level is 1 bytes
#0000
1
nRTS Trigger Level is 4bytes
#0001
2
nRTS Trigger Level is 8 bytes
#0010
3
nRTS Trigger Level is 14 bytes
#0011
4
nRTS Trigger Level is 30/14 (64 FIFO/16 FIFO)
#0100
5
nRTS Trigger Level is 46/14 (64 FIFO/16 FIFO)
#0101
6
nRTS Trigger Level is 62/14 (64 FIFO/16 FIFO)
#0110
RXOFF
Receiver Disable Control\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset Control\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset Control\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ABRDIF
Auto-baud Rate Detect Interrupt (Read Only)
Note1: This bit is set to logic 1 when auto-baud rate detect function is finished.
Note2: This bit is read only, but can be cleared by writing 1 to it.
1
1
read-only
0
Auto-baud rate detect function is not finished
#0
1
Auto-baud rate detect function is finished
#1
ABRDTOIF
Auto-baud Rate Time-out Interrupt (Read Only)
Note1: This bit is set to logic 1 in Auto-baud Rate Detect mode and the baud rate counter is overflow.
Note2: This bit is read only, but can be cleared by writing 1 to it.
2
1
read-only
0
Auto-baud rate counter is underflow
#0
1
Auto-baud rate counter is overflow
#1
ADDRDETF
RS-485 Address Byte Detect Flag (Read Only) \nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit is read only, but can be cleared by writing '1' to it.
3
1
read-only
0
Receiver detects a data that is not an address bit (bit 9 ='0')
#0
1
Receiver detects a data that is an address bit (bit 9 ='1')
#1
BIF
Break Interrupt Flag (Read Only)
This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits).
Note: This bit is read only, but can be cleared by writing '1' to it.
6
1
read-only
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
Note: This bit is read only, but can be cleared by writing '1' to it.
5
1
read-only
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid parity bit .
Note: This bit is read only, but can be cleared by writing '1' to it.
4
1
read-only
0
No parity error is generated
#0
1
Parity error is generated
#1
RXEMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RXFULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16/64, otherwise is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RXOVIF
RX Overflow Error Interrupt Flag (Read Only)
This bit is set when RX FIFO overflow.
If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 16/64 bytes this bit will be set.
Note: This bit is read only, but can be cleared by writing 1 to it.
0
1
read-only
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RXPTR
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15/63. When the using level of RX FIFO Buffer equal to 16/64, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15/63.
8
6
read-only
TXEMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into DAT (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXEMPTYF
Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXFULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16/64, otherwise is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TXOVIF
TX Overflow Error Interrupt Flag (Read Only)
If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.
Note: This bit is read only, but can be cleared by writing 1 to it.
24
1
read-only
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TXPTR
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15/63. When the using level of TX FIFO Buffer equal to 16/64, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15/63.
16
6
read-only
UART_FUNCSEL
UART_FUNCSEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUNCSEL
Function Select\n
0
2
read-write
0
UART function
#00
1
LIN function (Only Available in UART1/UART2 Channel)
#01
2
IrDA function
#10
3
RS-485 function
#11
UART_INTEN
UART_INTEN
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Control\n
18
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
ATOCTSEN
nCTS Auto-flow Control Enable Control\n When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
ATORTSEN
nRTS Auto-flow Control Enable Control\n When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Control\n
5
1
read-write
0
Buffer error interrupt Disabled
#0
1
Buffer error interrupt Enabled
#1
LINIEN
LIN Bus Interrupt Enable Control (Not Available in UART1/UART2)\n This bit is used for LIN function mode.
8
1
read-write
0
LIN bus interrupt Disabled
#0
1
LIN bus interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Control\n
3
1
read-write
0
Modem status interrupt Disabled
#0
1
Modem status interrupt Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Control\n
0
1
read-write
0
Receive data available interrupt Disabled
#0
1
Receive data available interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Control\n
2
1
read-write
0
Receive Line Status interrupt Disabled
#0
1
Receive Line Status interrupt Enabled
#1
RXTOIEN
RX Time-out Interrupt Enable Control\n
4
1
read-write
0
RX time-out interrupt Disabled
#0
1
RX time-out interrupt Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Control\n
1
1
read-write
0
Transmit holding register empty interrupt Disabled
#0
1
Transmit holding register empty interrupt Enabled
#1
TOCNTEN
Time-out Counter Enable Control\n
11
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
WKCTSIEN
nCTS Wake-up Interrupt Enable Control\n
9
1
read-write
0
nCTS wake-up system function Disabled
#0
1
Wake-up system function Enabled. When the system is in Power-down mode, an external nCTS change will wake up system from Power-down mode
#1
WKDATIEN
Incoming Data Wake-up Interrupt Enable Control
Hardware will clear this bit when the incoming data wake-up operation finishes and system clock work stable.
10
1
read-write
0
Incoming data wake-up system function Disabled
#0
1
Incoming data wake-up system function Enabled. When the system is in Power-down mode, incoming data will wake up system from Power-down mode
#1
UART_INTSTS
UART_INTSTS
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
BUFERRIF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5])is set, the transfer is not correct. If BFERRIEN (UART_INTEN [8]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is read only. This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BFERRIEN(UART_INTEN[5] and BUFERRIF(UART_INTSTS[5]) are both set to 1.\n
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
CTSWKIF
nCTS Wake-up Interrupt Flag (Read Only)\nNote1: If WKCTSIEN (UART_INTEN[9])is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it.
16
1
read-only
0
Chip stays in Power-down state
#0
1
Chip wake-up from Power-down state by nCTS wake-up
#1
DATWKIF
Data Wake-up Interrupt Flag (Read Only)\nThis bit is set if chip wake-up from Power-down state by data wake-up.\nNote1: If WKDATIEN (UART_INTEN[10]) is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it.
17
1
read-only
0
Chip stays in Power-down state
#0
1
Chip wake-up from Power-down state by data wake-up
#1
LINIF
LIN Bus Interrupt Flag (Read Only) (Not Available in UART0 Channel)\nNote: This bit is read only. This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]), SLVHEF(UART_LINSTS[1]) and SLVSYNCF(UART_LINSTS[3]) all are cleared.
7
1
read-only
0
None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated
#0
1
At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated
#1
LININT
LIN Bus Interrupt Indicator (Read Only)(Not Available in UART0 Channel)\nThis bit is set if LINIEN (UART_INTEN[8]) and LIN IF(UART_INTSTS[7]) are both set to 1.\n
15
1
read-only
0
No LIN Bus interrupt is generated
#0
1
The LIN Bus interrupt is generated
#1
MODEMIF
MODEM Interrupt Flag (Read Only) Channel \nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3] and MODEMIF(UART_INTSTS[4]) are both set to 1\n
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDAIF
Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
0
1
read-only
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDAINT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.\n
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.\nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLSINT
Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.\n
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
0
No Time-out interrupt flag is generated
#0
1
Time-out interrupt flag is generated
#1
RXTOINT
Time-out Interrupt Indicator (Read Only)\nThis bit is set if TOUTIEN(UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.\n
12
1
read-only
0
No Tout interrupt is generated
#0
1
Tout interrupt is generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
1
1
read-only
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1])and THREIF(UART_INTSTS[1]) are both set to 1.\n
9
1
read-only
0
No DATE interrupt is generated
#0
1
DATE interrupt is generated
#1
WKIF
UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.\nNote: This bit is read only. This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF(UART_INTSTS[16]) are cleared to 0 by writing 1 to DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[17]).
6
1
read-only
0
No DATWKIF and CTSWKIF are generated
#0
1
DATWKIF or CTSWKIF
#1
WKINT
UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set when DATWKIF or CTSWKIF is set to 1.\n
14
1
read-only
0
NO data or nCTS wake-up interrupt are generated
#0
1
Data or nCTS wake-up interrupt are generated
#1
UART_IRDA
UART_IRDA
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
RXINV
IrDA Inverse Receive Input Signal \n
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Control\n
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal \n
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINCTL
UART_LINCTL
UART LIN Control Register *
0x34
-1
read-write
n
0x0
0x0
BITERREN
Bit Error Detect Enable Control\n
12
1
read-write
0
Bit error detection function Disabled
#0
1
Bit error detection Enabled
#1
BRKDETEN
LIN Break Detection Enable Control\n
10
1
read-write
0
LIN break detection Disabled
#0
1
LIN break detection Enabled
#1
BRKFL
LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of BRKFL, User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]).\nNote2: This break field length is BRKFL + 1.\n
16
4
read-write
BSL
LIN Break/Sync Delimiter Length \nNote: This bit is used for LIN master to send header field.
20
2
read-write
0
The LIN break/sync delimiter length is 1-bit time
#00
1
The LIN break/sync delimiter length is 2-bit time
#01
2
The LIN break/sync delimiter length is 3-bit time
#10
3
The LIN break/sync delimiter length is 4-bit time
#11
HSEL
LIN Header Select \n
22
2
read-write
0
The LIN header includes break field
#00
1
The LIN header includes break field and sync field
#01
2
The LIN header includes break field , sync field and frame ID field
#10
3
Reserved
#11
IDPEN
LIN ID Parity Enable Control\n
9
1
read-write
0
LIN frame ID parity Disabled
#0
1
LIN frame ID parity Enabled
#1
MUTE
LIN Mute Mode Enable Control\nNote: The exit from mute mode condition and each control and interactions of this field are explained in 6.10.5.9 (LIN Slave mode).
4
1
read-write
0
LIN mute mode Disabled
#0
1
LIN mute mode Enabled
#1
PID
LIN PID Bits\nIf the parity generated by hardware, and user fills in ID0~ID5, (PID [29:24]), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must fill a frame ID and parity in this field.\nNote1: User can fill in any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).\nNote2: This field can be used for LIN Master mode or Slave mode.
24
8
read-write
RXOFF
LIN Receiver Disable Control\n
11
1
read-write
0
LIN receiver Enabled
#0
1
LIN receiver Disabled
#1
SENDH
LIN TX Send Header Enable Control
The LIN TX header can be break field or break and sync field or break, sync and frame ID field , it is depend on setting HSEL (UART_LINCTL[23:22]).
Note1: These registers are shadow registers of LINTXEN (UART_ALTCTL [7]) user can read/write it by setting LINTXEN (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]).
Note2: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically.
8
1
read-write
0
Send LIN TX header Disabled
#0
1
Send LIN TX header Enabled
#1
SLVAREN
LIN Slave Automatic Resynchronization Mode Enable Control\nNote2: When operating in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).\nNote3: The control and interactions of this field are explained in 6.10.5.9(Slave mode with automatic resynchronization).
2
1
read-write
0
LIN automatic resynchronization Disabled
#0
1
LIN automatic resynchronization Enabled
#1
SLVDUEN
LIN Slave Divider Update Method Enable Control\nNote2: This bit is used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) \nNote3: The control and interactions of this field are explained in 6.10.5.9 (Slave mode with automatic resynchronization).
3
1
read-write
0
UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time)
#0
1
UART_BAUD is updated at the next received character. User must set the bit before checksum reception
#1
SLVEN
LIN Slave Mode Enable Control\n
0
1
read-write
0
LIN Slave mode Disabled
#0
1
LIN Slave mode Enabled
#1
SLVHDEN
LIN Slave Header Detection Enable Control\n
1
1
read-write
0
LIN slave header detection Disabled
#0
1
LIN slave header detection Enabled
#1
UART_LINE
UART_LINE
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control\nNote: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
6
1
read-write
0
Break Control Disabled
#0
1
Break Control Enabled
#1
EPE
Even Parity Enable Control\nNote: This bit is effective only when PBE (UART_LINE[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of STOP Bit
2
1
read-write
0
One STOP bit is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 STOP bit is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 STOP bit is generated in the transmitted data
#1
PBE
Parity Bit Enable Control\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data.
3
1
read-write
0
No parity bit generated Disabled
#0
1
Parity bit generated Enabled
#1
SPE
Stick Parity Enable Control\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
5
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
WLS
Word Length Selection\nThis field sets UART word length.\n
0
2
read-write
0
5 bits
#00
1
6 bits
#01
2
7 bits
#10
3
8 bits
#11
UART_LINSTS
UART_LINSTS
UART LIN Status Register *
0x38
read-write
n
0x0
0x0
BITEF
Bit Error Detect Status Flag (Read Only) \nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BITEF (UART_LINSTS[9]) will be set.\n
9
1
read-only
BRKDETF
LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.\n
8
1
read-only
0
LIN break not detected
#0
1
LIN break detected
#1
SLVHDETF
LIN Slave Header Detection Flag (Read Only)
This bit is set by hardware when a LIN header is detected in LIN Slave mode and be cleared by writing 1 to it.
Note3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header ( break + sync + frame ID ), the SLVHDETF will be set whether the frame ID correct or not.
0
1
read-only
0
LIN header not detected
#0
1
LIN header detected (break + sync + frame ID)
#1
SLVHEF
LIN Slave Header Error Flag (Read Only)
This bit is set by hardware when a LIN header error is detected in LIN Slave mode and be cleared by writing 1 to it. The header errors include break delimiter is too short (less than 0.5 bit time) , frame error in sync field or Identifier field , sync field data is not 0x55 in Non-Automatic Resynchronization mode , sync field deviation error with Automatic Resynchronization mode , sync field measure time-out with Automatic Resynchronization mode and LIN header reception time-out .
1
1
read-only
0
LIN header error not detected
#0
1
LIN header error detected
#1
SLVIDPEF
LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct.\n
2
1
read-write
0
No active
#0
1
Receipted frame ID parity is not correct
#1
SLVSYNCF
LIN Slave Sync Field (Read Only)\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit is read only, but it can be cleared by writing 1 to it.\nNote3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header.
3
1
read-only
0
The current character is not at LIN sync state
#0
1
The current character is at LIN sync state
#1
UART_MODEM
UART_MODEM
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
RTS
nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
1
1
read-write
0
nRTS signal is active
#0
1
nRTS signal is inactive
#1
RTSACTLV
nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1010 and Figure 6.1011 for UART function mode.\nNote2: Refer to Figure 6.1021 and Figure 6.1022 for RS-485 function mode.
9
1
read-write
0
nRTS pin output is high level active
#0
1
nRTS pin output is low level active. (Default)
#1
RTSSTS
nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status.\n
13
1
read-only
0
nRTS pin output is low level voltage logic state
#0
1
nRTS pin output is high level voltage logic state
#1
UART_MODEMSTS
UART_MODEMSTS
UART Modem Status Register
0x14
-1
read-write
n
0x0
0x0
CTSACTLV
nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\n
8
1
read-write
0
nCTS pin input is high level active
#0
1
nCTS pin input is low level active. (Default)
#1
CTSDETF
Detect nCTS State Change Flag (Read Only)
This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.
Note: This bit is read only, but can be cleared by writing 1 to it.
0
1
read-only
0
nCTS input has not change state
#0
1
nCTS input has change state
#1
CTSSTS
nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled, and nCTS multi-function port is selected.
4
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
UART_TOUT
UART_TOUT
UART Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time.
8
8
read-write
TOIC
Time-out Interrupt Comparator\n
0
8
read-write
USBD
USBD Register Map
USBD
0x0
0x0
0x4
registers
n
0x10
0x234
registers
n
0x248
0x3C
registers
n
0x700
0x8
registers
n
0x8
0x4
registers
n
BUSINTEN
USBD_BUSINTEN
USB Bus Interrupt Enable Register
0x14
-1
read-write
n
0x0
0x0
DMADONEIEN
DMA Completion Interrupt \nThis bit enables the DMA completion interrupt\n
5
1
read-write
0
DMA completion interrupt Disabled
#0
1
DMA completion interrupt Enabled
#1
HISPDIEN
High-speed Settle \nThis bit enables the high-speed settle interrupt.\n
4
1
read-write
0
High-speed settle interrupt Disabled
#0
1
High-speed settle interrupt Enabled
#1
PHYCLKVLDIEN
Usable Clock Interrupt\nThis bit enables the usable clock interrupt.\n
6
1
read-write
0
Usable clock interrupt Disabled
#0
1
Usable clock interrupt Enabled
#1
RESUMEIEN
Resume \nThis bit enables the Resume interrupt.\n
2
1
read-write
0
Resume interrupt Disabled
#0
1
Resume interrupt Enabled
#1
RSTIEN
Reset Status \nThis bit enables the USB-Reset interrupt.\n
1
1
read-write
0
USB-Reset interrupt Disabled
#0
1
USB-Reset interrupt Enabled
#1
SOFIEN
SOF Interrupt\nThis bit enables the SOF interrupt.\n
0
1
read-write
0
SOF interrupt Disabled
#0
1
SOF interrupt Enabled
#1
SUSPENDIEN
Suspend Request \nThis bit enables the Suspend interrupt.\n
3
1
read-write
0
Suspend interrupt Disabled
#0
1
Suspend interrupt Enabled
#1
VBUSDETIEN
VBUS Detection Interrupt Enable Control\nThis bit enables the VBUS floating detection interrupt.\n
8
1
read-write
0
VBUS floating detection interrupt Disabled
#0
1
VBUS floating detection interrupt Enabled
#1
BUSINTSTS
USBD_BUSINTSTS
USB Bus Interrupt Status Register
0x10
read-write
n
0x0
0x0
DMADONEIF
DMA Completion Interrupt \n Write 1 to clear this bit to 0.
5
1
read-write
0
No DMA transfer over
#0
1
DMA transfer is over
#1
HISPDIF
High-speed Settle \n Write 1 to clear this bit to 0.
4
1
read-write
0
No valid high-speed reset protocol is detected
#0
1
Valid high-speed reset protocol is over and the device has settled in high-speed
#1
PHYCLKVLDIF
Usable Clock Interrupt \n Write 1 to clear this bit to 0.
6
1
read-write
0
Usable clock is not available
#0
1
Usable clock is available from the transceiver
#1
RESUMEIF
Resume \nWhen set, this bit indicates that a device resume has occurred.\n Write 1 to clear this bit to 0.
2
1
read-write
0
No device resume has occurred
#0
1
Device resume has occurred
#1
RSTIF
Reset Status \nWhen set, this bit indicates that either the USB root port reset is end.\n Write 1 to clear this bit to 0.
1
1
read-write
0
No USB root port reset is end
#0
1
USB root port reset is end
#1
SOFIF
SOF Receive Control\nThis bit indicates when a start-of-frame packet has been received. \n Write 1 to clear this bit to 0.
0
1
read-write
0
No start-of-frame packet has been received
#0
1
Start-of-frame packet has been received
#1
SUSPENDIF
Suspend Request \nThis bit is set as default and it has to be cleared by writing '1' before the USB reset. This bit is also set when a USB Suspend request is detected from the host. \n Write 1 to clear this bit to 0.
3
1
read-write
0
No USB Suspend request is detected from the host
#0
1
USB Suspend request is detected from the host
#1
VBUSDETIF
VBUS Detection Interrupt Status \n Write 1 to clear this bit to 0.
8
1
read-write
0
No VBUS is plug-in
#0
1
VBUS is plug-in
#1
CEPBUFEND
USBD_CEPBUFEND
Control Endpoint RAM End Address Register
0x58
read-write
n
0x0
0x0
EADDR
Control-endpoint End Address\nThis is the end-address of the RAM space allocated for the control-endpoint.
0
12
read-write
CEPBUFSTART
USBD_CEPBUFSTART
Control Endpoint RAM Start Address Register
0x54
read-write
n
0x0
0x0
SADDR
Control-endpoint Start Address\nThis is the start-address of the RAM space allocated for the control-endpoint.
0
12
read-write
CEPCTL
USBD_CEPCTL
Control-endpoint Control Register
0x2C
read-write
n
0x0
0x0
FLUSH
CEP-fLUSH Bit \n
3
1
read-write
0
No packet buffer and its corresponding USBD_CEPDATCNT register to be cleared
#0
1
The packet buffer and its corresponding USBD_CEPDATCNT register to be cleared. This bit is self-cleared
#1
NAKCLR
No Acknowledge Control\nThis bit plays a crucial role in any control transfer. \nNote: This bit can be updated only when CPU writes data[1:0] is 0x2 or 0x0.
0
1
read-write
0
The bit is being cleared by the local CPU by writing zero, the USB device controller will be responding with NAKs for the subsequent status phase. This mechanism holds the host from moving to the next request, until the local CPU is also ready to process the next request
#0
1
This bit is set to one by the USB device controller, whenever a setup token is received. The local CPU can take its own time to finish off any house-keeping work based on the request and then clear this bit
#1
STALLEN
Stall Enable Control\nWhen this stall bit is set, the control endpoint sends a stall handshake in response to any in or out token thereafter. This is typically used for response to invalid/unsupported requests. When this bit is being set the NAK clear bit has to be cleared at the same time since the NAK clear bit has highest priority than STALL. It is automatically cleared on receipt of a next setup-token. Thus, the local CPU does not need to write again to clear this bit.\nNote: This bit can be updated only when CPU writes data[1:0] 0x2 or 0x0.
1
1
read-write
0
No sends a stall handshake in response to any in or out token thereafter
#0
1
The control endpoint sends a stall handshake in response to any in or out token thereafter
#1
ZEROLEN
Zero Packet Length\nThis bit is valid for Auto Validation mode only. \n
2
1
read-write
0
No zero length packet to the host during Data stage to an IN token
#0
1
USB device controller can send a zero length packet to the host during Data stage to an IN token. This bit gets cleared once the zero length data packet is sent. Thus, the local CPU does not need to write again to clear this bit
#1
CEPDAT
USBD_CEPDAT
Control-endpoint Data Buffer
0x28
read-write
n
0x0
0x0
DAT
Control-endpoint Data Buffer \nControl endpoint data buffer for the buffer transaction (read or write).\nOnly word or byte access is supported.
0
32
read-write
CEPDATCNT
USBD_CEPDATCNT
Control-endpoint Data Count
0x40
read-only
n
0x0
0x0
DATCNT
Control-endpoint Data Count \nThe USB device controller maintains the count of the data of control-endpoint.
0
16
read-only
CEPINTEN
USBD_CEPINTEN
Control-endpoint Interrupt Enable Control Register
0x30
read-write
n
0x0
0x0
BUFEMPTYIEN
Buffer Empty Interrupt \n
12
1
read-write
0
The buffer empty interrupt in Control Endpoint Disabled
#0
1
The buffer empty interrupt in Control Endpoint Enabled
#1
BUFFULLIEN
Buffer Full Interrupt \n
11
1
read-write
0
The buffer full interrupt in Control Endpoint Disabled
#0
1
The buffer full interrupt in Control Endpoint Enabled
#1
ERRIEN
USB Error Interrupt \n
9
1
read-write
0
The USB Error interrupt in Control Endpoint Disabled
#0
1
The USB Error interrupt in Control Endpoint Enabled
#1
INTKIEN
in Token Interrupt \n
3
1
read-write
0
The IN token interrupt in Control Endpoint Disabled
#0
1
The IN token interrupt in Control Endpoint Enabled
#1
NAKIEN
NAK Sent Interrupt \n
7
1
read-write
0
The NAK sent interrupt in Control Endpoint Disabled
#0
1
The NAK sent interrupt in Control Endpoint Enabled
#1
OUTTKIEN
Out Token Interrupt \n
2
1
read-write
0
The OUT token interrupt in Control Endpoint Disabled
#0
1
The OUT token interrupt in Control Endpoint Enabled
#1
PINGIEN
Ping Token Interrupt \n
4
1
read-write
0
The ping token interrupt in Control Endpoint Disabled
#0
1
The ping token interrupt Control Endpoint Enabled
#1
RXPKIEN
Data Packet Received Interrupt \n
6
1
read-write
0
The data received interrupt in Control Endpoint Disabled
#0
1
The data received interrupt in Control Endpoint Enabled
#1
SETUPPKIEN
Setup Packet Interrupt \n
1
1
read-write
0
The SETUP packet interrupt in Control Endpoint Disabled
#0
1
The SETUP packet interrupt in Control Endpoint Enabled
#1
SETUPTKIEN
Setup Token Interrupt Enable Bit \n
0
1
read-write
0
The SETUP token interrupt in Control Endpoint Disabled
#0
1
The SETUP token interrupt in Control Endpoint Enabled
#1
STALLIEN
STALL Sent Interrupt \n
8
1
read-write
0
The STALL sent interrupt in Control Endpoint Disabled
#0
1
The STALL sent interrupt in Control Endpoint Enabled
#1
STSDONEIEN
Status Completion Interrupt \n
10
1
read-write
0
The Status Completion interrupt in Control Endpoint Disabled
#0
1
The Status Completion interrupt in Control Endpoint Enabled
#1
TXPKIEN
Data Packet Transmitted Interrupt \n
5
1
read-write
0
The data packet transmitted interrupt in Control Endpoint Disabled
#0
1
The data packet transmitted interrupt in Control Endpoint Enabled
#1
CEPINTSTS
USBD_CEPINTSTS
Control-endpoint Interrupt Status
0x34
-1
read-write
n
0x0
0x0
BUFEMPTYIF
Buffer Empty Interrupt \nNote: Write 1 to clear this bit to 0.
12
1
read-write
0
The control-endpoint buffer is not empty
#0
1
The control-endpoint buffer is empty
#1
BUFFULLIF
Buffer Full Interrupt \nNote: Write 1 to clear this bit to 0.
11
1
read-write
0
The control-endpoint buffer is not full
#0
1
The control-endpoint buffer is full
#1
ERRIF
USB Error Interrupt\nNote: Write 1 to clear this bit to 0.
9
1
read-write
0
No error had occurred during the transaction
#0
1
An error had occurred during the transaction
#1
INTKIF
in Token Interrupt \n Write 1 to clear this bit to 0.
3
1
read-write
0
The control-endpoint does not receive an IN token from the host
#0
1
The control-endpoint receives an IN token from the host
#1
NAKIF
NAK Sent Interrupt \nNote: Write 1 to clear this bit to 0.
7
1
read-write
0
No NAK-token is sent in response to an IN/OUT token
#0
1
A NAK-token is sent in response to an IN/OUT token
#1
OUTTKIF
Out Token Interrupt \nNote: Write 1 to clear this bit to 0.
2
1
read-write
0
The control-endpoint does not receive an OUT token from the host
#0
1
The control-endpoint receives an OUT token from the host
#1
PINGIF
Ping Token Interrupt \nNote: Write 1 to clear this bit to 0.
4
1
read-write
0
The control-endpoint does not receive a ping token from the host
#0
1
The control-endpoint receives a ping token from the host
#1
RXPKIF
Data Packet Received Interrupt \nNote: Write 1 to clear this bit to 0.
6
1
read-write
0
No data packet is successfully received from the host for an OUT-token and an ACK is sent to the host
#0
1
A data packet is successfully received from the host for an OUT-token and an ACK is sent to the host
#1
SETUPPKIF
Setup Packet Interrupt \nThis bit must be cleared (by writing 1) before the next setup packet can be received. If the bit is not cleared, then the successive setup packets will be overwritten in the setup packet buffer.\nNote: Write 1 to clear this bit to 0.
1
1
read-write
0
No setup packet has been received from the host
#0
1
A setup packet has been received from the host
#1
SETUPTKIF
Setup Token Interrupt \nNote: Write 1 to clear this bit to 0.
0
1
read-write
0
No setup token is received
#0
1
A setup token is received. Writing 1 clears this status bit
#1
STALLIF
STALL Sent Interrupt \nNote: Write 1 to clear this bit to 0.
8
1
read-write
0
No stall-token is sent in response to an IN/OUT token
#0
1
A stall-token is sent in response to an IN/OUT token
#1
STSDONEIF
Status Completion Interrupt \nNote: Write 1 to clear this bit to 0.
10
1
read-write
0
No USB transaction has completed successfully
#0
1
The status stage of a USB transaction has completed successfully
#1
TXPKIF
Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0.
5
1
read-write
0
No data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same
#0
1
A data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same
#1
CEPRXCNT
USBD_CEPRXCNT
Control-endpoint Out-transfer Data Count
0x3C
read-only
n
0x0
0x0
RXCNT
Out-transfer Data Count \nThe USB device controller maintains the count of the data received in case of an out transfer, during the control transfer.
0
8
read-only
CEPTXCNT
USBD_CEPTXCNT
Control-endpoint In-transfer Data Count
0x38
read-write
n
0x0
0x0
TXCNT
In-transfer Data Count\nThere is no mode selection for the control endpoint (but it operates like manual mode).The local-CPU has to fill the control-endpoint buffer with the data to be sent for an in-token and to write the count of bytes in this register. When zero is written into this field, a zero length packet is sent to the host. When the count written in the register is more than the MPS, the data sent will be of only MPS.
0
8
read-write
DMAADDR
USBD_DMAADDR
AHB DMA Address Register
0x700
read-write
n
0x0
0x0
DMAADDR
DMAADDR\nThe register specifies the address from which the DMA has to read / write. The address must WORD (32-bit) aligned.
0
32
read-write
DMACNT
USBD_DMACNT
DMA Count Register
0x60
read-write
n
0x0
0x0
DMACNT
DMA Transfer Count\nThe transfer count of the DMA operation to be performed is written to this register.
0
20
read-write
DMACTL
USBD_DMACTL
DMA Control Status Register
0x5C
read-write
n
0x0
0x0
DMAEN
DMA Enable Bit\n
5
1
read-write
0
DMA function Disabled
#0
1
DMA function Enabled
#1
DMARD
DMA Operation\n
4
1
read-write
0
The operation is a DMA write (read from USB buffer). DMA will check endpoint data available count (USBD_EPxDATCNT) according to EPNM setting before to perform DMA write operation
#0
1
The operation is a DMA read (write to USB buffer)
#1
DMARST
Reset DMA State Machine\n
7
1
read-write
0
No reset the DMA state machine
#0
1
Reset the DMA state machine
#1
EPNUM
DMA Endpoint Address Bits\nUsed to define the Endpoint Address
0
4
read-write
SGEN
Scatter Gather Function Enable Bit\n
6
1
read-write
0
Scatter gather function Disabled
#0
1
Scatter gather function Enabled
#1
EPABUFEND
USBD_EPABUFEND
Endpoint A RAM End Address Register
0x88
read-write
n
0x0
0x0
EADDR
Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L.
0
12
read-write
EPABUFSTART
USBD_EPABUFSTART
Endpoint A RAM Start Address Register
0x84
read-write
n
0x0
0x0
SADDR
Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L.
0
12
read-write
EPACFG
USBD_EPACFG
Endpoint A Configuration Register
0x80
-1
read-write
n
0x0
0x0
EPDIR
Endpoint Direction\n A maximum of one OUT and IN endpoint is allowed for each endpoint number.
3
1
read-write
0
out-endpoint (Host OUT to Device)
#0
1
in-endpoint (Host IN to Device)
#1
EPEN
Endpoint Valid\nWhen set, this bit enables this endpoint. This bit has no effect on Endpoint 0, which is always enabled.\n
0
1
read-write
0
The endpoint Disabled
#0
1
The endpoint Enabled
#1
EPNUM
Endpoint Number\nThis field selects the number of the endpoint. Valid numbers 1 to 15.\n Do not support two endpoints have same endpoint number.
4
4
read-write
EPTYPE
Endpoint Type\nThis field selects the type of this endpoint. Endpoint 0 is forced to a Control type. \n
1
2
read-write
0
Reserved
#00
1
Bulk
#01
2
Interrupt
#10
3
Isochronous
#11
EPADAT
USBD_EPADAT
Endpoint A Data Register
0x64
read-write
n
0x0
0x0
EPDAT
Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\n Only word or byte access are supported.
0
32
read-write
EPADATCNT
USBD_EPADATCNT
Endpoint A Data Available Count Register
0x70
read-only
n
0x0
0x0
DATCNT
Data Count\nFor an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.), this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.), this register returns the number of received valid bytes in the Host OUT transfer.
0
16
read-only
DMALOOP
DMA Loop\nThis register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
16
15
read-only
EPAINTEN
USBD_EPAINTEN
Endpoint A Interrupt Enable Register
0x6C
read-write
n
0x0
0x0
BUFEMPTYIEN
Buffer Empty Interrupt\nWhen set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.\n
1
1
read-write
0
Buffer empty interrupt Disabled
#0
1
Buffer empty interrupt Enabled
#1
BUFFULLIEN
Buffer Full Interrupt \nWhen set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.\n
0
1
read-write
0
Buffer full interrupt Disabled
#0
1
Buffer full interrupt Enabled
#1
ERRIEN
ERR Interrupt Enable Bit\nWhen set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.\n
11
1
read-write
0
Error event interrupt Disabled
#0
1
Error event interrupt Enabled
#1
INTKIEN
Data IN Token Interrupt Enable Bit\nWhen set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.\n
6
1
read-write
0
Data IN token interrupt Disabled
#0
1
Data IN token interrupt Enabled
#1
NAKIEN
USB NAK Sent Interrupt Enable Bit \nWhen set, this bit enables a local interrupt to be set when a NAK token is sent to the host.\n
8
1
read-write
0
NAK token interrupt Disabled
#0
1
NAK token interrupt Enabled
#1
NYETIEN
NYET Interrupt Enable Bit\nWhen set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.\n
10
1
read-write
0
NYET condition interrupt Disabled
#0
1
NYET condition interrupt Enabled
#1
OUTTKIEN
Data OUT Token Interrupt Enable Bit \nWhen set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.\n
5
1
read-write
0
Data OUT token interrupt Disabled
#0
1
Data OUT token interrupt Enabled
#1
PINGIEN
PING Token Interrupt Enable Bit \nWhen set, this bit enables a local interrupt to be set when a PING token has been received from the host.\n
7
1
read-write
0
PING token interrupt Disabled
#0
1
PING token interrupt Enabled
#1
RXPKIEN
Data Packet Received Interrupt Enable Bit \nWhen set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.\n
4
1
read-write
0
Data packet has been transmitted to the host interrupt Disabled
#0
1
Data packet has been transmitted to the host interrupt Enabled
#1
SHORTRXIEN
Bulk Out Short Packet Interrupt Enable Bit\nWhen set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.\n
12
1
read-write
0
Bulk out interrupt Disabled
#0
1
Bulk out interrupt Enabled
#1
SHORTTXIEN
Short Packet Transferred Interrupt Enable Bit \nWhen set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.\n
2
1
read-write
0
Short data packet interrupt Disabled
#0
1
Short data packet interrupt Enabled
#1
STALLIEN
USB STALL Sent Interrupt Enable Bit \nWhen set, this bit enables a local interrupt to be set when a stall token is sent to the host.\n
9
1
read-write
0
STALL token interrupt Disabled
#0
1
STALL token interrupt Enabled
#1
TXPKIEN
Data Packet Transmitted Interrupt Enable Bit \nWhen set, this bit enables a local interrupt to be set when a data packet has been received from the host.\n
3
1
read-write
0
Data packet has been received from the host interrupt Disabled
#0
1
Data packet has been received from the host interrupt Enabled
#1
EPAINTSTS
USBD_EPAINTSTS
Endpoint A Interrupt Status Register
0x68
-1
read-write
n
0x0
0x0
BUFEMPTYIF
Buffer Empty\nFor an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes. \nNote: This bit is read-only.
1
1
read-write
0
The endpoint buffer is not empty.\nThe currently selected buffer does not have a count of 0
#0
1
The endpoint buffer is empty.\nThe currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read)
#1
BUFFULLIF
Buffer Full \nFor an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write). For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).\nNote: This bit is read-only.
0
1
read-write
0
The endpoint packet buffer is not full
#0
1
The endpoint packet buffer is full
#1
ERRIF
ERR Sent \n Write 1 to clear this bit to 0.
11
1
read-write
0
No any error in the transaction
#0
1
There occurs any error in the transaction
#1
INTKIF
Data IN Token Interrupt \n Write 1 to clear this bit to 0.
6
1
read-write
0
No Data IN token has been received from the host
#0
1
A Data IN token has been received from the host
#1
NAKIF
USB NAK Sent\n Write 1 to clear this bit to 0.
8
1
read-write
0
The last USB IN packet could be provided, and was acknowledged with an ACK
#0
1
The last USB IN packet could not be provided, and was acknowledged with a NAK
#1
NYETIF
NYET Sent \n Write 1 to clear this bit to 0.
10
1
read-write
0
The space available in the RAM is sufficient to accommodate the next on coming data packet
#0
1
The space available in the RAM is not sufficient to accommodate the next on coming data packet
#1
OUTTKIF
Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0.
5
1
read-write
0
A Data OUT token has not been received from the host
#0
1
A Data OUT token has been received from the host. This bit also set by PING token (in high-speed only)
#1
PINGIF
PING Token Interrupt \n Write 1 to clear this bit to 0.
7
1
read-write
0
A Data PING token has not been received from the host
#0
1
A Data PING token has been received from the host
#1
RXPKIF
Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0.
4
1
read-write
0
No data packet is received from the host by the endpoint
#0
1
A data packet is received from the host by the endpoint
#1
SHORTRXIF
Bulk Out Short Packet Received\n Write 1 to clear this bit to 0.
12
1
read-write
0
No bulk out short packet is received
#0
1
Received bulk out short packet (including zero length packet)
#1
SHORTTXIF
Short Packet Transferred Interrupt \n Note: Write 1 to clear this bit to 0.
2
1
read-write
0
The length of the last packet was not less than the Maximum Packet Size (EPMPS)
#0
1
The length of the last packet was less than the Maximum Packet Size (EPMPS)
#1
STALLIF
USB STALL Sent\n Write 1 to clear this bit to 0.
9
1
read-write
0
The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL
#0
1
The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL
#1
TXPKIF
Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0.
3
1
read-write
0
No data packet is transmitted from the endpoint to the host
#0
1
A data packet is transmitted from the endpoint to the host
#1
EPAMPS
USBD_EPAMPS
Endpoint A Maximum Packet Size Register
0x78
read-write
n
0x0
0x0
EPMPS
Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint.
0
11
read-write
EPARSPCTL
USBD_EPARSPCTL
Endpoint A Response Control Register
0x74
read-write
n
0x0
0x0
DISBUF
Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet. The received packet size is reference USBD_EPxDATCNT register.\n
7
1
read-write
0
Buffer Not Disabled when Bulk-OUT short packet is received
#0
1
Buffer Disabled when Bulk-OUT short packet is received
#1
FLUSH
Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared. This bit is self-cleared. This bit should always be written after a configuration event.\n
0
1
read-write
0
The packet buffer is not flushed
#0
1
The packet buffer is flushed by user
#1
HALT
Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host. When an Endpoint Set Feature (ep_halt) is detected by the local CPU, it must write a '1' to this bit.\n
4
1
read-write
0
Do not send a STALL handshake as response to the token from the host
#0
1
Send a STALL handshake as response to the token from the host
#1
MODE
Mode Control\nThe two bits determine the operation mode of the in-endpoint. \nNote: These bits are not valid for an out-endpoint. The auto validate mode will be activated when the reserved mode is selected.
1
2
read-write
0
Auto-Validate Mode
#00
1
Manual-Validate Mode
#01
2
Fly Mode
#10
3
Reserved
#11
SHORTTXEN
Short Packet Transfer Enable Bit\nThis bit is applicable only in case of Auto-Validate Method. This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer. This bit gets cleared once the data packet is sent.\n
6
1
read-write
0
Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint
#0
1
Validate any remaining data in the buffer which is not equal to the MPS of the endpoint
#1
TOGGLE
Endpoint Toggle
This bit is used to clear the endpoint data toggle bit. Reading this bit returns the current state of the endpoint data toggle bit.
The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host. Only when toggle bit is 1 , this bit can be written into the inversed write data bit[3].
3
1
read-write
0
Do not clear the endpoint data toggle bit
#0
1
Clear the endpoint data toggle bit
#1
ZEROLEN
Zero Length\nThis bit is used to send a zero-length packet response to an IN-token. When this bit is set, a zero packet is sent to the host on reception of an IN-token. This bit gets cleared once the zero length data packet is sent.\n
5
1
read-write
0
A zero packet is not sent to the host on reception of an IN-token
#0
1
A zero packet is sent to the host on reception of an IN-token
#1
EPATXCNT
USBD_EPATXCNT
Endpoint A Transfer Count Register
0x7C
read-write
n
0x0
0x0
TXCNT
Endpoint Transfer Count\nFor IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints, this field has no effect.
0
11
read-write
EPBBUFEND
USBD_EPBBUFEND
Endpoint B RAM End Address Register
0xB0
read-write
n
0x0
0x0
EPBBUFSTART
USBD_EPBBUFSTART
Endpoint B RAM Start Address Register
0xAC
read-write
n
0x0
0x0
EPBCFG
USBD_EPBCFG
Endpoint B Configuration Register
0xA8
read-write
n
0x0
0x0
EPBDAT
USBD_EPBDAT
Endpoint B Data Register
0x8C
read-write
n
0x0
0x0
EPBDATCNT
USBD_EPBDATCNT
Endpoint B Data Available Count Register
0x98
read-write
n
0x0
0x0
EPBINTEN
USBD_EPBINTEN
Endpoint B Interrupt Enable Register
0x94
read-write
n
0x0
0x0
EPBINTSTS
USBD_EPBINTSTS
Endpoint B Interrupt Status Register
0x90
read-write
n
0x0
0x0
EPBMPS
USBD_EPBMPS
Endpoint B Maximum Packet Size Register
0xA0
read-write
n
0x0
0x0
EPBRSPCTL
USBD_EPBRSPCTL
Endpoint B Response Control Register
0x9C
read-write
n
0x0
0x0
EPBTXCNT
USBD_EPBTXCNT
Endpoint B Transfer Count Register
0xA4
read-write
n
0x0
0x0
EPCBUFEND
USBD_EPCBUFEND
Endpoint C RAM End Address Register
0xD8
read-write
n
0x0
0x0
EPCBUFSTART
USBD_EPCBUFSTART
Endpoint C RAM Start Address Register
0xD4
read-write
n
0x0
0x0
EPCCFG
USBD_EPCCFG
Endpoint C Configuration Register
0xD0
read-write
n
0x0
0x0
EPCDAT
USBD_EPCDAT
Endpoint C Data Register
0xB4
read-write
n
0x0
0x0
EPCDATCNT
USBD_EPCDATCNT
Endpoint C Data Available Count Register
0xC0
read-write
n
0x0
0x0
EPCINTEN
USBD_EPCINTEN
Endpoint C Interrupt Enable Register
0xBC
read-write
n
0x0
0x0
EPCINTSTS
USBD_EPCINTSTS
Endpoint C Interrupt Status Register
0xB8
read-write
n
0x0
0x0
EPCMPS
USBD_EPCMPS
Endpoint C Maximum Packet Size Register
0xC8
read-write
n
0x0
0x0
EPCRSPCTL
USBD_EPCRSPCTL
Endpoint C Response Control Register
0xC4
read-write
n
0x0
0x0
EPCTXCNT
USBD_EPCTXCNT
Endpoint C Transfer Count Register
0xCC
read-write
n
0x0
0x0
EPDBUFEND
USBD_EPDBUFEND
Endpoint D RAM End Address Register
0x100
read-write
n
0x0
0x0
EPDBUFSTART
USBD_EPDBUFSTART
Endpoint D RAM Start Address Register
0xFC
read-write
n
0x0
0x0
EPDCFG
USBD_EPDCFG
Endpoint D Configuration Register
0xF8
read-write
n
0x0
0x0
EPDDAT
USBD_EPDDAT
Endpoint D Data Register
0xDC
read-write
n
0x0
0x0
EPDDATCNT
USBD_EPDDATCNT
Endpoint D Data Available Count Register
0xE8
read-write
n
0x0
0x0
EPDINTEN
USBD_EPDINTEN
Endpoint D Interrupt Enable Register
0xE4
read-write
n
0x0
0x0
EPDINTSTS
USBD_EPDINTSTS
Endpoint D Interrupt Status Register
0xE0
read-write
n
0x0
0x0
EPDMPS
USBD_EPDMPS
Endpoint D Maximum Packet Size Register
0xF0
read-write
n
0x0
0x0
EPDRSPCTL
USBD_EPDRSPCTL
Endpoint D Response Control Register
0xEC
read-write
n
0x0
0x0
EPDTXCNT
USBD_EPDTXCNT
Endpoint D Transfer Count Register
0xF4
read-write
n
0x0
0x0
EPEBUFEND
USBD_EPEBUFEND
Endpoint E RAM End Address Register
0x128
read-write
n
0x0
0x0
EPEBUFSTART
USBD_EPEBUFSTART
Endpoint E RAM Start Address Register
0x124
read-write
n
0x0
0x0
EPECFG
USBD_EPECFG
Endpoint E Configuration Register
0x120
read-write
n
0x0
0x0
EPEDAT
USBD_EPEDAT
Endpoint E Data Register
0x104
read-write
n
0x0
0x0
EPEDATCNT
USBD_EPEDATCNT
Endpoint E Data Available Count Register
0x110
read-write
n
0x0
0x0
EPEINTEN
USBD_EPEINTEN
Endpoint E Interrupt Enable Register
0x10C
read-write
n
0x0
0x0
EPEINTSTS
USBD_EPEINTSTS
Endpoint E Interrupt Status Register
0x108
read-write
n
0x0
0x0
EPEMPS
USBD_EPEMPS
Endpoint E Maximum Packet Size Register
0x118
read-write
n
0x0
0x0
EPERSPCTL
USBD_EPERSPCTL
Endpoint E Response Control Register
0x114
read-write
n
0x0
0x0
EPETXCNT
USBD_EPETXCNT
Endpoint E Transfer Count Register
0x11C
read-write
n
0x0
0x0
EPFBUFEND
USBD_EPFBUFEND
Endpoint F RAM End Address Register
0x150
read-write
n
0x0
0x0
EPFBUFSTART
USBD_EPFBUFSTART
Endpoint F RAM Start Address Register
0x14C
read-write
n
0x0
0x0
EPFCFG
USBD_EPFCFG
Endpoint F Configuration Register
0x148
read-write
n
0x0
0x0
EPFDAT
USBD_EPFDAT
Endpoint F Data Register
0x12C
read-write
n
0x0
0x0
EPFDATCNT
USBD_EPFDATCNT
Endpoint F Data Available Count Register
0x138
read-write
n
0x0
0x0
EPFINTEN
USBD_EPFINTEN
Endpoint F Interrupt Enable Register
0x134
read-write
n
0x0
0x0
EPFINTSTS
USBD_EPFINTSTS
Endpoint F Interrupt Status Register
0x130
read-write
n
0x0
0x0
EPFMPS
USBD_EPFMPS
Endpoint F Maximum Packet Size Register
0x140
read-write
n
0x0
0x0
EPFRSPCTL
USBD_EPFRSPCTL
Endpoint F Response Control Register
0x13C
read-write
n
0x0
0x0
EPFTXCNT
USBD_EPFTXCNT
Endpoint F Transfer Count Register
0x144
read-write
n
0x0
0x0
EPGBUFEND
USBD_EPGBUFEND
Endpoint G RAM End Address Register
0x178
read-write
n
0x0
0x0
EPGBUFSTART
USBD_EPGBUFSTART
Endpoint G RAM Start Address Register
0x174
read-write
n
0x0
0x0
EPGCFG
USBD_EPGCFG
Endpoint G Configuration Register
0x170
read-write
n
0x0
0x0
EPGDAT
USBD_EPGDAT
Endpoint G Data Register
0x154
read-write
n
0x0
0x0
EPGDATCNT
USBD_EPGDATCNT
Endpoint G Data Available Count Register
0x160
read-write
n
0x0
0x0
EPGINTEN
USBD_EPGINTEN
Endpoint G Interrupt Enable Register
0x15C
read-write
n
0x0
0x0
EPGINTSTS
USBD_EPGINTSTS
Endpoint G Interrupt Status Register
0x158
read-write
n
0x0
0x0
EPGMPS
USBD_EPGMPS
Endpoint G Maximum Packet Size Register
0x168
read-write
n
0x0
0x0
EPGRSPCTL
USBD_EPGRSPCTL
Endpoint G Response Control Register
0x164
read-write
n
0x0
0x0
EPGTXCNT
USBD_EPGTXCNT
Endpoint G Transfer Count Register
0x16C
read-write
n
0x0
0x0
EPHBUFEND
USBD_EPHBUFEND
Endpoint H RAM End Address Register
0x1A0
read-write
n
0x0
0x0
EPHBUFSTART
USBD_EPHBUFSTART
Endpoint H RAM Start Address Register
0x19C
read-write
n
0x0
0x0
EPHCFG
USBD_EPHCFG
Endpoint H Configuration Register
0x198
read-write
n
0x0
0x0
EPHDAT
USBD_EPHDAT
Endpoint H Data Register
0x17C
read-write
n
0x0
0x0
EPHDATCNT
USBD_EPHDATCNT
Endpoint H Data Available Count Register
0x188
read-write
n
0x0
0x0
EPHINTEN
USBD_EPHINTEN
Endpoint H Interrupt Enable Register
0x184
read-write
n
0x0
0x0
EPHINTSTS
USBD_EPHINTSTS
Endpoint H Interrupt Status Register
0x180
read-write
n
0x0
0x0
EPHMPS
USBD_EPHMPS
Endpoint H Maximum Packet Size Register
0x190
read-write
n
0x0
0x0
EPHRSPCTL
USBD_EPHRSPCTL
Endpoint H Response Control Register
0x18C
read-write
n
0x0
0x0
EPHTXCNT
USBD_EPHTXCNT
Endpoint H Transfer Count Register
0x194
read-write
n
0x0
0x0
EPIBUFEND
USBD_EPIBUFEND
Endpoint I RAM End Address Register
0x1C8
read-write
n
0x0
0x0
EPIBUFSTART
USBD_EPIBUFSTART
Endpoint I RAM Start Address Register
0x1C4
read-write
n
0x0
0x0
EPICFG
USBD_EPICFG
Endpoint I Configuration Register
0x1C0
read-write
n
0x0
0x0
EPIDAT
USBD_EPIDAT
Endpoint I Data Register
0x1A4
read-write
n
0x0
0x0
EPIDATCNT
USBD_EPIDATCNT
Endpoint I Data Available Count Register
0x1B0
read-write
n
0x0
0x0
EPIINTEN
USBD_EPIINTEN
Endpoint I Interrupt Enable Register
0x1AC
read-write
n
0x0
0x0
EPIINTSTS
USBD_EPIINTSTS
Endpoint I Interrupt Status Register
0x1A8
read-write
n
0x0
0x0
EPIMPS
USBD_EPIMPS
Endpoint I Maximum Packet Size Register
0x1B8
read-write
n
0x0
0x0
EPIRSPCTL
USBD_EPIRSPCTL
Endpoint I Response Control Register
0x1B4
read-write
n
0x0
0x0
EPITXCNT
USBD_EPITXCNT
Endpoint I Transfer Count Register
0x1BC
read-write
n
0x0
0x0
EPJBUFEND
USBD_EPJBUFEND
Endpoint J RAM End Address Register
0x1F0
read-write
n
0x0
0x0
EPJBUFSTART
USBD_EPJBUFSTART
Endpoint J RAM Start Address Register
0x1EC
read-write
n
0x0
0x0
EPJCFG
USBD_EPJCFG
Endpoint J Configuration Register
0x1E8
read-write
n
0x0
0x0
EPJDAT
USBD_EPJDAT
Endpoint J Data Register
0x1CC
read-write
n
0x0
0x0
EPJDATCNT
USBD_EPJDATCNT
Endpoint J Data Available Count Register
0x1D8
read-write
n
0x0
0x0
EPJINTEN
USBD_EPJINTEN
Endpoint J Interrupt Enable Register
0x1D4
read-write
n
0x0
0x0
EPJINTSTS
USBD_EPJINTSTS
Endpoint J Interrupt Status Register
0x1D0
read-write
n
0x0
0x0
EPJMPS
USBD_EPJMPS
Endpoint J Maximum Packet Size Register
0x1E0
read-write
n
0x0
0x0
EPJRSPCTL
USBD_EPJRSPCTL
Endpoint J Response Control Register
0x1DC
read-write
n
0x0
0x0
EPJTXCNT
USBD_EPJTXCNT
Endpoint J Transfer Count Register
0x1E4
read-write
n
0x0
0x0
EPKBUFEND
USBD_EPKBUFEND
Endpoint K RAM End Address Register
0x218
read-write
n
0x0
0x0
EPKBUFSTART
USBD_EPKBUFSTART
Endpoint K RAM Start Address Register
0x214
read-write
n
0x0
0x0
EPKCFG
USBD_EPKCFG
Endpoint K Configuration Register
0x210
read-write
n
0x0
0x0
EPKDAT
USBD_EPKDAT
Endpoint K Data Register
0x1F4
read-write
n
0x0
0x0
EPKDATCNT
USBD_EPKDATCNT
Endpoint K Data Available Count Register
0x200
read-write
n
0x0
0x0
EPKINTEN
USBD_EPKINTEN
Endpoint K Interrupt Enable Register
0x1FC
read-write
n
0x0
0x0
EPKINTSTS
USBD_EPKINTSTS
Endpoint K Interrupt Status Register
0x1F8
read-write
n
0x0
0x0
EPKMPS
USBD_EPKMPS
Endpoint K Maximum Packet Size Register
0x208
read-write
n
0x0
0x0
EPKRSPCTL
USBD_EPKRSPCTL
Endpoint K Response Control Register
0x204
read-write
n
0x0
0x0
EPKTXCNT
USBD_EPKTXCNT
Endpoint K Transfer Count Register
0x20C
read-write
n
0x0
0x0
EPLBUFEND
USBD_EPLBUFEND
Endpoint L RAM End Address Register
0x240
read-write
n
0x0
0x0
EPLBUFSTART
USBD_EPLBUFSTART
Endpoint L RAM Start Address Register
0x23C
read-write
n
0x0
0x0
EPLCFG
USBD_EPLCFG
Endpoint L Configuration Register
0x238
read-write
n
0x0
0x0
EPLDAT
USBD_EPLDAT
Endpoint L Data Register
0x21C
read-write
n
0x0
0x0
EPLDATCNT
USBD_EPLDATCNT
Endpoint L Data Available Count Register
0x228
read-write
n
0x0
0x0
EPLINTEN
USBD_EPLINTEN
Endpoint L Interrupt Enable Register
0x224
read-write
n
0x0
0x0
EPLINTSTS
USBD_EPLINTSTS
Endpoint L Interrupt Status Register
0x220
read-write
n
0x0
0x0
EPLMPS
USBD_EPLMPS
Endpoint L Maximum Packet Size Register
0x230
read-write
n
0x0
0x0
EPLRSPCTL
USBD_EPLRSPCTL
Endpoint L Response Control Register
0x22C
read-write
n
0x0
0x0
EPLTXCNT
USBD_EPLTXCNT
Endpoint L Transfer Count Register
0x234
read-write
n
0x0
0x0
FADDR
USBD_FADDR
USB Function Address Register
0x20
read-write
n
0x0
0x0
FADDR
USB Function Address\nThis field contains the current USB address of the device. This field is cleared when a root port reset is detected.
0
7
read-write
FRAMECNT
USBD_FRAMECNT
USB Frame Count Register
0x1C
read-only
n
0x0
0x0
FRAMECNT
Frame Counter\nThis field contains the frame count from the most recent start-of-frame packet.
3
11
read-only
MFRAMECNT
Micro-frame Counter\nThis field contains the micro-frame number for the frame number in the frame counter field.
0
3
read-only
GINTEN
USBD_GINTEN
Global Interrupt Enable Register
0x8
-1
read-write
n
0x0
0x0
CEPIEN
Control Endpoint Interrupt Enable Bit \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the control endpoint.\n
1
1
read-write
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
EPAIEN
Interrupt Enable Control for Endpoint a \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint A.\n
2
1
read-write
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
EPBIEN
Interrupt Enable Control for Endpoint B \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint B \n
3
1
read-write
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
EPCIEN
Interrupt Enable Control for Endpoint C \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint C\n
4
1
read-write
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
EPDIEN
Interrupt Enable Control for Endpoint D \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint D\n
5
1
read-write
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
EPEIEN
Interrupt Enable Control for Endpoint E \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint E\n
6
1
read-write
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
EPFIEN
Interrupt Enable Control for Endpoint F \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint F\n
7
1
read-write
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
EPGIEN
Interrupt Enable Control for Endpoint G\nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint G\n
8
1
read-write
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
EPHIEN
Interrupt Enable Control for Endpoint H \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint H\n
9
1
read-write
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
EPIIEN
Interrupt Enable Control for Endpoint I \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint I\n
10
1
read-write
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
EPJIEN
Interrupt Enable Control for Endpoint J \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint J\n
11
1
read-write
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
EPKIEN
Interrupt Enable Control for Endpoint K \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint K\n
12
1
read-write
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
EPLIEN
Interrupt Enable Control for Endpoint L \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint L\n
13
1
read-write
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
USBIEN
USB Interrupt Enable Bit \nWhen set, this bit enables a local interrupt to be generated when a USB event occurs on the bus.\n
0
1
read-write
0
The related interrupt Disabled
#0
1
The related interrupt Enabled
#1
GINTSTS
USBD_GINTSTS
Global Interrupt Status Register
0x0
read-only
n
0x0
0x0
CEPIF
Control Endpoint Interrupt \nThis bit conveys the interrupt status for control endpoint. When set, Control-ep's interrupt status register should be read to determine the cause of the interrupt.\n
1
1
read-only
0
No interrupt event occurred
#0
1
The related interrupt event is occurred
#1
EPAIF
Endpoints a Interrupt\nWhen set, the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt.\n
2
1
read-only
0
No interrupt event occurred
#0
1
The related interrupt event is occurred
#1
EPBIF
Endpoints B Interrupt\nWhen set, the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt.\n
3
1
read-only
0
No interrupt event occurred
#0
1
The related interrupt event is occurred
#1
EPCIF
Endpoints C Interrupt\nWhen set, the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt.\n
4
1
read-only
0
No interrupt event occurred
#0
1
The related interrupt event is occurred
#1
EPDIF
Endpoints D Interrupt\nWhen set, the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt.\n
5
1
read-only
0
No interrupt event occurred
#0
1
The related interrupt event is occurred
#1
EPEIF
Endpoints E Interrupt\nWhen set, the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt.\n
6
1
read-only
0
No interrupt event occurred
#0
1
The related interrupt event is occurred
#1
EPFIF
Endpoints F Interrupt\nWhen set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt.\n
7
1
read-only
0
No interrupt event occurred
#0
1
The related interrupt event is occurred
#1
EPGIF
Endpoints G Interrupt\nWhen set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt.\n
8
1
read-only
0
No interrupt event occurred
#0
1
The related interrupt event is occurred
#1
EPHIF
Endpoints H Interrupt\nWhen set, the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt.\n
9
1
read-only
0
No interrupt event occurred
#0
1
The related interrupt event is occurred
#1
EPIIF
Endpoints I Interrupt\nWhen set, the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt.\n
10
1
read-only
0
No interrupt event occurred
#0
1
The related interrupt event is occurred
#1
EPJIF
Endpoints J Interrupt\nWhen set, the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt.\n
11
1
read-only
0
No interrupt event occurred
#0
1
The related interrupt event is occurred
#1
EPKIF
Endpoints K Interrupt\nWhen set, the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt.\n
12
1
read-only
0
No interrupt event occurred
#0
1
The related interrupt event is occurred
#1
EPLIF
Endpoints L Interrupt\nWhen set, the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt.\n
13
1
read-only
0
No interrupt event occurred
#0
1
The related interrupt event is occurred
#1
USBIF
USB Interrupt \nThis bit conveys the interrupt status for USB specific events endpoint. When set, USB interrupt status register should be read to determine the cause of the interrupt.\n
0
1
read-only
0
No interrupt event occurred
#0
1
The related interrupt event is occurred
#1
OPER
USBD_OPER
USB Operational Register
0x18
-1
read-write
n
0x0
0x0
CURSPD
Current USB Speed\n
2
1
read-write
0
The device has settled in Full Speed
#0
1
The USB device controller has settled in High Speed
#1
HISPDEN
USB High-speed\n
1
1
read-write
0
The USB device controller suppresses the chirp-sequence during reset protocol, thereby allowing the USB device controller to settle in full-speed, even though it is connected to a USB2.0 Host
#0
1
The USB device controller initiates a chirp-sequence during reset protocol
#1
RESUMEEN
Generate Resume\n
0
1
read-write
0
No resume sequence to be initiated to the host
#0
1
A resume sequence to be initiated to the host if device remote wake-up is enabled. Note: This bit is self-cleared
#1
PHYCTL
USBD_PHYCTL
USB PHY Control Register
0x704
-1
read-write
n
0x0
0x0
DPPUEN
DP Pull-up\n
8
1
read-write
0
Pull-up resistor on D+ Disabled
#0
1
Pull-up resistor on D+ Enabled
#1
LOWPWREN
PHY Low Power Mode Enable Bit (Low Active)\nUSB PHY HS low power mode configuration control bit.\nWhen this bit is 0, USB PHY is in Low Power Mode and USB PHY TX driver is enable only when USB Device Controller (USBD) transmit the data out to USB bus. In this mode, HS signal quality is not guaranteed.\n
3
1
read-write
0
USB PHY Low Power Mode Enabled
#0
1
USB PHY Low Power Mode Disabled
#1
PHYEN
PHY Suspend Enable Bit\n
9
1
read-write
0
The USB PHY is suspend
#0
1
The USB PHY is not suspend
#1
VBUSDET
VBUS Status\n
31
1
read-write
0
The VBUS is not detected yet
#0
1
The VBUS is detected
#1
WKEN
Wake-up Enable Bit\n
24
1
read-write
0
The wake-up function Disabled
#0
1
The wake-up function Enabled
#1
SETUP1_0
USBD_SETUP1_0
Setup1 Setup0 Bytes
0x44
-1
read-only
n
0x0
0x0
SETUP0
Setup Byte 0[7:0]\nThis register provides byte 0 of the last setup packet received. For a Standard Device Request, the following bmRequestType information is returned.\nBit 7(Direction):\n
0
8
read-only
0
Host to device.\nStandard.\nDevice
0
1
Device to host.\nClass.\nnterface
1
10
Vendor.\nEndpoint
10
11
Reserved.\n:Other
11
SETUP1
Setup Byte 1[15:8]\nThis register provides byte 1 of the last setup packet received. For a Standard Device Request, the following bRequest Code information is returned. \n
8
8
read-only
0
Get Status
#00000000
1
Clear Feature
#00000001
2
Reserved
#00000010
3
Set Feature
#00000011
4
Reserved
#00000100
5
Set Address
#00000101
6
Get Descriptor
#00000110
7
Set Descriptor
#00000111
8
Get Configuration
#00001000
9
Set Configuration
#00001001
10
Get Interface
#00001010
11
Set Interface
#00001011
12
Synch Frame
#00001100
SETUP3_2
USBD_SETUP3_2
Setup3 Setup2 Bytes
0x48
-1
read-only
n
0x0
0x0
SETUP2
Setup Byte 2 [7:0]\nThis register provides byte 2 of the last setup packet received. For a Standard Device Request, the least significant byte of the wValue field is returned.
0
8
read-only
SETUP3
Setup Byte 3 [15:8]\nThis register provides byte 3 of the last setup packet received. For a Standard Device Request, the most significant byte of the wValue field is returned.
8
8
read-only
SETUP5_4
USBD_SETUP5_4
Setup5 Setup4 Bytes
0x4C
-1
read-only
n
0x0
0x0
SETUP4
Setup Byte 4[7:0] \nThis register provides byte 4 of the last setup packet received. For a Standard Device Request, the least significant byte of the wIndex is returned.
0
8
read-only
SETUP5
Setup Byte 5[15:8] \nThis register provides byte 5 of the last setup packet received. For a Standard Device Request, the most significant byte of the wIndex field is returned.
8
8
read-only
SETUP7_6
USBD_SETUP7_6
Setup7 Setup6 Bytes
0x50
-1
read-only
n
0x0
0x0
SETUP6
Setup Byte 6[7:0] \nThis register provides byte 6 of the last setup packet received. For a Standard Device Request, the least significant byte of the wLength field is returned.
0
8
read-only
SETUP7
Setup Byte 7[15:8] \nThis register provides byte 7 of the last setup packet received. For a Standard Device Request, the most significant byte of the wLength field is returned.
8
8
read-only
TEST
USBD_TEST
USB Test Mode Register
0x24
read-write
n
0x0
0x0
TESTMODE
Test Mode Selection\nNote: This field is cleared when root port reset is detected.
0
3
read-write
0
Normal Operation
#000
1
Test_J
#001
2
Test_K
#010
3
Test_SE0_NAK
#011
4
Test_Packet
#100
5
Test_Force_Enable
#101
6
Reserved
#110
7
Reserved
#111
UVCEPAHCNT
USBD_UVCEPAHCNT
Endpoint A Header Count
0x254
read-write
n
0x0
0x0
CNT
This is the header count for the endpoint A~L The header count must be EVEN.
0
4
read-write
UVCEPBHCNT
USBD_UVCEPBHCNT
Endpoint B Header Count
0x258
read-write
n
0x0
0x0
UVCEPCHCNT
USBD_UVCEPCHCNT
Endpoint C Header Count
0x25C
read-write
n
0x0
0x0
UVCEPDHCNT
USBD_UVCEPDHCNT
Endpoint D Header Count
0x260
read-write
n
0x0
0x0
UVCEPEHCNT
USBD_UVCEPEHCNT
Endpoint E Header Count
0x264
read-write
n
0x0
0x0
UVCEPFHCNT
USBD_UVCEPFHCNT
Endpoint F Header Count
0x268
read-write
n
0x0
0x0
UVCEPGHCNT
USBD_UVCEPGHCNT
Endpoint G Header Count
0x26C
read-write
n
0x0
0x0
UVCEPHHCNT
USBD_UVCEPHHCNT
Endpoint H Header Count
0x270
read-write
n
0x0
0x0
UVCEPIHCNT
USBD_UVCEPIHCNT
Endpoint I Header Count
0x274
read-write
n
0x0
0x0
UVCEPJHCNT
USBD_UVCEPJHCNT
Endpoint J Header Count
0x278
read-write
n
0x0
0x0
UVCEPKHCNT
USBD_UVCEPKHCNT
Endpoint K Header Count
0x27C
read-write
n
0x0
0x0
UVCEPLHCNT
USBD_UVCEPLHCNT
Endpoint L Header Count
0x280
read-write
n
0x0
0x0
UVCHDAT0
USBD_UVCHDAT0
USB Header Word0
0x248
read-write
n
0x0
0x0
DAT
The first head data(byte 0 was sent first)
0
32
read-write
UVCHDAT1
USBD_UVCHDAT1
USB Header Word1
0x24C
read-write
n
0x0
0x0
DAT
The second head data(byte 0 was sent first)
0
32
read-write
UVCHDAT2
USBD_UVCHDAT2
USB Header Word2
0x250
read-write
n
0x0
0x0
DAT
The third head data(byte 0 was sent first)
0
32
read-write
USBH
USBH Register Map
USBH
0x0
0x0
0x5C
registers
n
0x200
0x8
registers
n
HCBULKCURRENTED
HCBULKCURRENTED
Host Controller Bulk Current ED Register
0x2C
read-write
n
0x0
0x0
BCED
Bulk Current Head ED\nPointer to indicate the physical address of the current endpoint of the Bulk list.
4
28
read-write
HCBULKHEADED
HCBULKHEADED
Host Controller Bulk Head ED Register
0x28
read-write
n
0x0
0x0
BHED
Bulk Head ED\nPointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list.
4
28
read-write
HCCOMMANDSTATUS
HCCOMMANDSTATUS
Host Controller Command Status Register
0x8
read-write
n
0x0
0x0
BLF
Bulk List Filled\nSet high to indicate there is an active TD on the Bulk list. This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list.\n
2
1
read-write
0
No active TD found or Host Controller begins to process the head of the Bulk list
#0
1
An active TD added or found on the Bulk list
#1
CLF
Control List Filled\nSet high to indicate there is an active TD on the Control List. It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List.\n
1
1
read-write
0
No active TD found or Host Controller begins to process the head of the Control list
#0
1
An active TD added or found on the Control list
#1
HCR
Host Controller Reset\nThis bit is set to initiate the software reset of Host Controller. This bit is cleared by the Host Controller, upon completed of the reset operation.\nThis bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports.\n
0
1
read-write
0
Host Controller is not in software reset state
#0
1
Host Controller is in software reset state
#1
SOC
Scheduling Overrun Count\nThese bits are incremented on each scheduling overrun error. It is initialized to 00b and wraps around at 11b. This will be incremented when a scheduling overrun is detected even if SO (HcInterruptStatus[0]) has already been set.
16
2
read-write
HCCONTROL
HCCONTROL
Host Controller Control Register
0x4
read-write
n
0x0
0x0
BLE
Bulk List Enable Bit\n
5
1
read-write
0
Processing of the Bulk list after next SOF (Start-Of-Frame) Disabled
#0
1
Processing of the Bulk list in the next frame Enabled
#1
CBSR
Control Bulk Service Ratio\nThis specifies the service ratio between Control and Bulk EDs. Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs. The internal count will be retained when crossing the frame boundary. In case of reset, HCD is responsible for restoring this\nValue.\n
0
2
read-write
0
Number of Control EDs over Bulk EDs served is 1:1
#00
1
Number of Control EDs over Bulk EDs served is 2:1
#01
2
Number of Control EDs over Bulk EDs served is 3:1
#10
3
Number of Control EDs over Bulk EDs served is 4:1
#11
CLE
Control List Enable Bit\n
4
1
read-write
0
Processing of the Control list after next SOF (Start-Of-Frame) Disabled
#0
1
Processing of the Control list in the next frame Enabled
#1
HCFS
Host Controller Functional State\nThis field sets the Host Controller state. The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port. States are:\n
6
2
read-write
0
USBRESET
#00
1
USBRESUME
#01
2
USBOPERATIONAL
#10
3
USBSUSPEND
#11
IE
Isochronous Enable Bit\nBoth ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list. Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list.\n
3
1
read-write
0
Processing of the Isochronous list after next SOF (Start-Of-Frame) Disabled
#0
1
Processing of the Isochronous list in the next frame Enabled, if the PLE (HcControl[2]) is high, too
#1
PLE
Periodic List Enable Bit\nWhen set, this bit enables processing of the Periodic (interrupt and isochronous) list. The Host Controller checks this bit prior to attempting any periodic transfers in a frame.\n To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high.
2
1
read-write
0
Processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame) Disabled
#0
1
Processing of the Periodic (Interrupt and Isochronous) list in the next frame Enabled
#1
HCCONTROLCURRENTED
HCCONTROLCURRENTED
Host Controller Control Current ED Register
0x24
read-write
n
0x0
0x0
CCED
Control Current Head ED\nPointer to indicate the physical address of the current Endpoint Descriptor of the Control list.
4
28
read-write
HCCONTROLHEADED
HCCONTROLHEADED
Host Controller Control Head ED Register
0x20
read-write
n
0x0
0x0
CHED
Control Head ED\nPointer to indicate physical address of the first Endpoint Descriptor of the Control list.
4
28
read-write
HCDONEHEAD
HCDONEHEAD
Host Controller Done Head Register
0x30
read-write
n
0x0
0x0
DH
Done Head\nPointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue.
4
28
read-write
HCFMINTERVAL
HCFMINTERVAL
Host Controller Frame Interval Register
0x34
-1
read-write
n
0x0
0x0
FI
Frame Interval\nThis field specifies the length of a frame as (bit times - 1). For 12,000 bit times in a frame, a value of 11,999 is stored here.
0
14
read-write
FIT
Frame Interval Toggle\nThis bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0]).\n
31
1
read-write
0
Host Controller Driver didn't load new value into FI (HcFmInterval[13:0])
#0
1
Host Controller Driver loads a new value into FI (HcFmInterval[13:0])
#1
FSMPS
FS Largest Data Packet\nThis field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame.
16
15
read-write
HCFMNUMBER
HCFMNUMBER
Host Controller Frame Number Register
0x3C
read-only
n
0x0
0x0
FN
Frame Number\nThis 16-bit incrementing counter field is incremented coincident with the loading of FR (HcFmRemaining[13:0]). The count rolls over from 'FFFFh' to '0h.'
0
16
read-only
HCFMREMAINING
HCFMREMAINING
Host Controller Frame Remaining Register
0x38
read-only
n
0x0
0x0
FR
Frame Remaining\nWhen the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period. When the count reaches 0, (end of frame) the counter reloads with Frame Interval. In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL.
0
14
read-only
FRT
Frame Remaining Toggle\nThis bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0.
31
1
read-only
HCHCCA
HCHCCA
Host Controller Communication Area Register
0x18
read-write
n
0x0
0x0
HCCA
Host Controller Communication Area\nPointer to indicate base address of the Host Controller Communication Area (HCCA).
8
24
read-write
HCINTERRUPTDISABLE
HCINTERRUPTDISABLE
Host Controller Interrupt Disable Control Register
0x14
read-write
n
0x0
0x0
FNO
Frame Number Overflow Disable Bit\nWrite Operation:\n
5
1
read-write
0
No effect.\nInterrupt generation due to FNO (HcInterruptStatus[5]) Disabled
#0
1
Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.\nInterrupt generation due to FNO (HcInterruptStatus[5]) Enabled
#1
MIE
Master Interrupt Disable Bit\nGlobal interrupt disable. Writing '1' to disable all interrupts.\nWrite Operation:\n
31
1
read-write
0
No effect.\nInterrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high
#0
1
Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled if the corresponding bit in HcInterruptEnable is high.\nInterrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high
#1
RD
Resume Detected Disable Bit\nWrite Operation:\n
3
1
read-write
0
No effect.\nInterrupt generation due to RD (HcInterruptStatus[3]) Disabled
#0
1
Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.\nInterrupt generation due to RD (HcInterruptStatus[3]) Enabled
#1
RHSC
Root Hub Status Change Disable Bit\nWrite Operation:\n
6
1
read-write
0
No effect.\nInterrupt generation due to RHSC (HcInterruptStatus[6]) Disabled
#0
1
Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.\nInterrupt generation due to RHSC (HcInterruptStatus[6]) Enabled
#1
SF
Start of Frame Disable Bit\nWrite Operation:\n
2
1
read-write
0
No effect.\nInterrupt generation due to SF (HcInterruptStatus[2]) Disabled
#0
1
Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.\nInterrupt generation due to SF (HcInterruptStatus[2]) Enabled
#1
SO
Scheduling Overrun Disable Bit\nWrite Operation:\n
0
1
read-write
0
No effect.\nInterrupt generation due to SO (HcInterruptStatus[0]) Disabled
#0
1
Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.\nInterrupt generation due to SO (HcInterruptStatus[0]) Enabled
#1
WDH
Write Back Done Head Disable Bit\nWrite Operation:\n
1
1
read-write
0
No effect.\nInterrupt generation due to WDH (HcInterruptStatus[1]) Disabled
#0
1
Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.\nInterrupt generation due to WDH (HcInterruptStatus[1]) Enabled
#1
HCINTERRUPTENABLE
HCINTERRUPTENABLE
Host Controller Interrupt Enable Control Register
0x10
read-write
n
0x0
0x0
FNO
Frame Number Overflow Interrupt Enable Bit\nWrite Operation:\n
5
1
read-write
0
No effect.\nInterrupt generation due to FNO (HcInterruptStatus[5]) Disabled
#0
1
Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled
#1
MIE
Master Interrupt Enable Bit\nThis bit is a global interrupt enable. A write of '1' allows interrupts to be enabled via the specific enable bits listed above.\nWrite Operation:\n
31
1
read-write
0
No effect.\nInterrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high
#0
1
Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high
#1
RD
Resume Detected Interrupt Enable Bit\nWrite Operation:\n
3
1
read-write
0
No effect.\nInterrupt generation due to RD (HcInterruptStatus[3]) Disabled
#0
1
Interrupt generation due to RD (HcInterruptStatus[3]) Enabled
#1
RHSC
Root Hub Status Change Interrupt Enable Bit\nWrite Operation:\n
6
1
read-write
0
No effect.\nInterrupt generation due to RHSC (HcInterruptStatus[6]) Disabled
#0
1
Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled
#1
SF
Start of Frame Interrupt Enable Bit\nWrite Operation:\n
2
1
read-write
0
No effect.\nInterrupt generation due to SF (HcInterruptStatus[2]) Disabled
#0
1
Interrupt generation due to SF (HcInterruptStatus[2]) Enabled
#1
SO
Scheduling Overrun Interrupt Enable Bit\nWrite Operation:\n
0
1
read-write
0
No effect.\nInterrupt generation due to SO (HcInterruptStatus[0]) Disabled
#0
1
Interrupt generation due to SO (HcInterruptStatus[0]) Enabled
#1
WDH
Write Back Done Head Interrupt Enable Bit\nWrite Operation:\n
1
1
read-write
0
No effect.\nInterrupt generation due to WDH (HcInterruptStatus[1]) Disabled
#0
1
Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled
#1
HCINTERRUPTSTATUS
HCINTERRUPTSTATUS
Host Controller Interrupt Status Register
0xC
read-write
n
0x0
0x0
FNO
Frame Number Overflow\nThis bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.\n
5
1
read-write
0
The bit 15 of Frame Number didn't change
#0
1
The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1
#1
RD
Resume Detected\nSet when Host Controller detects resume signaling on a downstream port.\n
3
1
read-write
0
No resume signaling detected on a downstream port
#0
1
Resume signaling detected on a downstream port
#1
RHSC
Root Hub Status Change\nThis bit is set when the content of HcRhStatus or the content of HcRhPortStatus1 register has changed.\n
6
1
read-write
0
The content of HcRhStatus and the content of HcRhPortStatus1 register didn't change
#0
1
The content of HcRhStatus or the content of HcRhPortStatus1 register has changed
#1
SF
Start of Frame\nSet when the Frame Management functional block signals a 'Start of Frame' event. Host Control generates a SOF token at the same time.\n
2
1
read-write
0
.Not the start of a frame
#0
1
.Indicate the start of a frame and Host Controller generates a SOF token
#1
SO
Scheduling Overrun\nSet when the List Processor determines a Schedule Overrun has occurred.\n
0
1
read-write
0
Schedule Overrun didn't occur
#0
1
Schedule Overrun has occurred
#1
WDH
Write Back Done Head\nSet after the Host Controller has written HcDoneHead to HccaDoneHead. Further updates of the HccaDoneHead will not occur until this bit has been cleared.\n
1
1
read-write
0
.Host Controller didn't update HccaDoneHead
#0
1
.Host Controller has written HcDoneHead to HccaDoneHead
#1
HCLSTHRESHOLD
HCLSTHRESHOLD
Host Controller Low-speed Threshold Register
0x44
-1
read-write
n
0x0
0x0
LST
Low-speed Threshold\n
0
12
read-write
HCMISCCONTROL
HCMISCCONTROL
Host Controller Miscellaneous Control Register
0x204
read-write
n
0x0
0x0
ABORT
AHB Bus ERROR Response\nThis bit indicates there is an ERROR response received in AHB bus.\n
1
1
read-write
0
No ERROR response received
#0
1
ERROR response received
#1
DBR16
Data Buffer Region 16\nWhen set, the size of the data buffer region is 16 bytes. Otherwise, the size is 32 bytes.
0
1
read-write
DPRT1
Port 1 Disable Bit\nThis bit controls if the connection between USB host controller and transceiver of port 1 is disabled. If the connection is disabled, the USB host controller will not recognize any event of USB bus.\nSet this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is.\n
16
1
read-write
0
The connection between USB host controller and transceiver of port 1 is enabled
#0
1
The connection between USB host controller and transceiver of port 1 is disabled and the transceiver of port 1 will also be forced into the standby mode
#1
DPRT2
Port 2 Disable Bit\nThis bit controls if the connection between USB host controller and transceiver of port 2 is disabled. If the connection is disabled, the USB host controller will not recognize any event of USB bus.\nSet this bit high, the transceiver of port 2 will also be forced into the standby mode no matter what USB host controller operation is.\n
17
1
read-write
0
The connection between USB host controller and transceiver of port 2 is enabled
#0
1
The connection between USB host controller and transceiver of port 2 is disabled and the transceiver of port 2 will also be forced into the standby mode
#1
OCAL
Overcurrent Active Low\nThis bit controls the polarity of overcurrent flag from external power IC.\n
3
1
read-write
0
Overcurrent flag is high active
#0
1
Overcurrent flag is low active
#1
PCAL
Port Power Control Active Low\nThis bit controls the polarity of port power control to external power IC.\n
4
1
read-write
0
Port power control is high active
#0
1
Port power control is low active
#1
SIEPD
SIE Pipeline Disable Bit\nWhen set, waits for all USB bus activity to complete prior to returning completion status to the List Processor. This is a failsafe mechanism to avoid potential problems with the clk_dr transition between 1.5 MHz and 12 MHz.
8
1
read-write
HCPERIODCURRENTED
HCPERIODCURRENTED
Host Controller Period Current ED Register
0x1C
read-write
n
0x0
0x0
PCED
Periodic Current ED\nPointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor.
4
28
read-write
HCPERIODICSTART
HCPERIODICSTART
Host Controller Periodic Start Register
0x40
read-write
n
0x0
0x0
PS
Periodic Start\nThis field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
0
14
read-write
HCPHYCONTROL
HCPHYCONTROL
Host Controller PHY Control Register
0x200
read-write
n
0x0
0x0
STBYEN
USB Transceiver Standby Enable Bit\nThis bit controls if USB transceiver could enter the standby mode to reduce power consumption.\n
27
1
read-write
0
The USB transceiver would never enter the standby mode
#0
1
The USB transceiver will enter Standby mode while port is in power off state (port power is inactive)
#1
HCREVISION
HCREVISION
Host Controller Revision Register
0x0
-1
read-only
n
0x0
0x0
REV
Revision\nIndicates the Open HCI Specification revision number implemented by the Hardware. Host Controller supports 1.1 specification.\n
0
8
read-only
HCRHDESCRIPTORA
HCRHDESCRIPTORA
Host Controller Root Hub Descriptor A Register
0x48
-1
read-write
n
0x0
0x0
NDP
Number Downstream Ports\nRoot Hub supports two downstream ports. It's 2 in this Root Hub.
0
8
read-write
NOCP
No Overcurrent Protection\nThis bit describes how the overcurrent status for the Root Hub ports reported.\n
12
1
read-write
0
Overcurrent status is reported
#0
1
Overcurrent status is not reported
#1
OCPM
Overcurrent Protection Mode\nThis bit describes how the overcurrent status for the Root Hub ports reported. This bit is only valid when NOCP (HcRhDescriptorA[12]) is cleared.\n
11
1
read-write
0
Global Overcurrent
#0
1
Individual Overcurrent
#1
PSM
Power Switching Mode\nThis bit is used to specify how the power switching of the Root Hub ports is controlled.\n
8
1
read-write
0
Global Switching
#0
1
Individual Switching
#1
HCRHDESCRIPTORB
HCRHDESCRIPTORB
Host Controller Root Hub Descriptor B Register
0x4C
read-write
n
0x0
0x0
PPCM
Port Power Control Mask\nGlobal power switching. This field is only valid if PowerSwitchingMode is set (individual port switching). When set, the port only responds to individual port power switching commands (Set/ClearPortPower). When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower).\n PPCM[15:3] and PPCM[0] are reserved.
16
16
read-write
0
Port power controlled by global power switching
0
1
Port power controlled by port power switching
1
HCRHPORTSTATUS1
HCRHPORTSTATUS1
Host Controller Root Hub Port Status [1]
0x54
read-write
n
0x0
0x0
CCS
Current Connect Status (Read) or Clear Port Enable Bit (Write)\nWrite Operation:\n
0
1
read-write
0
No effect.\nNo device connected
#0
1
Clear port Enabled.\nDevice connected
#1
CSC
Connect Status Change\nThis bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus1[0]) changed).\nWrite 1 to clear this bit to zero.\n
16
1
read-write
0
No connect/disconnect event (CCS (HcRhPortStatus1[0]) didn't change)
#0
1
Hardware detection of connect/disconnect event (CCS (HcRhPortStatus1[0]) changed)
#1
LSDA
Low Speed Device Attached (Read) or Clear Port Power (Write)\nThis bit defines the speed (and bud idle) of the attached device. It is only valid when CCS (HcRhPortStatus1[0]) is set.\nThis bit is also used to clear port power.\nWrite Operation:\n
9
1
read-write
0
No effect.\nFull Speed device
#0
1
Clear PPS (HcRhPortStatus1[8]).\nLow-speed device
#1
OCIC
Port Overcurrent Indicator Change\nThis bit is set when POCI (HcRhPortStatus1[3]) changes.\nWrite 1 to clear this bit to zero.\n
19
1
read-write
0
POCI (HcRhPortStatus1[3]) is not changed
#0
1
POCI (HcRhPortStatus1[3]) is changed
#1
PES
Port Enable Status\nWrite Operation:\n
1
1
read-write
0
No effect.\nPort Disabled
#0
1
Set port Enabled.\nPort Enabled
#1
PESC
Port Enable Status Change\nThis bit indicates that the port has been disabled (PES (HcRhPortStatus1[1]) cleared) due to a hardware event.\nWrite 1 to clear this bit to zero.\n
17
1
read-write
0
PES (HcRhPortStatus1[1]) is not changed
#0
1
PES (HcRhPortStatus1[1]) is changed
#1
POCI
Port Overcurrent Indicator (Read) or Clear Port Suspend (Write)\nThis bit reflects the state of the overcurrent status pin dedicated to this port. This field is only valid if NOCP (HcRhDescriptorA[12]) is cleared and OCPM (HcRhDescriptorA[11]) is set.\nThis bit is also used to initiate the selective result sequence for the port.\nWrite Operation:\n
3
1
read-write
0
No effect.\nNo overcurrent condition
#0
1
Clear port suspend.\nOvercurrent condition
#1
PPS
Port Power Status\nThis bit reflects the power state of the port regardless of the power switching mode.\nWrite Operation:\n
8
1
read-write
0
No effect.\nPort power Diabled
#0
1
Port Power Enabled.\nPort power Enabled
#1
PRS
Port Reset Status\nThis bit reflects the reset state of the port.\nWrite Operation:\n
4
1
read-write
0
No effect.\nPort reset signal is not active
#0
1
Set port reset.\nPort reset signal is active
#1
PRSC
Port Reset Status Change\nThis bit indicates that the port reset signal has completed.\nWrite 1 to clear this bit to zero.\n
20
1
read-write
0
Port reset is not completed
#0
1
Port reset is completed
#1
PSS
Port Suspend Status\nThis bit indicates the port is suspended\nWrite Operation:\n
2
1
read-write
0
No effect.\nPort is not suspended
#0
1
Set port suspend.\nPort is selectively suspended
#1
PSSC
Port Suspend Status Change\nThis bit indicates the completion of the selective resume sequence for the port.\nWrite 1 to clear this bit to zero.\n
18
1
read-write
0
Port resume is not completed
#0
1
Port resume is completed
#1
HCRHPORTSTATUS2
HCRHPORTSTATUS2
Host Controller Root Hub Port Status [2]
0x58
read-write
n
0x0
0x0
HCRHSTATUS
HCRHSTATUS
Host Controller Root Hub Status Register
0x50
read-write
n
0x0
0x0
CRWE
Clear Remote Wake-up Enable Bit\nThis bit is used to clear DRWE (HcRhStatus[15]).\nThis bit is always read as zero.\nWrite Operation:\n
31
1
read-write
0
No effect
#0
1
Clear DRWE (HcRhStatus[15])
#1
DRWE
Device Remote Wake-up Enable Bit\nThis bit controls if port's Connect Status Change as a remote wake-up event.\nWrite Operation:\n
15
1
read-write
0
No effect.\nConnect status changed as a remote wake-up event Disabled
#0
1
Connect status changed as a remote wake-up event Enabled
#1
LPS
Clear Global Power\n
0
1
read-write
0
No effect
#0
1
Clear global power
#1
LPSC
Set Global Power\n
16
1
read-write
0
No effect
#0
1
Set global power
#1
OCI
Overcurrent Indicator\nThis bit reflects the state of the overcurrent status pin. This field is only valid if NOCP (HcRhDesA[12]) and OCPM (HcRhDesA[11]) are cleared.\n
1
1
read-write
0
No overcurrent condition
#0
1
Overcurrent condition
#1
OCIC
Overcurrent Indicator Change\nThis bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]).\nWrite 1 to clear this bit to zero.\n
17
1
read-write
0
OCI (HcRhStatus[1]) is not changed
#0
1
OCI (HcRhStatus[1]) is changed
#1
WDT
WDT Register Map
WDT
0x0
0x0
0x8
registers
n
0x10
0x4
registers
n
ALTCTL
WDT_ALTCTL
Watchdog Timer Alternative Control Register
0x4
read-write
n
0x0
0x0
RSTDSEL
Watchdog Timer Reset Delay Selection\nWhen Watchdog Timer time-out happened, software has a time named Watchdog Timer reset delay period to clear Watchdog Timer counter to prevent Watchdog Timer time-out reset happened. Software can select a suitable value of Watchdog Timer reset delay period for different Watchdog Timer time-out period.\nNote: This bit will be reset to 0 if Watchdog Timer time-out reset happened.
0
2
read-write
0
Watchdog Timer reset delay period is (1024+2) * WDT_CLK
#00
1
Watchdog Timer reset delay period is (128+2) * WDT_CLK
#01
2
Watchdog Timer reset delay period is (16+2) * WDT_CLK
#10
3
Watchdog Timer reset delay period is (1+2) * WDT_CLK
#11
CTL
WDT_CTL
Watchdog Timer Control Register
0x0
-1
read-write
n
0x0
0x0
ICEDEBUG
ICE Debug Mode Acknowledge Disable Control \nWatchdog Timer counter will keep going no matter CPU is held by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement affects Watchdog Timer counting
#0
1
ICE debug mode acknowledgement Disabled
#1
IF
Watchdog Timer Interrupt Flag\nThis bit will set to 1 while Watchdog Timer counter value reaches the selected Watchdog Timer time-out interval\nNote: This bit is cleared by writing 1 to it.
3
1
read-write
0
Watchdog Timer time-out interrupt did not occur
#0
1
Watchdog Timer time-out interrupt occurred
#1
INTEN
Watchdog Timer Interrupt Enable Control \nIf this bit is enabled, the Watchdog Timer time-out interrupt signal is generated and inform to CPU. \n
6
1
read-write
0
Watchdog Timer interrupt Disabled
#0
1
Watchdog Timer interrupt Enabled
#1
RSTCNT
Clear Watchdog Timer\nNote: This bit will be automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Reset the internal 18-bit Watchdog Timer counter
#1
RSTEN
Watchdog Timer Reset Enable Control \nSetting this bit will enable the Watchdog Timer time-out reset function If the Watchdog Timer counter value has not been cleared after the specific Watchdog Timer reset delay period expires.\n
1
1
read-write
0
Watchdog Timer time-out reset function Disabled
#0
1
Watchdog Timer time-out reset function Enabled
#1
RSTFC
Watchdog Timer Reset Flag Cleared\nWrite 1 to clear the RSTF (WDT_RSTSTS [2]).
2
1
read-write
TOUTSEL
Watchdog Timer Time-out Interval Selection \nThese three bits select the time-out interval period for the Watchdog Timer.\n
8
3
read-write
0
24 *TWDT
#000
1
26 *TWDT
#001
2
28 *TWDT
#010
3
210 *TWDT
#011
4
212 *TWDT
#100
5
214 *TWDT
#101
6
216 *TWDT
#110
7
218 *TWDT
#111
WDTEN
Watchdog Timer Enable Control \n
7
1
read-write
0
Watchdog Timer Disabled (This action will reset the internal counter)
#0
1
Watchdog Timer Enabled
#1
WKEN
Watchdog Timer Wake-up Function Enable Control \nIf this bit is set to 1, while Watchdog Timer interrupt flag IF (WDT_CTL[3]) is generated to 1 and INTEN (WDT_CTL[6] Watchdog Timer interrupt enable) is enabled, the Watchdog Timer time-out interrupt signal will generate a wake-up trigger event to chip.\nNote: Chip can be woken-up by Watchdog Timer time-out interrupt signal generated only if Watchdog Timer clock source is selected to 32 kHz oscillator.
4
1
read-write
0
Wake-up trigger event Disabled if Watchdog Timer time-out interrupt signal generated
#0
1
Wake-up trigger event Enabled if Watchdog Timer time-out interrupt signal generated
#1
WKF
Watchdog Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of Watchdog Timer \nNote: This bit is cleared by writing 1 to it.
5
1
read-write
0
Watchdog Timer does not cause chip wake-up
#0
1
Chip wake-up from Power-down if Watchdog Timer time-out interrupt signal generated
#1
RSTSTS
WDT_RSTSTS
Watchdog Timer Reset Status Register
0x10
-1
read-only
n
0x0
0x0
RSTF
Watchdog Timer Reset Flag \nThis bit indicates the system has been reset by Watchdog Timer time-out reset or not.\nNote: This bit is cleared by writing 1 to RSTFC (WDT_CTL [2]).
2
1
read-only
0
Watchdog Timer time-out reset did not occur
#0
1
Watchdog Timer time-out reset occurred
#1
WWDT
WWDT Register Map
WWDT
0x0
0x0
0x10
registers
n
0x18
0x4
registers
n
CNT
WWDT_CNT
Window Watchdog Timer Counter Value Register
0xC
-1
read-only
n
0x0
0x0
CNTDAT
WWDT Counter Value\nThis register reflects the current WWDT counter value and is read only.
0
6
read-only
CTL
WWDT_CTL
Window Watchdog Timer Control Register
0x4
-1
read-write
n
0x0
0x0
CMPDAT
WWDT Window Compare Bits\nSet this register to adjust the valid reload window. \nSoftware can only write RLDCNT to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT. If Software writes RLDCNT when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
16
6
read-write
ICEDEBUG
ICE Debug Mode Acknowledge Disable Control\nWWDT down counter will keep going no matter CPU is held by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement effects WWDT counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
WWDT Interrupt Enable Control\nIf this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.\n
1
1
read-write
0
WWDT counter compare match interrupt Disabled
#0
1
WWDT counter compare match interrupt Enabled
#1
PSCSEL
WWDT Counter Prescale Period Selection\n
8
4
read-write
0
Pre-scale is 1 Max time-out period is 1 * 64 * TWWDT
#0000
1
Pre-scale is 2 Max time-out period is 2 * 64 * TWWDT
#0001
2
Pre-scale is 4 Max time-out period is 4 * 64 * TWWDT
#0010
3
Pre-scale is 8 Max time-out period is 8 * 64 * TWWDT
#0011
4
Pre-scale is 16 Max time-out period is 16 * 64 * TWWDT
#0100
5
Pre-scale is 32 Max time-out period is 32 * 64 * TWWDT
#0101
6
Pre-scale is 64 Max time-out period is 64 * 64 * TWWDT
#0110
7
Pre-scale is 128 Max time-out period is 128 * 64 * TWWDT
#0111
8
Pre-scale is 192 Max time-out period is 192 * 64 * TWWDT
#1000
9
Pre-scale is 256 Max time-out period is 256 * 64 * TWWDT
#1001
10
Pre-scale is 384 Max time-out period is 384 * 64 * TWWDT
#1010
11
Pre-scale is 512 Max time-out period is 512 * 64 * TWWDT
#1011
12
Pre-scale is 768 Max time-out period is 768 * 64 * TWWDT
#1100
13
Pre-scale is 1024 Max time-out period is 1024 * 64 * TWWDT
#1101
14
Pre-scale is 1536 Max time-out period is 1536 * 64 * TWWDT
#1110
15
Pre-scale is 2048 Max time-out period is 2048 * 64 * TWWDT
#1111
WWDTEN
WWDT Enable Control\nSet this bit to enable Window Watchdog Timer counter counting.\n
0
1
read-write
0
Window Watchdog Timer counter is stopped
#0
1
Window Watchdog Timer counter is starting counting
#1
RLDCNT
WWDT_RLDCNT
Window Watchdog Timer Reload Counter Register
0x0
write-only
n
0x0
0x0
RLDCNT
WWDT Reload Counter Bits\nWriting 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F. \n Software can only write RLDCNT to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT. If software writes RLDCNT when current WWDT counter value is larger than CMPDAT, WWDT reset signal will generate immediately.
0
32
write-only
RSTSTS
WWDT_RSTSTS
Window Watchdog Timer Reset Status Register
0x18
read-only
n
0x0
0x0
WWDTRF
WWDT Timer-out Reset Flag \nThis bit indicates the system has been reset by WWDT time-out reset or not.\n This bit is cleared by writing 1 to WWDTRFC (WWDT_STATUS [1])
1
1
read-only
0
WWDT time-out reset did not occur
#0
1
WWDT time-out reset occurred
#1
STATUS
WWDT_STATUS
Window Watchdog Timer Status Register
0x8
read-write
n
0x0
0x0
WWDTIF
WWDT Compare Match Interrupt Flag \nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT value.\n This bit is cleared by writing 1 to WWDT_STATUS[0]
0
1
read-write
0
No effect
#0
1
WWDT counter value matches CMPDAT value
#1
WWDTRFC
WWDT Timer-out Reset Flag Cleared\nWhen the window watch dog reset happened, the register WWDTRF (WWDT_RSTSTS [1]) will be set to 1. Write 1 to this bit and the WWDTRF (WWDT_RSTSTS [1]) will be cleared.
1
1
read-write