\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
TIM6 control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Counter enable
bits : 0 - 0 (1 bit)
UDIS : Update disable
bits : 1 - 1 (1 bit)
URS : Update request source
bits : 2 - 2 (1 bit)
OPM : One-pulse mode
bits : 3 - 3 (1 bit)
ARPE : Auto-reload preload enable
bits : 7 - 7 (1 bit)
TIM6 status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UIF : Update interrupt flag
bits : 0 - 0 (1 bit)
TIM6 event generation register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UG : Update generation
bits : 0 - 0 (1 bit)
TIM6 counter
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : CNT
bits : 0 - 15 (16 bit)
TIM6 prescaler
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSC : Prescaler valueThe counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
bits : 0 - 15 (16 bit)
TIM6 auto-reload register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARR : Prescaler value
bits : 0 - 15 (16 bit)
TIM6 control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MMS : Master mode selection
bits : 4 - 6 (3 bit)
TIM6 DMA/Interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UIE : Update interrupt enable
bits : 0 - 0 (1 bit)
UDE : Update DMA request enable
bits : 8 - 8 (1 bit)
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