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Flash

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

ACR

PRGKEYR

OPTKEYR

SR

OBR

WRPR1

PECR

PDKEYR

WRPR2

WRPR3

PEKEYR


ACR

Access control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACR ACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LATENCY PRFTEN ACC64 SLEEP_PD RUN_PD

LATENCY : Latency
bits : 0 - 0 (1 bit)

PRFTEN : Prefetch enable
bits : 1 - 1 (1 bit)

ACC64 : 64-bit access
bits : 2 - 2 (1 bit)

SLEEP_PD : Flash mode during Sleep
bits : 3 - 3 (1 bit)

RUN_PD : Flash mode during Run
bits : 4 - 4 (1 bit)


PRGKEYR

Program memory key register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PRGKEYR PRGKEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRGKEYR

PRGKEYR : Program memory key
bits : 0 - 31 (32 bit)


OPTKEYR

Option byte key register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

OPTKEYR OPTKEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPTKEYR

OPTKEYR : Option byte key
bits : 0 - 31 (32 bit)


SR

Status register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BSY EOP ENDHV READY WRPERR PGAERR SIZERR OPTVERR OPTVERRUSR

BSY : Write/erase operations in progress
bits : 0 - 0 (1 bit)
access : read-only

EOP : End of operation
bits : 1 - 1 (1 bit)
access : read-only

ENDHV : End of high voltage
bits : 2 - 2 (1 bit)
access : read-only

READY : Flash memory module ready after low power mode
bits : 3 - 3 (1 bit)
access : read-only

WRPERR : Write protected error
bits : 8 - 8 (1 bit)
access : read-write

PGAERR : Programming alignment error
bits : 9 - 9 (1 bit)
access : read-write

SIZERR : Size error
bits : 10 - 10 (1 bit)
access : read-write

OPTVERR : Option validity error
bits : 11 - 11 (1 bit)
access : read-write

OPTVERRUSR : Option UserValidity Error
bits : 12 - 12 (1 bit)
access : read-write


OBR

Option byte register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OBR OBR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDPRT BOR_LEV IWDG_SW nRTS_STOP nRST_STDBY BFB2

RDPRT : Read protection
bits : 0 - 7 (8 bit)

BOR_LEV : BOR_LEV
bits : 16 - 19 (4 bit)

IWDG_SW : IWDG_SW
bits : 20 - 20 (1 bit)

nRTS_STOP : nRTS_STOP
bits : 21 - 21 (1 bit)

nRST_STDBY : nRST_STDBY
bits : 22 - 22 (1 bit)

BFB2 : Boot From Bank 2
bits : 23 - 23 (1 bit)


WRPR1

Write protection register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRPR1 WRPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRP1

WRP1 : Write protection
bits : 0 - 31 (32 bit)


PECR

Program/erase control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PECR PECR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PELOCK PRGLOCK OPTLOCK PROG DATA FTDW ERASE FPRG PARALLELBANK EOPIE ERRIE OBL_LAUNCH

PELOCK : FLASH_PECR and data EEPROM lock
bits : 0 - 0 (1 bit)

PRGLOCK : Program memory lock
bits : 1 - 1 (1 bit)

OPTLOCK : Option bytes block lock
bits : 2 - 2 (1 bit)

PROG : Program memory selection
bits : 3 - 3 (1 bit)

DATA : Data EEPROM selection
bits : 4 - 4 (1 bit)

FTDW : Fixed time data write for Byte, Half Word and Word programming
bits : 8 - 8 (1 bit)

ERASE : Page or Double Word erase mode
bits : 9 - 9 (1 bit)

FPRG : Half Page/Double Word programming mode
bits : 10 - 10 (1 bit)

PARALLELBANK : Parallel bank mode
bits : 15 - 15 (1 bit)

EOPIE : End of programming interrupt enable
bits : 16 - 16 (1 bit)

ERRIE : Error interrupt enable
bits : 17 - 17 (1 bit)

OBL_LAUNCH : Launch the option byte loading
bits : 18 - 18 (1 bit)


PDKEYR

Power down key register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PDKEYR PDKEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDKEYR

PDKEYR : RUN_PD in FLASH_ACR key
bits : 0 - 31 (32 bit)


WRPR2

Write protection register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRPR2 WRPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRP2

WRP2 : WRP2
bits : 0 - 31 (32 bit)


WRPR3

Write protection register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRPR3 WRPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRP3

WRP3 : WRP3
bits : 0 - 31 (32 bit)


PEKEYR

Program/erase key register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PEKEYR PEKEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PEKEYR

PEKEYR : FLASH_PEC and data EEPROM key
bits : 0 - 31 (32 bit)



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