\n
address_offset : 0x0 Bytes (0x0)
size : 0x15 byte (0x0)
mem_usage : registers
protection :
DBGMCU_IDCODE
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DEV_ID : Device identifier
bits : 0 - 11 (12 bit)
REV_ID : Revision identifie
bits : 16 - 31 (16 bit)
Debug MCU configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_SLEEP : Debug Sleep mode
bits : 0 - 0 (1 bit)
DBG_STOP : Debug Stop mode
bits : 1 - 1 (1 bit)
DBG_STANDBY : Debug Standby mode
bits : 2 - 2 (1 bit)
TRACE_IOEN : Trace pin assignment control
bits : 5 - 5 (1 bit)
TRACE_MODE : Trace pin assignment control
bits : 6 - 7 (2 bit)
Debug MCU APB1 freeze register1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_TIM2_STOP : TIM2 counter stopped when core is halted
bits : 0 - 0 (1 bit)
DBG_TIM3_STOP : TIM3 counter stopped when core is halted
bits : 1 - 1 (1 bit)
DBG_TIM4_STOP : TIM4 counter stopped when core is halted
bits : 2 - 2 (1 bit)
DBG_TIM5_STOP : TIM5 counter stopped when core is halted
bits : 3 - 3 (1 bit)
DBG_TIM6_STOP : TIM6 counter stopped when core is halted
bits : 4 - 4 (1 bit)
DBG_TIM7_STOP : TIM7 counter stopped when core is halted
bits : 5 - 5 (1 bit)
DBG_RTC_STOP : Debug RTC stopped when core is halted
bits : 10 - 10 (1 bit)
DBG_WWDG_STOP : Debug window watchdog stopped when core is halted
bits : 11 - 11 (1 bit)
DBG_IWDG_STOP : Debug independent watchdog stopped when core is halted
bits : 12 - 12 (1 bit)
DBG_I2C1_SMBUS_TIMEOUT : SMBUS timeout mode stopped when core is halted
bits : 21 - 21 (1 bit)
DBG_I2C2_SMBUS_TIMEOUT : SMBUS timeout mode stopped when core is halted
bits : 22 - 22 (1 bit)
Debug MCU APB1 freeze register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_TIM9_STOP : TIM counter stopped when core is halted
bits : 2 - 2 (1 bit)
DBG_TIM10_STOP : TIM counter stopped when core is halted
bits : 3 - 3 (1 bit)
DBG_TIM11_STOP : TIM counter stopped when core is halted
bits : 4 - 4 (1 bit)
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