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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x11 byte (0x0)
mem_usage : registers
protection :

Registers

CSR

CCR

CDR


CSR

ADC Common status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRDY_MST EOSMP_MST EOC_MST EOS_MST OVR_MST JEOC_MST JEOS_MST AWD1_MST AWD2_MST AWD3_MST JQOVF_MST ADRDY_SLV EOSMP_SLV EOC_SLV EOS_SLV OVR_SLV JEOC_SLV JEOS_SLV AWD1_SLV AWD2_SLV AWD3_SLV JQOVF_SLV

ADDRDY_MST : ADDRDY_MST
bits : 0 - 0 (1 bit)

EOSMP_MST : EOSMP_MST
bits : 1 - 1 (1 bit)

EOC_MST : EOC_MST
bits : 2 - 2 (1 bit)

EOS_MST : EOS_MST
bits : 3 - 3 (1 bit)

OVR_MST : OVR_MST
bits : 4 - 4 (1 bit)

JEOC_MST : JEOC_MST
bits : 5 - 5 (1 bit)

JEOS_MST : JEOS_MST
bits : 6 - 6 (1 bit)

AWD1_MST : AWD1_MST
bits : 7 - 7 (1 bit)

AWD2_MST : AWD2_MST
bits : 8 - 8 (1 bit)

AWD3_MST : AWD3_MST
bits : 9 - 9 (1 bit)

JQOVF_MST : JQOVF_MST
bits : 10 - 10 (1 bit)

ADRDY_SLV : ADRDY_SLV
bits : 16 - 16 (1 bit)

EOSMP_SLV : EOSMP_SLV
bits : 17 - 17 (1 bit)

EOC_SLV : End of regular conversion of the slave ADC
bits : 18 - 18 (1 bit)

EOS_SLV : End of regular sequence flag of the slave ADC
bits : 19 - 19 (1 bit)

OVR_SLV : Overrun flag of the slave ADC
bits : 20 - 20 (1 bit)

JEOC_SLV : End of injected conversion flag of the slave ADC
bits : 21 - 21 (1 bit)

JEOS_SLV : End of injected sequence flag of the slave ADC
bits : 22 - 22 (1 bit)

AWD1_SLV : Analog watchdog 1 flag of the slave ADC
bits : 23 - 23 (1 bit)

AWD2_SLV : Analog watchdog 2 flag of the slave ADC
bits : 24 - 24 (1 bit)

AWD3_SLV : Analog watchdog 3 flag of the slave ADC
bits : 25 - 25 (1 bit)

JQOVF_SLV : Injected Context Queue Overflow flag of the slave ADC
bits : 26 - 26 (1 bit)


CCR

ADC common control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUAL DELAY DMACFG MDMA CKMODE PRESC VREFEN CH17SEL CH18SEL

DUAL : Dual ADC mode selection
bits : 0 - 4 (5 bit)

DELAY : Delay between 2 sampling phases
bits : 8 - 11 (4 bit)

DMACFG : DMA configuration (for multi-ADC mode)
bits : 13 - 13 (1 bit)

MDMA : Direct memory access mode for multi ADC mode
bits : 14 - 15 (2 bit)

CKMODE : ADC clock mode
bits : 16 - 17 (2 bit)

PRESC : ADC prescaler
bits : 18 - 21 (4 bit)

VREFEN : VREFINT enable
bits : 22 - 22 (1 bit)

CH17SEL : CH17 selection
bits : 23 - 23 (1 bit)

CH18SEL : CH18 selection
bits : 24 - 24 (1 bit)


CDR

ADC common regular data register for dual and triple modes
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CDR CDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATA_MST RDATA_SLV

RDATA_MST : Regular data of the master ADC
bits : 0 - 15 (16 bit)

RDATA_SLV : Regular data of the slave ADC
bits : 16 - 31 (16 bit)



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