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DCMI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CR

MIS

ICR

ESCR

ESUR

CWSTRT

CWSIZE

DR

SR

RIS

IER


CR

control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPTURE CM CROP JPEG ESS PCKPOL HSPOL VSPOL FCRC EDM ENABLE BSM OEBS LSM OELS

CAPTURE : Capture enable
bits : 0 - 0 (1 bit)

CM : Capture mode
bits : 1 - 1 (1 bit)

CROP : Crop feature
bits : 2 - 2 (1 bit)

JPEG : JPEG format
bits : 3 - 3 (1 bit)

ESS : Embedded synchronization select
bits : 4 - 4 (1 bit)

PCKPOL : Pixel clock polarity
bits : 5 - 5 (1 bit)

HSPOL : Horizontal synchronization polarity
bits : 6 - 6 (1 bit)

VSPOL : Vertical synchronization polarity
bits : 7 - 7 (1 bit)

FCRC : Frame capture rate control
bits : 8 - 9 (2 bit)

EDM : Extended data mode
bits : 10 - 11 (2 bit)

ENABLE : DCMI enable
bits : 14 - 14 (1 bit)

BSM : Byte Select mode
bits : 16 - 17 (2 bit)

OEBS : Odd/Even Byte Select (Byte Select Start)
bits : 18 - 18 (1 bit)

LSM : Line Select mode
bits : 19 - 19 (1 bit)

OELS : Odd/Even Line Select (Line Select Start)
bits : 20 - 20 (1 bit)


MIS

masked interrupt status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MIS MIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAME_MIS OVR_MIS ERR_MIS VSYNC_MIS LINE_MIS

FRAME_MIS : Capture complete masked interrupt status
bits : 0 - 0 (1 bit)

OVR_MIS : Overrun masked interrupt status
bits : 1 - 1 (1 bit)

ERR_MIS : Synchronization error masked interrupt status
bits : 2 - 2 (1 bit)

VSYNC_MIS : VSYNC masked interrupt status
bits : 3 - 3 (1 bit)

LINE_MIS : Line masked interrupt status
bits : 4 - 4 (1 bit)


ICR

interrupt clear register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICR ICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAME_ISC OVR_ISC ERR_ISC VSYNC_ISC LINE_ISC

FRAME_ISC : Capture complete interrupt status clear
bits : 0 - 0 (1 bit)

OVR_ISC : Overrun interrupt status clear
bits : 1 - 1 (1 bit)

ERR_ISC : Synchronization error interrupt status clear
bits : 2 - 2 (1 bit)

VSYNC_ISC : Vertical synch interrupt status clear
bits : 3 - 3 (1 bit)

LINE_ISC : line interrupt status clear
bits : 4 - 4 (1 bit)


ESCR

embedded synchronization code register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ESCR ESCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSC LSC LEC FEC

FSC : Frame start delimiter code
bits : 0 - 7 (8 bit)

LSC : Line start delimiter code
bits : 8 - 15 (8 bit)

LEC : Line end delimiter code
bits : 16 - 23 (8 bit)

FEC : Frame end delimiter code
bits : 24 - 31 (8 bit)


ESUR

embedded synchronization unmask register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ESUR ESUR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSU LSU LEU FEU

FSU : Frame start delimiter unmask
bits : 0 - 7 (8 bit)

LSU : Line start delimiter unmask
bits : 8 - 15 (8 bit)

LEU : Line end delimiter unmask
bits : 16 - 23 (8 bit)

FEU : Frame end delimiter unmask
bits : 24 - 31 (8 bit)


CWSTRT

crop window start
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CWSTRT CWSTRT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HOFFCNT VST

HOFFCNT : Horizontal offset count
bits : 0 - 13 (14 bit)

VST : Vertical start line count
bits : 16 - 28 (13 bit)


CWSIZE

crop window size
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CWSIZE CWSIZE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPCNT VLINE

CAPCNT : Capture count
bits : 0 - 13 (14 bit)

VLINE : Vertical line count
bits : 16 - 29 (14 bit)


DR

data register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR DR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Byte0 Byte1 Byte2 Byte3

Byte0 : Data byte 0
bits : 0 - 7 (8 bit)

Byte1 : Data byte 1
bits : 8 - 15 (8 bit)

Byte2 : Data byte 2
bits : 16 - 23 (8 bit)

Byte3 : Data byte 3
bits : 24 - 31 (8 bit)


SR

status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSYNC VSYNC FNE

HSYNC : HSYNC
bits : 0 - 0 (1 bit)

VSYNC : VSYNC
bits : 1 - 1 (1 bit)

FNE : FIFO not empty
bits : 2 - 2 (1 bit)


RIS

raw interrupt status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RIS RIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAME_RIS OVR_RIS ERR_RIS VSYNC_RIS LINE_RIS

FRAME_RIS : Capture complete raw interrupt status
bits : 0 - 0 (1 bit)

OVR_RIS : Overrun raw interrupt status
bits : 1 - 1 (1 bit)

ERR_RIS : Synchronization error raw interrupt status
bits : 2 - 2 (1 bit)

VSYNC_RIS : VSYNC raw interrupt status
bits : 3 - 3 (1 bit)

LINE_RIS : Line raw interrupt status
bits : 4 - 4 (1 bit)


IER

interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAME_IE OVR_IE ERR_IE VSYNC_IE LINE_IE

FRAME_IE : Capture complete interrupt enable
bits : 0 - 0 (1 bit)

OVR_IE : Overrun interrupt enable
bits : 1 - 1 (1 bit)

ERR_IE : Synchronization error interrupt enable
bits : 2 - 2 (1 bit)

VSYNC_IE : VSYNC interrupt enable
bits : 3 - 3 (1 bit)

LINE_IE : Line interrupt enable
bits : 4 - 4 (1 bit)



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