PWR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

add a new register to this peripheral

CR1

SR1

SR2

CR5

PUCRA

PDCRA

PUCRB

PDCRB

CR6

CR7

SR3

CR2

IOxCFG

CR3

DBGR

EXTSRR

DBGSMPS

TRIMR

ENGTRIM

DBG1

DBG2

CR4


CR1

Power control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPMS APC

LPMS : Low Power Mode Selection
bits : 0 - 0 (1 bit)

APC : Apply Pull-up and pull-down configuration from CPU
bits : 4 - 4 (1 bit)


SR1

Power status register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR1 SR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WUF0 WUF1 WUF2 WUF3 WUF4 WUF5 WUF6 WUF7 WUF8 WUF9 WUF10 WUF11 WBLEF WBLEHCPUF IWUF

WUF0 : WakeUp Flag 0
bits : 0 - 0 (1 bit)

WUF1 : WakeUp Flag 1
bits : 1 - 1 (1 bit)

WUF2 : WakeUp Flag 2
bits : 2 - 2 (1 bit)

WUF3 : WakeUp Flag 3
bits : 3 - 3 (1 bit)

WUF4 : WakeUp Flag 4
bits : 4 - 4 (1 bit)

WUF5 : WakeUp Flag 5
bits : 5 - 5 (1 bit)

WUF6 : WakeUp Flag 6
bits : 6 - 6 (1 bit)

WUF7 : WakeUp Flag 7
bits : 7 - 7 (1 bit)

WUF8 : WakeUp Flag 8
bits : 8 - 8 (1 bit)

WUF9 : WakeUp Flag 9
bits : 9 - 9 (1 bit)

WUF10 : WakeUp Flag 10
bits : 10 - 10 (1 bit)

WUF11 : WakeUp Flag 11
bits : 11 - 11 (1 bit)

WBLEF : Wakeup BLE Flag
bits : 12 - 12 (1 bit)

WBLEHCPUF : Wakeup BLE HOST CPU Flag (cf. user manual)
bits : 13 - 13 (1 bit)

IWUF : WakeUp Flag Internal
bits : 15 - 15 (1 bit)


SR2

Power status register 2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR2 SR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMPSBYPR SMPSENR SMPSRDY REGLPS REGMS PVDO IOBOOTVAL

SMPSBYPR : SMPS Force Bypass Control Replica
bits : 0 - 0 (1 bit)

SMPSENR : SMPS Enable Control Replica
bits : 1 - 1 (1 bit)

SMPSRDY : SMPS Ready Status
bits : 2 - 2 (1 bit)

REGLPS : Regulator Low Power Started
bits : 8 - 8 (1 bit)

REGMS : Regulator Main LDO Started
bits : 9 - 9 (1 bit)

PVDO : Power Voltage Detector Output
bits : 11 - 11 (1 bit)

IOBOOTVAL :
bits : 12 - 15 (4 bit)


CR5

Power control register 5
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR5 CR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMPSLVL SMPSBOMSEL SMPSFRDY SMPSLPOPEN SMPSFBYP NOSMPS SMPS_ENA_DCM CLKDETR_DISABLE

SMPSLVL : SMPS Output Level Voltage Selection
bits : 0 - 3 (4 bit)

SMPSBOMSEL : SMPS BOM Selection
bits : 4 - 5 (2 bit)

SMPSFRDY : Force ready check
bits : 7 - 7 (1 bit)

SMPSLPOPEN : In Low Power mode SMPS is in OPEN mode (instead of PRECHARGE mode).
bits : 8 - 8 (1 bit)

SMPSFBYP : Force SMPS Regulator in bypass mode
bits : 9 - 9 (1 bit)

NOSMPS : No SMPS Mode
bits : 10 - 10 (1 bit)

SMPS_ENA_DCM : Discontinuous conduction mode enable.
bits : 11 - 11 (1 bit)

CLKDETR_DISABLE : disable the SMPS clock detection
bits : 12 - 12 (1 bit)


PUCRA

Power Port A pull-up control register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUCRA PUCRA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PUA0 PUA1 PUA2 PUA3 PUA4 PUA5 PUA6 PUA7 PUA8 PUA9 PUA10 PUA11 PUA12 PUA13 PUA14 PUA15

PUA0 : Port A PAll-up bit 0
bits : 0 - 0 (1 bit)

PUA1 : Port A PAll-up bit 1
bits : 1 - 1 (1 bit)

PUA2 : Port A PAll-up bit 2
bits : 2 - 2 (1 bit)

PUA3 : Port A PAll-up bit 3
bits : 3 - 3 (1 bit)

PUA4 : Port A PAll-up bit 4
bits : 4 - 4 (1 bit)

PUA5 : Port A PAll-up bit 5
bits : 5 - 5 (1 bit)

PUA6 : Port A PAll-up bit 6
bits : 6 - 6 (1 bit)

PUA7 : Port A PAll-up bit 7
bits : 7 - 7 (1 bit)

PUA8 : Port A PAll-up bit 8
bits : 8 - 8 (1 bit)

PUA9 : Port A PAll-up bit 9
bits : 9 - 9 (1 bit)

PUA10 : Port A PAll-up bit 10
bits : 10 - 10 (1 bit)

PUA11 : Port A PAll-up bit 11
bits : 11 - 11 (1 bit)

PUA12 : Port A PAll-up bit 12
bits : 12 - 12 (1 bit)

PUA13 : Port A PAll-up bit 13
bits : 13 - 13 (1 bit)

PUA14 : Port A PAll-up bit 14
bits : 14 - 14 (1 bit)

PUA15 : Port A PAll-up bit 15
bits : 15 - 15 (1 bit)


PDCRA

Power Port A pull-down control register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDCRA PDCRA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDA0 PDA1 PDA2 PDA3 PDA4 PDA5 PDA6 PDA7 PDA8 PDA9 PDA10 PDA11 PDA12 PDA13 PDA14 PDA15

PDA0 : Port A pull-down bit 0
bits : 0 - 0 (1 bit)

PDA1 : Port A pull-down bit 1
bits : 1 - 1 (1 bit)

PDA2 : Port A pull-down bit 2
bits : 2 - 2 (1 bit)

PDA3 : Port A pull-down bit 3
bits : 3 - 3 (1 bit)

PDA4 : Port A pull-down bit 4
bits : 4 - 4 (1 bit)

PDA5 : Port A pull-down bit 5
bits : 5 - 5 (1 bit)

PDA6 : Port A pull-down bit 6
bits : 6 - 6 (1 bit)

PDA7 : Port A pull-down bit 7
bits : 7 - 7 (1 bit)

PDA8 : Port A pull-down bit 8
bits : 8 - 8 (1 bit)

PDA9 : Port A pull-down bit 9
bits : 9 - 9 (1 bit)

PDA10 : Port A pull-down bit 10
bits : 10 - 10 (1 bit)

PDA11 : Port A pull-down bit 11
bits : 11 - 11 (1 bit)

PDA12 : Port A pull-down bit 12
bits : 12 - 12 (1 bit)

PDA13 : Port A pull-down bit 13
bits : 13 - 13 (1 bit)

PDA14 : Port A pull-down bit 14
bits : 14 - 14 (1 bit)

PDA15 : Port A pull-down bit 15
bits : 15 - 15 (1 bit)


PUCRB

Power Port B pull-up control register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUCRB PUCRB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PUB0 PUB1 PUB2 PUB3 PUB4 PUB5 PUB6 PUB7 PUB8 PUB9 PUB10 PUB11 PUB12 PUB13 PUB14 PUB15

PUB0 : Port B PBll-up bit 0
bits : 0 - 0 (1 bit)

PUB1 : Port B PBll-up bit 1
bits : 1 - 1 (1 bit)

PUB2 : Port B PBll-up bit 2
bits : 2 - 2 (1 bit)

PUB3 : Port B PBll-up bit 3
bits : 3 - 3 (1 bit)

PUB4 : Port B PBll-up bit 4
bits : 4 - 4 (1 bit)

PUB5 : Port B PBll-up bit 5
bits : 5 - 5 (1 bit)

PUB6 : Port B PBll-up bit 6
bits : 6 - 6 (1 bit)

PUB7 : Port B PBll-up bit 7
bits : 7 - 7 (1 bit)

PUB8 : Port B PBll-up bit 8
bits : 8 - 8 (1 bit)

PUB9 : Port B PBll-up bit 9
bits : 9 - 9 (1 bit)

PUB10 : Port B PBll-up bit 10
bits : 10 - 10 (1 bit)

PUB11 : Port B PBll-up bit 11
bits : 11 - 11 (1 bit)

PUB12 : Port B PBll-up bit 12
bits : 12 - 12 (1 bit)

PUB13 : Port B PBll-up bit 13
bits : 13 - 13 (1 bit)

PUB14 : Port B PBll-up bit 14
bits : 14 - 14 (1 bit)

PUB15 : Port B PBll-up bit 15
bits : 15 - 15 (1 bit)


PDCRB

Power Port B pull-down control register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDCRB PDCRB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDB0 PDB1 PDB2 PDB3 PDB4 PDB5 PDB6 PDB7 PDB8 PDB9 PDB10 PDB11 PDB12 PDB13 PDB14 PDB15

PDB0 : Port B pull-down bit 0
bits : 0 - 0 (1 bit)

PDB1 : Port B pull-down bit 1
bits : 1 - 1 (1 bit)

PDB2 : Port B pull-down bit 2
bits : 2 - 2 (1 bit)

PDB3 : Port B pull-down bit 3
bits : 3 - 3 (1 bit)

PDB4 : Port B pull-down bit 4
bits : 4 - 4 (1 bit)

PDB5 : Port B pull-down bit 5
bits : 5 - 5 (1 bit)

PDB6 : Port B pull-down bit 6
bits : 6 - 6 (1 bit)

PDB7 : Port B pull-down bit 7
bits : 7 - 7 (1 bit)

PDB8 : Port B pull-down bit 8
bits : 8 - 8 (1 bit)

PDB9 : Port B pull-down bit 9
bits : 9 - 9 (1 bit)

PDB10 : Port B pull-down bit 10
bits : 10 - 10 (1 bit)

PDB11 : Port B pull-down bit 11
bits : 11 - 11 (1 bit)

PDB12 : Port B pull-down bit 12
bits : 12 - 12 (1 bit)

PDB13 : Port B pull-down bit 13
bits : 13 - 13 (1 bit)

PDB14 : Port B pull-down bit 14
bits : 14 - 14 (1 bit)

PDB15 : Port B pull-down bit 15
bits : 15 - 15 (1 bit)


CR6

This register manages the selection of the wakeup sources to get out of DEEPSTOP mode
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR6 CR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EWU12 EWU13 EWU14 EWU15 EWU16 EWU17 EWU18 EWU19 EWU20 EWU21 EWU22 EWU23 EWU24 EWU25 EWU26 EWU27

EWU12 : Enable wakeup on PA0 I/O event.
bits : 0 - 0 (1 bit)

EWU13 : Enable wakeup on PA1 I/O event.
bits : 1 - 1 (1 bit)

EWU14 : Enable wakeup on PA2 I/O event.
bits : 2 - 2 (1 bit)

EWU15 : Enable wakeup on PA3 I/O event.
bits : 3 - 3 (1 bit)

EWU16 : Enable wakeup on PA4 I/O event.
bits : 4 - 4 (1 bit)

EWU17 : Enable wakeup on PA5 I/O event.
bits : 5 - 5 (1 bit)

EWU18 : Enable wakeup on PA6 I/O event.
bits : 6 - 6 (1 bit)

EWU19 : Enable wakeup on PA7 I/O event.
bits : 7 - 7 (1 bit)

EWU20 : Enable wakeup on PB8 I/O event.
bits : 8 - 8 (1 bit)

EWU21 : Enable wakeup on PB9 I/O event.
bits : 9 - 9 (1 bit)

EWU22 : Enable wakeup on PB10 I/O event.
bits : 10 - 10 (1 bit)

EWU23 : Enable wakeup on PB11 I/O event.
bits : 11 - 11 (1 bit)

EWU24 : Enable wakeup on PA12 I/O event.
bits : 12 - 12 (1 bit)

EWU25 : Enable wakeup on PA13 I/O event.
bits : 13 - 13 (1 bit)

EWU26 : Enable wakeup on PA14 I/O event.
bits : 14 - 14 (1 bit)

EWU27 : Enable wakeup on PA15 I/O event.
bits : 15 - 15 (1 bit)


CR7

This register manages the polarity for the I/Os wakeup sources to get out of DEEPSTOP
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR7 CR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WUP12 WUP13 WUP14 WUP15 WUP16 WUP17 WUP18 WUP19 WUP20 WUP21 WUP22 WUP23 WUP24 WUP25 WUP26 WUP27

WUP12 : Wakeup polarity for PA0 IO event.
bits : 0 - 0 (1 bit)

WUP13 : Wakeup polarity for PA1 IO event.
bits : 1 - 1 (1 bit)

WUP14 : Wakeup polarity for PA2 IO event.
bits : 2 - 2 (1 bit)

WUP15 : Wakeup polarity for PA3 IO event.
bits : 3 - 3 (1 bit)

WUP16 : Wakeup polarity for PA4 IO event.
bits : 4 - 4 (1 bit)

WUP17 : Wakeup polarity for PA5 IO event.
bits : 5 - 5 (1 bit)

WUP18 : Wakeup polarity for PA6 IO event.
bits : 6 - 6 (1 bit)

WUP19 : Wakeup polarity for PA7 IO event.
bits : 7 - 7 (1 bit)

WUP20 : Wakeup polarity for PB8 IO event.
bits : 8 - 8 (1 bit)

WUP21 : Wakeup polarity for PB9 IO event.
bits : 9 - 9 (1 bit)

WUP22 : Wakeup polarity for PB10 I/O.
bits : 10 - 10 (1 bit)

WUP23 : Wakeup polarity for PB11 I/O.
bits : 11 - 11 (1 bit)

WUP24 : Wakeup polarity for PA12 I/O.
bits : 12 - 12 (1 bit)

WUP25 : Wakeup polarity for PA13 IO event.
bits : 13 - 13 (1 bit)

WUP26 : Wakeup polarity for PA14 I/O.
bits : 14 - 14 (1 bit)

WUP27 : Wakeup polarity for PA15 I/O.
bits : 15 - 15 (1 bit)


SR3

This register provides the information concerning which source woke up the device after a DEEPSTOP.
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR3 SR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WUF12 WUF13 WUF14 WUF15 WUF16 WUF17 WUF18 WUF19 WUF20 WUF21 WUF22 WUF23 WUF24 WUF25 WUF26 WUF27

WUF12 : PA0 I/O wakeup flag.
bits : 0 - 0 (1 bit)

WUF13 : PA1 I/O wakeup flag.
bits : 1 - 1 (1 bit)

WUF14 : PA2 I/O wakeup flag.
bits : 2 - 2 (1 bit)

WUF15 : PA3 I/O wakeup flag.
bits : 3 - 3 (1 bit)

WUF16 : PA4 I/O wakeup flag.
bits : 4 - 4 (1 bit)

WUF17 : PA5 I/O wakeup flag.
bits : 5 - 5 (1 bit)

WUF18 : PA6 I/O wakeup flag.
bits : 6 - 6 (1 bit)

WUF19 : PA7 I/O wakeup flag.
bits : 7 - 7 (1 bit)

WUF20 : PB8 I/O wakeup flag.
bits : 8 - 8 (1 bit)

WUF21 : PB9 I/O wakeup flag.
bits : 9 - 9 (1 bit)

WUF22 : PB10 I/O wakeup flag.
bits : 10 - 10 (1 bit)

WUF23 : PB11 I/O wakeup flag.
bits : 11 - 11 (1 bit)

WUF24 : PA12 I/O wakeup flag.
bits : 12 - 12 (1 bit)

WUF25 : PA13 I/O wakeup flag.
bits : 13 - 13 (1 bit)

WUF26 : PA14 I/O wakeup flag.
bits : 14 - 14 (1 bit)

WUF27 : PA15 I/O wakeup flag.
bits : 15 - 15 (1 bit)


CR2

Power control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PVDE PVDLS RAMRET1 RAMRET2 RAMRET3 SCALEMR ENTS LSILPMUFEN

PVDE : Programmable Voltage Detector Enable
bits : 0 - 0 (1 bit)

PVDLS : Programmable Voltage Detector Level selection
bits : 1 - 3 (3 bit)

RAMRET1 : RAM1 retention during low power mode
bits : 5 - 5 (1 bit)

RAMRET2 : RAM2 retention during low power mode
bits : 6 - 6 (1 bit)

RAMRET3 : RAM3 retention during low power mode
bits : 7 - 7 (1 bit)

SCALEMR : Voltage scaling Main Regulator Selection.
bits : 8 - 8 (1 bit)

ENTS : Enable Temperature Sensor
bits : 9 - 9 (1 bit)

LSILPMUFEN : LSI LPMU Force ENable
bits : 10 - 10 (1 bit)


IOxCFG

IO DEEPSTOP drive configuration register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOxCFG IOxCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOCFG0 IOCFG1 IOCFG2 IOCFG3 IOCFG4 IOCFG5 IOCFG6 IOCFG7

IOCFG0 : Drive configuration for PA8.
bits : 0 - 1 (2 bit)

IOCFG1 : Drive configuration for PA9.
bits : 2 - 3 (2 bit)

IOCFG2 : Drive configuration for PA10.
bits : 4 - 5 (2 bit)

IOCFG3 : Drive configuration for PA11.
bits : 6 - 7 (2 bit)

IOCFG4 : Drive configuration for PA4.
bits : 8 - 9 (2 bit)

IOCFG5 : Drive configuration for PA5.
bits : 10 - 11 (2 bit)

IOCFG6 : Drive configuration for PA6.
bits : 12 - 13 (2 bit)

IOCFG7 : Drive configuration for PA7.
bits : 14 - 15 (2 bit)


CR3

Power control register 3
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR3 CR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EWU0 EWU1 EWU2 EWU3 EWU4 EWU5 EWU6 EWU7 EWU8 EWU9 EWU10 EWU11 EWBLE EWBLEHCPU EIWL

EWU0 : Enable WakeUp line 0
bits : 0 - 0 (1 bit)

EWU1 : Enable WakeUp line 1
bits : 1 - 1 (1 bit)

EWU2 : Enable WakeUp line 2
bits : 2 - 2 (1 bit)

EWU3 : Enable WakeUp line 3
bits : 3 - 3 (1 bit)

EWU4 : Enable WakeUp line 4
bits : 4 - 4 (1 bit)

EWU5 : Enable WakeUp line 5
bits : 5 - 5 (1 bit)

EWU6 : Enable WakeUp line 6
bits : 6 - 6 (1 bit)

EWU7 : Enable WakeUp line 7
bits : 7 - 7 (1 bit)

EWU8 : Enable WakeUp line 8
bits : 8 - 8 (1 bit)

EWU9 : Enable WakeUp line 9
bits : 9 - 9 (1 bit)

EWU10 : Enable WakeUp line 10
bits : 10 - 10 (1 bit)

EWU11 : Enable WakeUp line 11
bits : 11 - 11 (1 bit)

EWBLE : Wakeup BLE Enable
bits : 12 - 12 (1 bit)

EWBLEHCPU : EWBLEHCPU Wakeup BLE Host CPU Enable
bits : 13 - 13 (1 bit)

EIWL : Enable internal WakeUp line
bits : 15 - 15 (1 bit)


DBGR

This register is used for debug features
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGR DBGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEEPSTOP2

DEEPSTOP2 : DEEPSTOP2 low power saving emulation enable.
bits : 0 - 0 (1 bit)


EXTSRR

Power status clear register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTSRR EXTSRR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEEPSTOPF RFPHASEF

DEEPSTOPF : System DeepStop Flag
bits : 9 - 9 (1 bit)

RFPHASEF : RFPHAS Flag
bits : 10 - 10 (1 bit)


DBGSMPS

This register drives some control signals for the SMPS
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGSMPS DBGSMPS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TESTDIG TESTKEL HOT_STUP NO_STUP TESTILIM CTLRES_RAMP DIS_BIG_MOS TEST_OL

TESTDIG : SMPS_TEST_DIG_3V3[3:0] control bus.
bits : 0 - 3 (4 bit)

TESTKEL : SMPS_TEST_KEL_3V3[2:0] control bus.
bits : 4 - 5 (2 bit)

HOT_STUP : HOT_STUP_3V3 SMPS control signal.
bits : 6 - 6 (1 bit)

NO_STUP : NO_STUP_3V3 SMPS control signal.
bits : 7 - 7 (1 bit)

TESTILIM : SMPS_TEST_ILIM_3V3 control signal.
bits : 8 - 8 (1 bit)

CTLRES_RAMP : CTLRES_RAMP_3V3 SMPS control signal.
bits : 9 - 9 (1 bit)

DIS_BIG_MOS : DIS_BIG_MOS_3V3 SMPS control signal.
bits : 10 - 10 (1 bit)

TEST_OL : TEST_OL_3V3 SMPS control signal.
bits : 11 - 11 (1 bit)


TRIMR

This register provides the trimming values applied by hardware according to the trimming done at EWS.
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TRIMR TRIMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIM_LSI_LPMU TRIM_MR SMPS_TRIM RAM_SIZE

TRIM_LSI_LPMU : LPMU low speed internal oscillator trimming.
bits : 0 - 3 (4 bit)

TRIM_MR : Main regulator voltage trimming.
bits : 4 - 7 (4 bit)

SMPS_TRIM : SMPS_TRIM
bits : 8 - 11 (4 bit)

RAM_SIZE : Indicates the RAM size available in the device.
bits : 12 - 13 (2 bit)


ENGTRIM

This register allows the software overloading the hardware trimming flashed at EWS.
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENGTRIM ENGTRIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIMLSILPMUEN TRIM_LSI_LPMU TRIMMREN TRIM_MR SMPSTRIMEN SMPS_TRIM

TRIMLSILPMUEN : TRIM_LSI_LPMU software overload enable.
bits : 0 - 0 (1 bit)

TRIM_LSI_LPMU : LPMU low speed internal oscillator trimming chosen by the software.
bits : 1 - 4 (4 bit)

TRIMMREN : TRIM_MR software overload enable.
bits : 5 - 5 (1 bit)

TRIM_MR : Main regulator voltage trimming chosen by the software.
bits : 6 - 9 (4 bit)

SMPSTRIMEN : SMPS_TRIM software overload enable.
bits : 10 - 10 (1 bit)

SMPS_TRIM : SMPS output voltage trimming chosen by the software.
bits : 11 - 14 (4 bit)


DBG1

This register shows the current states of the FLASH FSM and SMPS FSM.
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DBG1 DBG1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMPS_FSM_STATE FLASH_FSM_STATE

SMPS_FSM_STATE : Indicates the current state of the SMPS FSM inside the PWRC.
bits : 0 - 2 (3 bit)

FLASH_FSM_STATE : Indicates the current state of the FLASH FSM inside the PWRC
bits : 8 - 10 (3 bit)


DBG2

This register shows the current states of the FLASH FSM and SMPS FSM.
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DBG2 DBG2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMU_FSM_STATE RAM_FSM_STATE

PMU_FSM_STATE : Indicates the current state of the PMU FSM inside the PWRC.
bits : 0 - 3 (4 bit)

RAM_FSM_STATE : Indicates the current state of the RAM FSM inside the PWRC
bits : 8 - 9 (2 bit)


CR4

Power control register 4
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR4 CR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WUP0 WUP1 WUP2 WUP3 WUP4 WUP5 WUP6 WUP7 WUP8 WUP9 WUP10 WUP11

WUP0 : Wakeup polarity for PB0 IO event.
bits : 0 - 0 (1 bit)

WUP1 : Wakeup polarity for PB1 IO event.
bits : 1 - 1 (1 bit)

WUP2 : Wakeup polarity for PB2 IO event.
bits : 2 - 2 (1 bit)

WUP3 : Wakeup polarity for PB3 IO event.
bits : 3 - 3 (1 bit)

WUP4 : Wakeup polarity for PB4 IO event.
bits : 4 - 4 (1 bit)

WUP5 : Wakeup polarity for PB5 IO event.
bits : 5 - 5 (1 bit)

WUP6 : Wakeup polarity for PB6 IO event.
bits : 6 - 6 (1 bit)

WUP7 : Wakeup polarity for PB7 IO event.
bits : 7 - 7 (1 bit)

WUP8 : Wakeup polarity for PA8 IO event.
bits : 8 - 8 (1 bit)

WUP9 : Wakeup polarity for PA9 IO event.
bits : 9 - 9 (1 bit)

WUP10 : Wakeup polarity for PA10 I/O.
bits : 10 - 10 (1 bit)

WUP11 : Wakeup polarity for PA11 I/O.
bits : 11 - 11 (1 bit)



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