\n

TIMER32_0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection :

Registers

IR

PC

MCR

MR0

MR1

MR2

MR3

EMR

TCR

PWMC

TC

PR


IR

Interrupt register. The IR can be written to clear interrupts, and can be read to identify which of the five possible interrupt sources are pending.
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IR IR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR0_int MR1_int MR2_int MR3_int

MR0_int : Interrupt flag for match channel 0
bits : 0 - 0 (1 bit)
access : read-write

MR1_int : Interrupt flag for match channel 1
bits : 1 - 1 (1 bit)
access : read-write

MR2_int : Interrupt flag for match channel 2
bits : 2 - 2 (1 bit)
access : read-write

MR3_int : Interrupt flag for match channel 3
bits : 3 - 3 (1 bit)
access : read-write


PC

Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC PC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PC

PC : Prescale counter value
bits : 0 - 31 (32 bit)
access : read-write


MCR

Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCR MCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR0I MR0R MR0S MR1I MR1R MR1S MR2I MR2R MR2S MR3I MR3R MR3S

MR0I : Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0x0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

MR0R : Reset on MR0: the TC will be reset if MR0 matches it
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0x0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

MR0S : Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0x0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

MR1I : Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0x0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

MR1R : Reset on MR1: the TC will be reset if MR1 matches it
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0x0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

MR1S : Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0x0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

MR2I : Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0x0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

MR2R : Reset on MR2: the TC will be reset if MR2 matches it
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0x0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

MR2S : Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0x0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

MR3I : Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0x0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

MR3R : Reset on MR3: the TC will be reset if MR3 matches it
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0x0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

MR3S : Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0x0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.


MR0

Match Register 0 (MR0). MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR0 MR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MATCH

MATCH : Timer counter match value
bits : 0 - 31 (32 bit)
access : read-write


MR1

Match Register 1 (MR1). See MR0 description.
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR1 MR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MATCH

MATCH : Timer counter match value
bits : 0 - 31 (32 bit)
access : read-write


MR2

Match Register 2 (MR1). See MR0 description.
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR2 MR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MATCH

MATCH : Timer counter match value
bits : 0 - 31 (32 bit)
access : read-write


MR3

Match Register 3 (MR1). See MR0 description.
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR3 MR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MATCH

MATCH : Timer counter match value
bits : 0 - 31 (32 bit)
access : read-write


EMR

External Match Register (EMR). The EMR controls the match function and the external match pins CT32B_MAT[1:0].
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EMR EMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EM0 EM1 EMC0 EMC1

EM0 : External Match 0. This bit reflects the state of output CT32B_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B_MAT0 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). Only valid when the timer is enabled.
bits : 0 - 0 (1 bit)
access : read-write

EM1 : External Match 1. This bit reflects the state of output CT32B_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B_MAT1 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). Only valid when the timer is enabled.
bits : 1 - 1 (1 bit)
access : read-write

EMC0 : External match control 0
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : DO_NOTHING

Do Nothing

0x1 : CLEAR

Clear the corresponding External Match bit/output to 0 (CT32B_MAT0 pin is LOW if pinned out).

0x2 : SET

Set the corresponding External Match bit/output to 1 (CT32B_MAT0 pin is HIGH if pinned out).

0x3 : TOGGLE

Toggle the corresponding External Match bit/output.

End of enumeration elements list.

EMC1 : External match control 1
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

0x0 : DO_NOTHING

Do Nothing

0x1 : CLEAR

Clear the corresponding External Match bit/output to 0 (CT32B_MAT1 pin is LOW if pinned out).

0x2 : SET

Set the corresponding External Match bit/output to 1 (CT32B_MAT1 pin is HIGH if pinned out).

0x3 : TOGGLE

Toggle the corresponding External Match bit/output.

End of enumeration elements list.


TCR

Timer control register. The TCR is used to control the timer counter functions. The TC can be disabled or reset through the TCR
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR TCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEn CRst

CEn : Counter Enable. When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled.
bits : 0 - 0 (1 bit)
access : read-write

CRst : Counter Reset. When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
bits : 1 - 1 (1 bit)
access : read-write


PWMC

PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B_MAT[1:0].
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWMC PWMC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWMEN0 PWMEN1

PWMEN0 : PWM channel0 enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0x0 : DISABLED

CT32B_MAT0 is controlled by EM0

0x1 : ENABLED

PWM mode is enabled for CT32B_MAT0

End of enumeration elements list.

PWMEN1 : PWM channel1 enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0x0 : DISABLED

CT32B_MAT1 is controlled by EM1

0x1 : ENABLED

PWM mode is enabled for CT32B_MAT1

End of enumeration elements list.


TC

Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC TC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC

TC : Timer counter value
bits : 0 - 31 (32 bit)
access : read-write


PR

Prescale register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PR PR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PR

PR : Prescale max value
bits : 0 - 31 (32 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.