\n
address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection :
RTC Time Seconds Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSR : Time Seconds Register
bits : 0 - 31 (32 bit)
access : read-write
RTC Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWR : Software Reset
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
End of enumeration elements list.
SUP : Supervisor Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Non-supervisor mode write accesses are not supported and generate a bus error.
#1 : 1
Non-supervisor mode write accesses are supported.
End of enumeration elements list.
UM : Update Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Registers cannot be written when locked.
#1 : 1
Registers can be written when locked under limited conditions.
End of enumeration elements list.
CPS : Clock Pin Select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT.
#1 : 1
The RTC 32.768 kHz clock is output on RTC_CLKOUT, provided it is output to other peripherals.
End of enumeration elements list.
LPOS : LPO Select
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC prescaler increments using 32.768 kHz clock.
#1 : 1
RTC prescaler increments using 1 kHz LPO, bits [4:0] of the prescaler are ignored.
End of enumeration elements list.
CLKO : Clock Output
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The 32 kHz clock is output to other peripherals.
#1 : 1
The 32 kHz clock is not output to other peripherals.
End of enumeration elements list.
CPE : Clock Pin Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
The RTC_CLKOUT function is disabled.
#1 : 1
Enable RTC_CLKOUT function.
End of enumeration elements list.
RTC Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIF : Time Invalid Flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Time is valid.
#1 : 1
Time is invalid and time counter is read as zero.
End of enumeration elements list.
TOF : Time Overflow Flag
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Time overflow has not occurred.
#1 : 1
Time overflow has occurred and time counter is read as zero.
End of enumeration elements list.
TAF : Time Alarm Flag
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Time alarm has not occurred.
#1 : 1
Time alarm has occurred.
End of enumeration elements list.
TCE : Time Counter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time counter is disabled.
#1 : 1
Time counter is enabled.
End of enumeration elements list.
RTC Lock Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCL : Time Compensation Lock
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time Compensation Register is locked and writes are ignored.
#1 : 1
Time Compensation Register is not locked and writes complete as normal.
End of enumeration elements list.
CRL : Control Register Lock
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Control Register is locked and writes are ignored.
#1 : 1
Control Register is not locked and writes complete as normal.
End of enumeration elements list.
SRL : Status Register Lock
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Status Register is locked and writes are ignored.
#1 : 1
Status Register is not locked and writes complete as normal.
End of enumeration elements list.
LRL : Lock Register Lock
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Lock Register is locked and writes are ignored.
#1 : 1
Lock Register is not locked and writes complete as normal.
End of enumeration elements list.
RTC Interrupt Enable Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIIE : Time Invalid Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time invalid flag does not generate an interrupt.
#1 : 1
Time invalid flag does generate an interrupt.
End of enumeration elements list.
TOIE : Time Overflow Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time overflow flag does not generate an interrupt.
#1 : 1
Time overflow flag does generate an interrupt.
End of enumeration elements list.
TAIE : Time Alarm Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time alarm flag does not generate an interrupt.
#1 : 1
Time alarm flag does generate an interrupt.
End of enumeration elements list.
TSIE : Time Seconds Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Seconds interrupt is disabled.
#1 : 1
Seconds interrupt is enabled.
End of enumeration elements list.
TSIC : Timer Seconds Interrupt Configuration
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 000
1 Hz.
#001 : 001
2 Hz.
#010 : 010
4 Hz.
#011 : 011
8 Hz.
#100 : 100
16 Hz.
#101 : 101
32 Hz.
#110 : 110
64 Hz.
#111 : 111
128 Hz.
End of enumeration elements list.
RTC Time Prescaler Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPR : Time Prescaler Register
bits : 0 - 15 (16 bit)
access : read-write
RTC Time Alarm Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TAR : Time Alarm Register
bits : 0 - 31 (32 bit)
access : read-write
RTC Time Compensation Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCR : Time Compensation Register
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
#10000000 : 10000000
Time Prescaler Register overflows every 32896 clock cycles.
#10000001 : 10000001
Time Prescaler Register overflows every 32895 clock cycles.
#11111111 : 11111111
Time Prescaler Register overflows every 32769 clock cycles.
#0 : 00000000
Time Prescaler Register overflows every 32768 clock cycles.
#1 : 00000001
Time Prescaler Register overflows every 32767 clock cycles.
#1111110 : 01111110
Time Prescaler Register overflows every 32642 clock cycles.
#1111111 : 01111111
Time Prescaler Register overflows every 32641 clock cycles.
End of enumeration elements list.
CIR : Compensation Interval Register
bits : 8 - 15 (8 bit)
access : read-write
TCV : Time Compensation Value
bits : 16 - 23 (8 bit)
access : read-only
CIC : Compensation Interval Counter
bits : 24 - 31 (8 bit)
access : read-only
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.