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RTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection :

Registers

TSR

CR

SR

LR

IER

TPR

TAR

TCR


TSR

RTC Time Seconds Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSR TSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSR

TSR : Time Seconds Register
bits : 0 - 31 (32 bit)
access : read-write


CR

RTC Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWR SUP UM CPS LPOS CLKO CPE

SWR : Software Reset
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect.

End of enumeration elements list.

SUP : Supervisor Access
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Non-supervisor mode write accesses are not supported and generate a bus error.

#1 : 1

Non-supervisor mode write accesses are supported.

End of enumeration elements list.

UM : Update Mode
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Registers cannot be written when locked.

#1 : 1

Registers can be written when locked under limited conditions.

End of enumeration elements list.

CPS : Clock Pin Select
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT.

#1 : 1

The RTC 32.768 kHz clock is output on RTC_CLKOUT, provided it is output to other peripherals.

End of enumeration elements list.

LPOS : LPO Select
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

RTC prescaler increments using 32.768 kHz clock.

#1 : 1

RTC prescaler increments using 1 kHz LPO, bits [4:0] of the prescaler are ignored.

End of enumeration elements list.

CLKO : Clock Output
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

The 32 kHz clock is output to other peripherals.

#1 : 1

The 32 kHz clock is not output to other peripherals.

End of enumeration elements list.

CPE : Clock Pin Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

The RTC_CLKOUT function is disabled.

#1 : 1

Enable RTC_CLKOUT function.

End of enumeration elements list.


SR

RTC Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIF TOF TAF TCE

TIF : Time Invalid Flag
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Time is valid.

#1 : 1

Time is invalid and time counter is read as zero.

End of enumeration elements list.

TOF : Time Overflow Flag
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Time overflow has not occurred.

#1 : 1

Time overflow has occurred and time counter is read as zero.

End of enumeration elements list.

TAF : Time Alarm Flag
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Time alarm has not occurred.

#1 : 1

Time alarm has occurred.

End of enumeration elements list.

TCE : Time Counter Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Time counter is disabled.

#1 : 1

Time counter is enabled.

End of enumeration elements list.


LR

RTC Lock Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LR LR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCL CRL SRL LRL

TCL : Time Compensation Lock
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Time Compensation Register is locked and writes are ignored.

#1 : 1

Time Compensation Register is not locked and writes complete as normal.

End of enumeration elements list.

CRL : Control Register Lock
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Control Register is locked and writes are ignored.

#1 : 1

Control Register is not locked and writes complete as normal.

End of enumeration elements list.

SRL : Status Register Lock
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Status Register is locked and writes are ignored.

#1 : 1

Status Register is not locked and writes complete as normal.

End of enumeration elements list.

LRL : Lock Register Lock
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Lock Register is locked and writes are ignored.

#1 : 1

Lock Register is not locked and writes complete as normal.

End of enumeration elements list.


IER

RTC Interrupt Enable Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIIE TOIE TAIE TSIE TSIC

TIIE : Time Invalid Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Time invalid flag does not generate an interrupt.

#1 : 1

Time invalid flag does generate an interrupt.

End of enumeration elements list.

TOIE : Time Overflow Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Time overflow flag does not generate an interrupt.

#1 : 1

Time overflow flag does generate an interrupt.

End of enumeration elements list.

TAIE : Time Alarm Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Time alarm flag does not generate an interrupt.

#1 : 1

Time alarm flag does generate an interrupt.

End of enumeration elements list.

TSIE : Time Seconds Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Seconds interrupt is disabled.

#1 : 1

Seconds interrupt is enabled.

End of enumeration elements list.

TSIC : Timer Seconds Interrupt Configuration
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#000 : 000

1 Hz.

#001 : 001

2 Hz.

#010 : 010

4 Hz.

#011 : 011

8 Hz.

#100 : 100

16 Hz.

#101 : 101

32 Hz.

#110 : 110

64 Hz.

#111 : 111

128 Hz.

End of enumeration elements list.


TPR

RTC Time Prescaler Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPR TPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TPR

TPR : Time Prescaler Register
bits : 0 - 15 (16 bit)
access : read-write


TAR

RTC Time Alarm Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAR TAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAR

TAR : Time Alarm Register
bits : 0 - 31 (32 bit)
access : read-write


TCR

RTC Time Compensation Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR TCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCR CIR TCV CIC

TCR : Time Compensation Register
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

#10000000 : 10000000

Time Prescaler Register overflows every 32896 clock cycles.

#10000001 : 10000001

Time Prescaler Register overflows every 32895 clock cycles.

#11111111 : 11111111

Time Prescaler Register overflows every 32769 clock cycles.

#0 : 00000000

Time Prescaler Register overflows every 32768 clock cycles.

#1 : 00000001

Time Prescaler Register overflows every 32767 clock cycles.

#1111110 : 01111110

Time Prescaler Register overflows every 32642 clock cycles.

#1111111 : 01111111

Time Prescaler Register overflows every 32641 clock cycles.

End of enumeration elements list.

CIR : Compensation Interval Register
bits : 8 - 15 (8 bit)
access : read-write

TCV : Time Compensation Value
bits : 16 - 23 (8 bit)
access : read-only

CIC : Compensation Interval Counter
bits : 24 - 31 (8 bit)
access : read-only



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