Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1D0 byte (0x0)
mem_usage : registers
protection :
PCC LPTMR0 Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCD : Peripheral Clock Divider Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 000
Divide by 1.
#001 : 001
Divide by 2.
#010 : 010
Divide by 3.
#011 : 011
Divide by 4.
#100 : 100
Divide by 5.
#101 : 101
Divide by 6.
#110 : 110
Divide by 7.
#111 : 111
Divide by 8.
End of enumeration elements list.
FRAC : Peripheral Clock Divider Fraction
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fractional value is 0.
#1 : 1
Fractional value is 1.
End of enumeration elements list.
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock is off.
#001 : 001
Clock option 1
#010 : 010
Clock option 2
#011 : 011
Clock option 3
#100 : 100
Clock option 4
#101 : 101
Clock option 5
#110 : 110
Clock option 6
#111 : 111
Clock option 7
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC PORTA Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC PORTB Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC PORTC Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC PORTD Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC PORTE Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC FlexIO Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock is off.
#001 : 001
Clock option 1
#010 : 010
Clock option 2
#011 : 011
Clock option 3
#100 : 100
Clock option 4
#101 : 101
Clock option 5
#110 : 110
Clock option 6
#111 : 111
Clock option 7
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC EWM Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC LPI2C0 Register
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock is off.
#001 : 001
Clock option 1
#010 : 010
Clock option 2
#011 : 011
Clock option 3
#100 : 100
Clock option 4
#101 : 101
Clock option 5
#110 : 110
Clock option 6
#111 : 111
Clock option 7
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC LPUART0 Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock is off.
#001 : 001
Clock option 1
#010 : 010
Clock option 2
#011 : 011
Clock option 3
#100 : 100
Clock option 4
#101 : 101
Clock option 5
#110 : 110
Clock option 6
#111 : 111
Clock option 7
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC LPUART1 Register
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock is off.
#001 : 001
Clock option 1
#010 : 010
Clock option 2
#011 : 011
Clock option 3
#100 : 100
Clock option 4
#101 : 101
Clock option 5
#110 : 110
Clock option 6
#111 : 111
Clock option 7
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC CMP0 Register
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC FTFC Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC DMAMUX Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC FlexCAN0 Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC FlexCAN1 Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC FTM3 Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock is off. An external clock can be enabled for this peripheral.
#001 : 001
Clock option 1
#010 : 010
Clock option 2
#011 : 011
Clock option 3
#100 : 100
Clock option 4
#101 : 101
Clock option 5
#110 : 110
Clock option 6
#111 : 111
Clock option 7
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC ADC1 Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock is off.
#001 : 001
Clock option 1
#010 : 010
Clock option 2
#011 : 011
Clock option 3
#100 : 100
Clock option 4
#101 : 101
Clock option 5
#110 : 110
Clock option 6
#111 : 111
Clock option 7
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC LPSPI0 Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock is off.
#001 : 001
Clock option 1
#010 : 010
Clock option 2
#011 : 011
Clock option 3
#100 : 100
Clock option 4
#101 : 101
Clock option 5
#110 : 110
Clock option 6
#111 : 111
Clock option 7
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC LPSPI1 Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock is off.
#001 : 001
Clock option 1
#010 : 010
Clock option 2
#011 : 011
Clock option 3
#100 : 100
Clock option 4
#101 : 101
Clock option 5
#110 : 110
Clock option 6
#111 : 111
Clock option 7
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC PDB1 Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC CRC Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC PDB0 Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC LPIT Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock is off.
#001 : 001
Clock option 1
#010 : 010
Clock option 2
#011 : 011
Clock option 3
#100 : 100
Clock option 4
#101 : 101
Clock option 5
#110 : 110
Clock option 6
#111 : 111
Clock option 7
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC FTM0 Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock is off. An external clock can be enabled for this peripheral.
#001 : 001
Clock option 1
#010 : 010
Clock option 2
#011 : 011
Clock option 3
#100 : 100
Clock option 4
#101 : 101
Clock option 5
#110 : 110
Clock option 6
#111 : 111
Clock option 7
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC FTM1 Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock is off. An external clock can be enabled for this peripheral.
#001 : 001
Clock option 1
#010 : 010
Clock option 2
#011 : 011
Clock option 3
#100 : 100
Clock option 4
#101 : 101
Clock option 5
#110 : 110
Clock option 6
#111 : 111
Clock option 7
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC FTM2 Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock is off. An external clock can be enabled for this peripheral.
#001 : 001
Clock option 1
#010 : 010
Clock option 2
#011 : 011
Clock option 3
#100 : 100
Clock option 4
#101 : 101
Clock option 5
#110 : 110
Clock option 6
#111 : 111
Clock option 7
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC ADC0 Register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock is off.
#001 : 001
Clock option 1
#010 : 010
Clock option 2
#011 : 011
Clock option 3
#100 : 100
Clock option 4
#101 : 101
Clock option 5
#110 : 110
Clock option 6
#111 : 111
Clock option 7
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC RTC Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled. The current clock selection and divider options are locked.
End of enumeration elements list.
PR : Present
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
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