\n

MSCM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x40C byte (0x0)
mem_usage : registers
protection :

Registers

CPxTYPE

CPxCFG0

CPxCFG1

CPxCFG2

CPxCFG3

CP0TYPE

CP0NUM

CP0MASTER

CP0COUNT

CP0CFG0

CP0CFG1

CP0CFG2

CP0CFG3

CPxNUM

OCMDR0

OCMDR1

OCMDR2

CPxMASTER

CPxCOUNT


CPxTYPE

Processor X Type Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CPxTYPE CPxTYPE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RYPZ PERSONALITY

RYPZ : Processor x Revision
bits : 0 - 7 (8 bit)
access : read-only

PERSONALITY : Processor x Personality
bits : 8 - 31 (24 bit)
access : read-only


CPxCFG0

Processor X Configuration Register 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CPxCFG0 CPxCFG0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCWY DCSZ ICWY ICSZ

DCWY : Level 1 Data Cache Ways
bits : 0 - 7 (8 bit)
access : read-only

DCSZ : Level 1 Data Cache Size
bits : 8 - 15 (8 bit)
access : read-only

ICWY : Level 1 Instruction Cache Ways
bits : 16 - 23 (8 bit)
access : read-only

ICSZ : Level 1 Instruction Cache Size
bits : 24 - 31 (8 bit)
access : read-only


CPxCFG1

Processor X Configuration Register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CPxCFG1 CPxCFG1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L2WY L2SZ

L2WY : Level 2 Instruction Cache Ways
bits : 16 - 23 (8 bit)
access : read-only

L2SZ : Level 2 Instruction Cache Size
bits : 24 - 31 (8 bit)
access : read-only


CPxCFG2

Processor X Configuration Register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CPxCFG2 CPxCFG2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMUSZ TMLSZ

TMUSZ : Tightly-coupled Memory Upper Size
bits : 8 - 15 (8 bit)
access : read-only

TMLSZ : Tightly-coupled Memory Lower Size
bits : 24 - 31 (8 bit)
access : read-only


CPxCFG3

Processor X Configuration Register 3
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CPxCFG3 CPxCFG3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FPU SIMD JAZ MMU TZ CMP BB SBP

FPU : Floating Point Unit
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : FPU_0

FPU support is not included.

0x1 : FPU_1

FPU support is included.

End of enumeration elements list.

SIMD : SIMD/NEON instruction support
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

0 : SIMD_0

SIMD/NEON support is not included.

0x1 : SIMD_1

SIMD/NEON support is included.

End of enumeration elements list.

JAZ : Jazelle support
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

0 : JAZ_0

Jazelle support is not included.

0x1 : JAZ_1

Jazelle support is included.

End of enumeration elements list.

MMU : Memory Management Unit
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

0 : MMU_0

MMU support is not included.

0x1 : MMU_1

MMU support is included.

End of enumeration elements list.

TZ : Trust Zone
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

0 : TZ_0

Trust Zone support is not included.

0x1 : TZ_1

Trust Zone support is included.

End of enumeration elements list.

CMP : Core Memory Protection unit
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

0 : CMP_0

Core Memory Protection is not included.

0x1 : CMP_1

Core Memory Protection is included.

End of enumeration elements list.

BB : Bit Banding
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

0 : BB_0

Bit Banding is not supported.

0x1 : BB_1

Bit Banding is supported.

End of enumeration elements list.

SBP : System Bus Ports
bits : 8 - 9 (2 bit)
access : read-only


CP0TYPE

Processor 0 Type Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CP0TYPE CP0TYPE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RYPZ PERSONALITY

RYPZ : Processor 0 Revision
bits : 0 - 7 (8 bit)
access : read-only

PERSONALITY : Processor 0 Personality
bits : 8 - 31 (24 bit)
access : read-only


CP0NUM

Processor 0 Number Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CP0NUM CP0NUM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPN

CPN : Processor 0 Number
bits : 0 - 0 (1 bit)
access : read-only


CP0MASTER

Processor 0 Master Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CP0MASTER CP0MASTER read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPMN

PPMN : Processor 0 Physical Master Number
bits : 0 - 5 (6 bit)
access : read-only


CP0COUNT

Processor 0 Count Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CP0COUNT CP0COUNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCNT

PCNT : Processor Count
bits : 0 - 1 (2 bit)
access : read-only


CP0CFG0

Processor 0 Configuration Register 0
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CP0CFG0 CP0CFG0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCWY DCSZ ICWY ICSZ

DCWY : Level 1 Data Cache Ways
bits : 0 - 7 (8 bit)
access : read-only

DCSZ : Level 1 Data Cache Size
bits : 8 - 15 (8 bit)
access : read-only

ICWY : Level 1 Instruction Cache Ways
bits : 16 - 23 (8 bit)
access : read-only

ICSZ : Level 1 Instruction Cache Size
bits : 24 - 31 (8 bit)
access : read-only


CP0CFG1

Processor 0 Configuration Register 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CP0CFG1 CP0CFG1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L2WY L2SZ

L2WY : Level 2 Instruction Cache Ways
bits : 16 - 23 (8 bit)
access : read-only

L2SZ : Level 2 Instruction Cache Size
bits : 24 - 31 (8 bit)
access : read-only


CP0CFG2

Processor 0 Configuration Register 2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CP0CFG2 CP0CFG2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMUSZ TMLSZ

TMUSZ : Tightly-coupled Memory Upper Size
bits : 8 - 15 (8 bit)
access : read-only

TMLSZ : Tightly-coupled Memory Lower Size
bits : 24 - 31 (8 bit)
access : read-only


CP0CFG3

Processor 0 Configuration Register 3
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CP0CFG3 CP0CFG3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FPU SIMD JAZ MMU TZ CMP BB SBP

FPU : Floating Point Unit
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : FPU_0

FPU support is not included.

0x1 : FPU_1

FPU support is included.

End of enumeration elements list.

SIMD : SIMD/NEON instruction support
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

0 : SIMD_0

SIMD/NEON support is not included.

0x1 : SIMD_1

SIMD/NEON support is included.

End of enumeration elements list.

JAZ : Jazelle support
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

0 : JAZ_0

Jazelle support is not included.

0x1 : JAZ_1

Jazelle support is included.

End of enumeration elements list.

MMU : Memory Management Unit
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

0 : MMU_0

MMU support is not included.

0x1 : MMU_1

MMU support is included.

End of enumeration elements list.

TZ : Trust Zone
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

0 : TZ_0

Trust Zone support is not included.

0x1 : TZ_1

Trust Zone support is included.

End of enumeration elements list.

CMP : Core Memory Protection unit
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

0 : CMP_0

Core Memory Protection is not included.

0x1 : CMP_1

Core Memory Protection is included.

End of enumeration elements list.

BB : Bit Banding
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

0 : BB_0

Bit Banding is not supported.

0x1 : BB_1

Bit Banding is supported.

End of enumeration elements list.

SBP : System Bus Ports
bits : 8 - 9 (2 bit)
access : read-only


CPxNUM

Processor X Number Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CPxNUM CPxNUM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPN

CPN : Processor x Number
bits : 0 - 0 (1 bit)
access : read-only


OCMDR0

On-Chip Memory Descriptor Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCMDR0 OCMDR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCM1 OCMPU OCMT RO OCMW OCMSZ OCMSZH V

OCM1 : OCMEM Control Field 1
bits : 4 - 5 (2 bit)
access : read-write

OCMPU : OCMPU
bits : 12 - 12 (1 bit)
access : read-only

OCMT : OCMT
bits : 13 - 15 (3 bit)
access : read-only

Enumeration:

0x4 : OCMT_4

OCMEMn is a Program Flash.

0x5 : OCMT_5

OCMEMn is a Data Flash.

0x6 : OCMT_6

OCMEMn is an EEE.

End of enumeration elements list.

RO : RO
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : RO_0

Writes to the OCMDRn[11:0] are allowed

0x1 : RO_1

Writes to the OCMDRn[11:0] are ignored

End of enumeration elements list.

OCMW : OCMW
bits : 17 - 19 (3 bit)
access : read-only

Enumeration:

0x2 : OCMW_2

OCMEMn 32-bits wide

0x3 : OCMW_3

OCMEMn 64-bits wide

0x4 : OCMW_4

OCMEMn 128-bits wide

0x5 : OCMW_5

OCMEMn 256-bits wide

End of enumeration elements list.

OCMSZ : OCMSZ
bits : 24 - 27 (4 bit)
access : read-only

Enumeration:

0 : OCMSZ_0

no OCMEMn

0x1 : OCMSZ_1

1KB OCMEMn

0x2 : OCMSZ_2

2KB OCMEMn

0x3 : OCMSZ_3

4KB OCMEMn

0x4 : OCMSZ_4

8KB OCMEMn

0x5 : OCMSZ_5

16KB OCMEMn

0x6 : OCMSZ_6

32KB OCMEMn

0x7 : OCMSZ_7

64KB OCMEMn

0x8 : OCMSZ_8

128KB OCMEMn

0x9 : OCMSZ_9

256KB OCMEMn

0xA : OCMSZ_10

512KB OCMEMn

0xB : OCMSZ_11

1MB OCMEMn

0xC : OCMSZ_12

2MB OCMEMn

0xD : OCMSZ_13

4MB OCMEMn

0xE : OCMSZ_14

8MB OCMEMn

0xF : OCMSZ_15

16MB OCMEMn

End of enumeration elements list.

OCMSZH : OCMSZH
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

0 : OCMSZH_0

OCMEMn is a power-of-2 capacity.

0x1 : OCMSZH_1

OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.

End of enumeration elements list.

V : V
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : V_0

OCMEMn is not present.

0x1 : V_1

OCMEMn is present.

End of enumeration elements list.


OCMDR1

On-Chip Memory Descriptor Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCMDR1 OCMDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCM1 OCMPU OCMT RO OCMW OCMSZ OCMSZH V

OCM1 : OCMEM Control Field 1
bits : 4 - 5 (2 bit)
access : read-write

OCMPU : OCMPU
bits : 12 - 12 (1 bit)
access : read-only

OCMT : OCMT
bits : 13 - 15 (3 bit)
access : read-only

Enumeration:

0x4 : OCMT_4

OCMEMn is a Program Flash.

0x5 : OCMT_5

OCMEMn is a Data Flash.

0x6 : OCMT_6

OCMEMn is an EEE.

End of enumeration elements list.

RO : RO
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : RO_0

Writes to the OCMDRn[11:0] are allowed

0x1 : RO_1

Writes to the OCMDRn[11:0] are ignored

End of enumeration elements list.

OCMW : OCMW
bits : 17 - 19 (3 bit)
access : read-only

Enumeration:

0x2 : OCMW_2

OCMEMn 32-bits wide

0x3 : OCMW_3

OCMEMn 64-bits wide

0x4 : OCMW_4

OCMEMn 128-bits wide

0x5 : OCMW_5

OCMEMn 256-bits wide

End of enumeration elements list.

OCMSZ : OCMSZ
bits : 24 - 27 (4 bit)
access : read-only

Enumeration:

0 : OCMSZ_0

no OCMEMn

0x1 : OCMSZ_1

1KB OCMEMn

0x2 : OCMSZ_2

2KB OCMEMn

0x3 : OCMSZ_3

4KB OCMEMn

0x4 : OCMSZ_4

8KB OCMEMn

0x5 : OCMSZ_5

16KB OCMEMn

0x6 : OCMSZ_6

32KB OCMEMn

0x7 : OCMSZ_7

64KB OCMEMn

0x8 : OCMSZ_8

128KB OCMEMn

0x9 : OCMSZ_9

256KB OCMEMn

0xA : OCMSZ_10

512KB OCMEMn

0xB : OCMSZ_11

1MB OCMEMn

0xC : OCMSZ_12

2MB OCMEMn

0xD : OCMSZ_13

4MB OCMEMn

0xE : OCMSZ_14

8MB OCMEMn

0xF : OCMSZ_15

16MB OCMEMn

End of enumeration elements list.

OCMSZH : OCMSZH
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

0 : OCMSZH_0

OCMEMn is a power-of-2 capacity.

0x1 : OCMSZH_1

OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.

End of enumeration elements list.

V : V
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : V_0

OCMEMn is not present.

0x1 : V_1

OCMEMn is present.

End of enumeration elements list.


OCMDR2

On-Chip Memory Descriptor Register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCMDR2 OCMDR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCMPU OCMT RO OCMW OCMSZ OCMSZH V

OCMPU : OCMPU
bits : 12 - 12 (1 bit)
access : read-only

OCMT : OCMT
bits : 13 - 15 (3 bit)
access : read-only

Enumeration:

0x4 : OCMT_4

OCMEMn is a Program Flash.

0x5 : OCMT_5

OCMEMn is a Data Flash.

0x6 : OCMT_6

OCMEMn is an EEE.

End of enumeration elements list.

RO : RO
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : RO_0

Writes to the OCMDRn[11:0] are allowed

0x1 : RO_1

Writes to the OCMDRn[11:0] are ignored

End of enumeration elements list.

OCMW : OCMW
bits : 17 - 19 (3 bit)
access : read-only

Enumeration:

0x2 : OCMW_2

OCMEMn 32-bits wide

0x3 : OCMW_3

OCMEMn 64-bits wide

0x4 : OCMW_4

OCMEMn 128-bits wide

0x5 : OCMW_5

OCMEMn 256-bits wide

End of enumeration elements list.

OCMSZ : OCMSZ
bits : 24 - 27 (4 bit)
access : read-only

Enumeration:

0 : OCMSZ_0

no OCMEMn

0x1 : OCMSZ_1

1KB OCMEMn

0x2 : OCMSZ_2

2KB OCMEMn

0x3 : OCMSZ_3

4KB OCMEMn

0x4 : OCMSZ_4

8KB OCMEMn

0x5 : OCMSZ_5

16KB OCMEMn

0x6 : OCMSZ_6

32KB OCMEMn

0x7 : OCMSZ_7

64KB OCMEMn

0x8 : OCMSZ_8

128KB OCMEMn

0x9 : OCMSZ_9

256KB OCMEMn

0xA : OCMSZ_10

512KB OCMEMn

0xB : OCMSZ_11

1MB OCMEMn

0xC : OCMSZ_12

2MB OCMEMn

0xD : OCMSZ_13

4MB OCMEMn

0xE : OCMSZ_14

8MB OCMEMn

0xF : OCMSZ_15

16MB OCMEMn

End of enumeration elements list.

OCMSZH : OCMSZH
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

0 : OCMSZH_0

OCMEMn is a power-of-2 capacity.

0x1 : OCMSZH_1

OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.

End of enumeration elements list.

V : V
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : V_0

OCMEMn is not present.

0x1 : V_1

OCMEMn is present.

End of enumeration elements list.


CPxMASTER

Processor X Master Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CPxMASTER CPxMASTER read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPMN

PPMN : Processor x Physical Master Number
bits : 0 - 5 (6 bit)
access : read-only


CPxCOUNT

Processor X Count Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CPxCOUNT CPxCOUNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCNT

PCNT : Processor Count
bits : 0 - 1 (2 bit)
access : read-only



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