Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection :
Cache control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENCACHE : Cache enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Cache disabled
#1 : 1
Cache enabled
End of enumeration elements list.
PCCR2 : Forces all cacheable spaces to write through
bits : 2 - 2 (1 bit)
access : read-write
PCCR3 : Forces no allocation on cache misses (must also have PCCR2 asserted)
bits : 3 - 3 (1 bit)
access : read-write
INVW0 : Invalidate Way 0
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
No operation
#1 : 1
When setting the GO bit, invalidate all lines in way 0.
End of enumeration elements list.
PUSHW0 : Push Way 0
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
No operation
#1 : 1
When setting the GO bit, push all modified lines in way 0
End of enumeration elements list.
INVW1 : Invalidate Way 1
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
No operation
#1 : 1
When setting the GO bit, invalidate all lines in way 1
End of enumeration elements list.
PUSHW1 : Push Way 1
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
No operation
#1 : 1
When setting the GO bit, push all modified lines in way 1
End of enumeration elements list.
GO : Initiate Cache Command
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Write: no effect. Read: no cache command active.
#1 : 1
Write: initiate command indicated by bits 27-24. Read: cache command active.
End of enumeration elements list.
Cache regions mode register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R15 : Region 15 mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
Non-cacheable
#01 : 01
Non-cacheable
#10 : 10
Write-through
#11 : 11
Write-back
End of enumeration elements list.
R14 : Region 14 mode
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
Non-cacheable
#01 : 01
Non-cacheable
#10 : 10
Write-through
#11 : 11
Write-back
End of enumeration elements list.
R13 : Region 13 mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
Non-cacheable
#01 : 01
Non-cacheable
#10 : 10
Write-through
#11 : 11
Write-back
End of enumeration elements list.
R12 : Region 12 mode
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
Non-cacheable
#01 : 01
Non-cacheable
#10 : 10
Write-through
#11 : 11
Write-back
End of enumeration elements list.
R11 : Region 11 mode
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
Non-cacheable
#01 : 01
Non-cacheable
#10 : 10
Write-through
#11 : 11
Write-back
End of enumeration elements list.
R10 : Region 10 mode
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 00
Non-cacheable
#01 : 01
Non-cacheable
#10 : 10
Write-through
#11 : 11
Write-back
End of enumeration elements list.
R9 : Region 9 mode
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 00
Non-cacheable
#01 : 01
Non-cacheable
#10 : 10
Write-through
#11 : 11
Write-back
End of enumeration elements list.
R8 : Region 8 mode
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
Non-cacheable
#01 : 01
Non-cacheable
#10 : 10
Write-through
#11 : 11
Write-back
End of enumeration elements list.
R7 : Region 7 mode
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
Non-cacheable
#01 : 01
Non-cacheable
#10 : 10
Write-through
#11 : 11
Write-back
End of enumeration elements list.
R6 : Region 6 mode
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
Non-cacheable
#01 : 01
Non-cacheable
#10 : 10
Write-through
#11 : 11
Write-back
End of enumeration elements list.
R5 : Region 5 mode
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
Non-cacheable
#01 : 01
Non-cacheable
#10 : 10
Write-through
#11 : 11
Write-back
End of enumeration elements list.
R4 : Region 4 mode
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 00
Non-cacheable
#01 : 01
Non-cacheable
#10 : 10
Write-through
#11 : 11
Write-back
End of enumeration elements list.
R3 : Region 3 mode
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
Non-cacheable
#01 : 01
Non-cacheable
#10 : 10
Write-through
#11 : 11
Write-back
End of enumeration elements list.
R2 : Region 2 mode
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 00
Non-cacheable
#01 : 01
Non-cacheable
#10 : 10
Write-through
#11 : 11
Write-back
End of enumeration elements list.
R1 : Region 1 mode
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 00
Non-cacheable
#01 : 01
Non-cacheable
#10 : 10
Write-through
#11 : 11
Write-back
End of enumeration elements list.
R0 : Region 0 mode
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 00
Non-cacheable
#01 : 01
Non-cacheable
#10 : 10
Write-through
#11 : 11
Write-back
End of enumeration elements list.
Cache line control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LGO : Initiate Cache Line Command
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Write: no effect. Read: no line command active.
#1 : 1
Write: initiate line command indicated by bits 27-24. Read: line command active.
End of enumeration elements list.
CACHEADDR : Cache address
bits : 2 - 13 (12 bit)
access : read-write
WSEL : Way select
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Way 0
#1 : 1
Way 1
End of enumeration elements list.
TDSEL : Tag/Data Select
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data
#1 : 1
Tag
End of enumeration elements list.
LCIVB : Line Command Initial Valid Bit
bits : 20 - 20 (1 bit)
access : read-write
LCIMB : Line Command Initial Modified Bit
bits : 21 - 21 (1 bit)
access : read-write
LCWAY : Line Command Way
bits : 22 - 22 (1 bit)
access : read-write
LCMD : Line Command
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
Search and read or write
#01 : 01
Invalidate
#10 : 10
Push
#11 : 11
Clear
End of enumeration elements list.
LADSEL : Line Address Select
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Cache address
#1 : 1
Physical address
End of enumeration elements list.
LACC : Line access type
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Read
#1 : 1
Write
End of enumeration elements list.
Cache search address register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LGO : Initiate Cache Line Command
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Write: no effect. Read: no line command active.
#1 : 1
Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active.
End of enumeration elements list.
PHYADDR : Physical Address
bits : 2 - 31 (30 bit)
access : read-write
Cache read/write value register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Cache read/write Data
bits : 0 - 31 (32 bit)
access : read-write
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