\n
address_offset : 0x0 Bytes (0x0)
size : 0x40C byte (0x0)
mem_usage : registers
protection :
Processor X Type Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RYPZ : Processor x Revision
bits : 0 - 7 (8 bit)
access : read-only
PERSONALITY : Processor x Personality
bits : 8 - 31 (24 bit)
access : read-only
Processor X Configuration Register 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCWY : Level 1 Data Cache Ways
bits : 0 - 7 (8 bit)
access : read-only
DCSZ : Level 1 Data Cache Size
bits : 8 - 15 (8 bit)
access : read-only
ICWY : Level 1 Instruction Cache Ways
bits : 16 - 23 (8 bit)
access : read-only
ICSZ : Level 1 Instruction Cache Size
bits : 24 - 31 (8 bit)
access : read-only
Processor X Configuration Register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
L2WY : Level 2 Instruction Cache Ways
bits : 16 - 23 (8 bit)
access : read-only
L2SZ : Level 2 Instruction Cache Size
bits : 24 - 31 (8 bit)
access : read-only
Processor X Configuration Register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TMUSZ : Tightly-coupled Memory Upper Size
bits : 8 - 15 (8 bit)
access : read-only
TMLSZ : Tightly-coupled Memory Lower Size
bits : 24 - 31 (8 bit)
access : read-only
Processor X Configuration Register 3
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FPU : Floating Point Unit
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
FPU support is not included.
#1 : 1
FPU support is included.
End of enumeration elements list.
SIMD : SIMD/NEON instruction support
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
SIMD/NEON support is not included.
#1 : 1
SIMD/NEON support is included.
End of enumeration elements list.
JAZ : Jazelle support
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Jazelle support is not included.
#1 : 1
Jazelle support is included.
End of enumeration elements list.
MMU : Memory Management Unit
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
MMU support is not included.
#1 : 1
MMU support is included.
End of enumeration elements list.
TZ : Trust Zone
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Trust Zone support is not included.
#1 : 1
Trust Zone support is included.
End of enumeration elements list.
CMP : Core Memory Protection unit
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Core Memory Protection is not included.
#1 : 1
Core Memory Protection is included.
End of enumeration elements list.
BB : Bit Banding
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Bit Banding is not supported.
#1 : 1
Bit Banding is supported.
End of enumeration elements list.
SBP : System Bus Ports
bits : 8 - 9 (2 bit)
access : read-only
Processor 0 Type Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RYPZ : Processor 0 Revision
bits : 0 - 7 (8 bit)
access : read-only
PERSONALITY : Processor 0 Personality
bits : 8 - 31 (24 bit)
access : read-only
Processor 0 Number Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPN : Processor 0 Number
bits : 0 - 0 (1 bit)
access : read-only
Processor 0 Master Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PPMN : Processor 0 Physical Master Number
bits : 0 - 5 (6 bit)
access : read-only
Processor 0 Count Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PCNT : Processor Count
bits : 0 - 1 (2 bit)
access : read-only
Processor 0 Configuration Register 0
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCWY : Level 1 Data Cache Ways
bits : 0 - 7 (8 bit)
access : read-only
DCSZ : Level 1 Data Cache Size
bits : 8 - 15 (8 bit)
access : read-only
ICWY : Level 1 Instruction Cache Ways
bits : 16 - 23 (8 bit)
access : read-only
ICSZ : Level 1 Instruction Cache Size
bits : 24 - 31 (8 bit)
access : read-only
Processor 0 Configuration Register 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
L2WY : Level 2 Instruction Cache Ways
bits : 16 - 23 (8 bit)
access : read-only
L2SZ : Level 2 Instruction Cache Size
bits : 24 - 31 (8 bit)
access : read-only
Processor 0 Configuration Register 2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TMUSZ : Tightly-coupled Memory Upper Size
bits : 8 - 15 (8 bit)
access : read-only
TMLSZ : Tightly-coupled Memory Lower Size
bits : 24 - 31 (8 bit)
access : read-only
Processor 0 Configuration Register 3
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FPU : Floating Point Unit
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
FPU support is not included.
#1 : 1
FPU support is included.
End of enumeration elements list.
SIMD : SIMD/NEON instruction support
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
SIMD/NEON support is not included.
#1 : 1
SIMD/NEON support is included.
End of enumeration elements list.
JAZ : Jazelle support
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Jazelle support is not included.
#1 : 1
Jazelle support is included.
End of enumeration elements list.
MMU : Memory Management Unit
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
MMU support is not included.
#1 : 1
MMU support is included.
End of enumeration elements list.
TZ : Trust Zone
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Trust Zone support is not included.
#1 : 1
Trust Zone support is included.
End of enumeration elements list.
CMP : Core Memory Protection unit
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Core Memory Protection is not included.
#1 : 1
Core Memory Protection is included.
End of enumeration elements list.
BB : Bit Banding
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Bit Banding is not supported.
#1 : 1
Bit Banding is supported.
End of enumeration elements list.
SBP : System Bus Ports
bits : 8 - 9 (2 bit)
access : read-only
Processor X Number Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPN : Processor x Number
bits : 0 - 0 (1 bit)
access : read-only
On-Chip Memory Descriptor Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCM1 : OCMEM Control Field 1
bits : 4 - 5 (2 bit)
access : read-write
OCMPU : OCMPU
bits : 12 - 12 (1 bit)
access : read-only
OCMT : OCMT
bits : 13 - 15 (3 bit)
access : read-only
Enumeration:
#100 : 100
OCMEMn is a Program Flash.
#101 : 101
OCMEMn is a Data Flash.
#110 : 110
OCMEMn is an EEE.
End of enumeration elements list.
RO : RO
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writes to the OCMDRn[11:0] are allowed
#1 : 1
Writes to the OCMDRn[11:0] are ignored
End of enumeration elements list.
OCMW : OCMW
bits : 17 - 19 (3 bit)
access : read-only
Enumeration:
#010 : 010
OCMEMn 32-bits wide
#011 : 011
OCMEMn 64-bits wide
#100 : 100
OCMEMn 128-bits wide
#101 : 101
OCMEMn 256-bits wide
End of enumeration elements list.
OCMSZ : OCMSZ
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
#0000 : 0000
no OCMEMn
#0001 : 0001
1KB OCMEMn
#0010 : 0010
2KB OCMEMn
#0011 : 0011
4KB OCMEMn
#0100 : 0100
8KB OCMEMn
#0101 : 0101
16KB OCMEMn
#0110 : 0110
32KB OCMEMn
#0111 : 0111
64KB OCMEMn
#1000 : 1000
128KB OCMEMn
#1001 : 1001
256KB OCMEMn
#1010 : 1010
512KB OCMEMn
#1011 : 1011
1MB OCMEMn
#1100 : 1100
2MB OCMEMn
#1101 : 1101
4MB OCMEMn
#1110 : 1110
8MB OCMEMn
#1111 : 1111
16MB OCMEMn
End of enumeration elements list.
OCMSZH : OCMSZH
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
#0 : 0
OCMEMn is a power-of-2 capacity.
#1 : 1
OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
End of enumeration elements list.
V : V
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
OCMEMn is not present.
#1 : 1
OCMEMn is present.
End of enumeration elements list.
On-Chip Memory Descriptor Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCM1 : OCMEM Control Field 1
bits : 4 - 5 (2 bit)
access : read-write
OCMPU : OCMPU
bits : 12 - 12 (1 bit)
access : read-only
OCMT : OCMT
bits : 13 - 15 (3 bit)
access : read-only
Enumeration:
#100 : 100
OCMEMn is a Program Flash.
#101 : 101
OCMEMn is a Data Flash.
#110 : 110
OCMEMn is an EEE.
End of enumeration elements list.
RO : RO
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writes to the OCMDRn[11:0] are allowed
#1 : 1
Writes to the OCMDRn[11:0] are ignored
End of enumeration elements list.
OCMW : OCMW
bits : 17 - 19 (3 bit)
access : read-only
Enumeration:
#010 : 010
OCMEMn 32-bits wide
#011 : 011
OCMEMn 64-bits wide
#100 : 100
OCMEMn 128-bits wide
#101 : 101
OCMEMn 256-bits wide
End of enumeration elements list.
OCMSZ : OCMSZ
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
#0000 : 0000
no OCMEMn
#0001 : 0001
1KB OCMEMn
#0010 : 0010
2KB OCMEMn
#0011 : 0011
4KB OCMEMn
#0100 : 0100
8KB OCMEMn
#0101 : 0101
16KB OCMEMn
#0110 : 0110
32KB OCMEMn
#0111 : 0111
64KB OCMEMn
#1000 : 1000
128KB OCMEMn
#1001 : 1001
256KB OCMEMn
#1010 : 1010
512KB OCMEMn
#1011 : 1011
1MB OCMEMn
#1100 : 1100
2MB OCMEMn
#1101 : 1101
4MB OCMEMn
#1110 : 1110
8MB OCMEMn
#1111 : 1111
16MB OCMEMn
End of enumeration elements list.
OCMSZH : OCMSZH
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
#0 : 0
OCMEMn is a power-of-2 capacity.
#1 : 1
OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
End of enumeration elements list.
V : V
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
OCMEMn is not present.
#1 : 1
OCMEMn is present.
End of enumeration elements list.
On-Chip Memory Descriptor Register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCMPU : OCMPU
bits : 12 - 12 (1 bit)
access : read-only
OCMT : OCMT
bits : 13 - 15 (3 bit)
access : read-only
Enumeration:
#100 : 100
OCMEMn is a Program Flash.
#101 : 101
OCMEMn is a Data Flash.
#110 : 110
OCMEMn is an EEE.
End of enumeration elements list.
RO : RO
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writes to the OCMDRn[11:0] are allowed
#1 : 1
Writes to the OCMDRn[11:0] are ignored
End of enumeration elements list.
OCMW : OCMW
bits : 17 - 19 (3 bit)
access : read-only
Enumeration:
#010 : 010
OCMEMn 32-bits wide
#011 : 011
OCMEMn 64-bits wide
#100 : 100
OCMEMn 128-bits wide
#101 : 101
OCMEMn 256-bits wide
End of enumeration elements list.
OCMSZ : OCMSZ
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
#0000 : 0000
no OCMEMn
#0001 : 0001
1KB OCMEMn
#0010 : 0010
2KB OCMEMn
#0011 : 0011
4KB OCMEMn
#0100 : 0100
8KB OCMEMn
#0101 : 0101
16KB OCMEMn
#0110 : 0110
32KB OCMEMn
#0111 : 0111
64KB OCMEMn
#1000 : 1000
128KB OCMEMn
#1001 : 1001
256KB OCMEMn
#1010 : 1010
512KB OCMEMn
#1011 : 1011
1MB OCMEMn
#1100 : 1100
2MB OCMEMn
#1101 : 1101
4MB OCMEMn
#1110 : 1110
8MB OCMEMn
#1111 : 1111
16MB OCMEMn
End of enumeration elements list.
OCMSZH : OCMSZH
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
#0 : 0
OCMEMn is a power-of-2 capacity.
#1 : 1
OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
End of enumeration elements list.
V : V
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
OCMEMn is not present.
#1 : 1
OCMEMn is present.
End of enumeration elements list.
Processor X Master Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PPMN : Processor x Physical Master Number
bits : 0 - 5 (6 bit)
access : read-only
Processor X Count Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PCNT : Processor Count
bits : 0 - 1 (2 bit)
access : read-only
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