Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x840 byte (0x0)
mem_usage : registers
protection :
Control/Error Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
MPU is disabled. All accesses from all bus masters are allowed.
#1 : 1
MPU is enabled
End of enumeration elements list.
NRGD : Number Of Region Descriptors
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
#0000 : 0000
8 region descriptors
#0001 : 0001
12 region descriptors
#0010 : 0010
16 region descriptors
End of enumeration elements list.
NSP : Number Of Slave Ports
bits : 12 - 15 (4 bit)
access : read-only
HRL : Hardware Revision Level
bits : 16 - 19 (4 bit)
access : read-only
SPERR4 : Slave Port 4 Error
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
No error has occurred for slave port 4.
#1 : 1
An error has occurred for slave port 4.
End of enumeration elements list.
SPERR3 : Slave Port 3 Error
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
No error has occurred for slave port 3.
#1 : 1
An error has occurred for slave port 3.
End of enumeration elements list.
SPERR2 : Slave Port 2 Error
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
No error has occurred for slave port 2.
#1 : 1
An error has occurred for slave port 2.
End of enumeration elements list.
SPERR1 : Slave Port 1 Error
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
No error has occurred for slave port 1.
#1 : 1
An error has occurred for slave port 1.
End of enumeration elements list.
SPERR0 : Slave Port 0 Error
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No error has occurred for slave port 0.
#1 : 1
An error has occurred for slave port 0.
End of enumeration elements list.
Error Address Register, slave port 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EADDR : Error Address
bits : 0 - 31 (32 bit)
access : read-only
Error Detail Register, slave port 0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ERW : Error Read/Write
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Read
#1 : 1
Write
End of enumeration elements list.
EATTR : Error Attributes
bits : 1 - 3 (3 bit)
access : read-only
Enumeration:
#000 : 000
User mode, instruction access
#001 : 001
User mode, data access
#010 : 010
Supervisor mode, instruction access
#011 : 011
Supervisor mode, data access
End of enumeration elements list.
EMN : Error Master Number
bits : 4 - 7 (4 bit)
access : read-only
EPID : Error Process Identification
bits : 8 - 15 (8 bit)
access : read-only
EACD : Error Access Control Detail
bits : 16 - 31 (16 bit)
access : read-only
Error Address Register, slave port 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EADDR : Error Address
bits : 0 - 31 (32 bit)
access : read-only
Error Detail Register, slave port 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ERW : Error Read/Write
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Read
#1 : 1
Write
End of enumeration elements list.
EATTR : Error Attributes
bits : 1 - 3 (3 bit)
access : read-only
Enumeration:
#000 : 000
User mode, instruction access
#001 : 001
User mode, data access
#010 : 010
Supervisor mode, instruction access
#011 : 011
Supervisor mode, data access
End of enumeration elements list.
EMN : Error Master Number
bits : 4 - 7 (4 bit)
access : read-only
EPID : Error Process Identification
bits : 8 - 15 (8 bit)
access : read-only
EACD : Error Access Control Detail
bits : 16 - 31 (16 bit)
access : read-only
Error Address Register, slave port 2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EADDR : Error Address
bits : 0 - 31 (32 bit)
access : read-only
Error Detail Register, slave port 2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ERW : Error Read/Write
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Read
#1 : 1
Write
End of enumeration elements list.
EATTR : Error Attributes
bits : 1 - 3 (3 bit)
access : read-only
Enumeration:
#000 : 000
User mode, instruction access
#001 : 001
User mode, data access
#010 : 010
Supervisor mode, instruction access
#011 : 011
Supervisor mode, data access
End of enumeration elements list.
EMN : Error Master Number
bits : 4 - 7 (4 bit)
access : read-only
EPID : Error Process Identification
bits : 8 - 15 (8 bit)
access : read-only
EACD : Error Access Control Detail
bits : 16 - 31 (16 bit)
access : read-only
Error Address Register, slave port 3
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EADDR : Error Address
bits : 0 - 31 (32 bit)
access : read-only
Error Detail Register, slave port 3
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ERW : Error Read/Write
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Read
#1 : 1
Write
End of enumeration elements list.
EATTR : Error Attributes
bits : 1 - 3 (3 bit)
access : read-only
Enumeration:
#000 : 000
User mode, instruction access
#001 : 001
User mode, data access
#010 : 010
Supervisor mode, instruction access
#011 : 011
Supervisor mode, data access
End of enumeration elements list.
EMN : Error Master Number
bits : 4 - 7 (4 bit)
access : read-only
EPID : Error Process Identification
bits : 8 - 15 (8 bit)
access : read-only
EACD : Error Access Control Detail
bits : 16 - 31 (16 bit)
access : read-only
Error Address Register, slave port 4
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EADDR : Error Address
bits : 0 - 31 (32 bit)
access : read-only
Error Detail Register, slave port 4
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ERW : Error Read/Write
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Read
#1 : 1
Write
End of enumeration elements list.
EATTR : Error Attributes
bits : 1 - 3 (3 bit)
access : read-only
Enumeration:
#000 : 000
User mode, instruction access
#001 : 001
User mode, data access
#010 : 010
Supervisor mode, instruction access
#011 : 011
Supervisor mode, data access
End of enumeration elements list.
EMN : Error Master Number
bits : 4 - 7 (4 bit)
access : read-only
EPID : Error Process Identification
bits : 8 - 15 (8 bit)
access : read-only
EACD : Error Access Control Detail
bits : 16 - 31 (16 bit)
access : read-only
Region Descriptor 0, Word 0
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 0, Word 1
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 0, Word 2
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor 0, Word 3
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Region descriptor is invalid
#1 : 1
Region descriptor is valid
End of enumeration elements list.
PIDMASK : Process Identifier Mask
bits : 16 - 23 (8 bit)
access : read-write
PID : Process Identifier
bits : 24 - 31 (8 bit)
access : read-write
Region Descriptor 1, Word 0
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 1, Word 1
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 1, Word 2
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor 1, Word 3
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Region descriptor is invalid
#1 : 1
Region descriptor is valid
End of enumeration elements list.
PIDMASK : Process Identifier Mask
bits : 16 - 23 (8 bit)
access : read-write
PID : Process Identifier
bits : 24 - 31 (8 bit)
access : read-write
Region Descriptor 2, Word 0
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 2, Word 1
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 2, Word 2
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor 2, Word 3
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Region descriptor is invalid
#1 : 1
Region descriptor is valid
End of enumeration elements list.
PIDMASK : Process Identifier Mask
bits : 16 - 23 (8 bit)
access : read-write
PID : Process Identifier
bits : 24 - 31 (8 bit)
access : read-write
Region Descriptor 3, Word 0
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 3, Word 1
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 3, Word 2
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor 3, Word 3
address_offset : 0x43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Region descriptor is invalid
#1 : 1
Region descriptor is valid
End of enumeration elements list.
PIDMASK : Process Identifier Mask
bits : 16 - 23 (8 bit)
access : read-write
PID : Process Identifier
bits : 24 - 31 (8 bit)
access : read-write
Region Descriptor 4, Word 0
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 4, Word 1
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 4, Word 2
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor 4, Word 3
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Region descriptor is invalid
#1 : 1
Region descriptor is valid
End of enumeration elements list.
PIDMASK : Process Identifier Mask
bits : 16 - 23 (8 bit)
access : read-write
PID : Process Identifier
bits : 24 - 31 (8 bit)
access : read-write
Region Descriptor 5, Word 0
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 5, Word 1
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 5, Word 2
address_offset : 0x458 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor 5, Word 3
address_offset : 0x45C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Region descriptor is invalid
#1 : 1
Region descriptor is valid
End of enumeration elements list.
PIDMASK : Process Identifier Mask
bits : 16 - 23 (8 bit)
access : read-write
PID : Process Identifier
bits : 24 - 31 (8 bit)
access : read-write
Region Descriptor 6, Word 0
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 6, Word 1
address_offset : 0x464 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 6, Word 2
address_offset : 0x468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor 6, Word 3
address_offset : 0x46C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Region descriptor is invalid
#1 : 1
Region descriptor is valid
End of enumeration elements list.
PIDMASK : Process Identifier Mask
bits : 16 - 23 (8 bit)
access : read-write
PID : Process Identifier
bits : 24 - 31 (8 bit)
access : read-write
Region Descriptor 7, Word 0
address_offset : 0x470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 7, Word 1
address_offset : 0x474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 7, Word 2
address_offset : 0x478 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor 7, Word 3
address_offset : 0x47C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Region descriptor is invalid
#1 : 1
Region descriptor is valid
End of enumeration elements list.
PIDMASK : Process Identifier Mask
bits : 16 - 23 (8 bit)
access : read-write
PID : Process Identifier
bits : 24 - 31 (8 bit)
access : read-write
Region Descriptor 8, Word 0
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 8, Word 1
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 8, Word 2
address_offset : 0x488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor 8, Word 3
address_offset : 0x48C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Region descriptor is invalid
#1 : 1
Region descriptor is valid
End of enumeration elements list.
PIDMASK : Process Identifier Mask
bits : 16 - 23 (8 bit)
access : read-write
PID : Process Identifier
bits : 24 - 31 (8 bit)
access : read-write
Region Descriptor 9, Word 0
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 9, Word 1
address_offset : 0x494 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 9, Word 2
address_offset : 0x498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor 9, Word 3
address_offset : 0x49C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Region descriptor is invalid
#1 : 1
Region descriptor is valid
End of enumeration elements list.
PIDMASK : Process Identifier Mask
bits : 16 - 23 (8 bit)
access : read-write
PID : Process Identifier
bits : 24 - 31 (8 bit)
access : read-write
Region Descriptor 10, Word 0
address_offset : 0x4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 10, Word 1
address_offset : 0x4A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 10, Word 2
address_offset : 0x4A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor 10, Word 3
address_offset : 0x4AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Region descriptor is invalid
#1 : 1
Region descriptor is valid
End of enumeration elements list.
PIDMASK : Process Identifier Mask
bits : 16 - 23 (8 bit)
access : read-write
PID : Process Identifier
bits : 24 - 31 (8 bit)
access : read-write
Region Descriptor 11, Word 0
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 11, Word 1
address_offset : 0x4B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 11, Word 2
address_offset : 0x4B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor 11, Word 3
address_offset : 0x4BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Region descriptor is invalid
#1 : 1
Region descriptor is valid
End of enumeration elements list.
PIDMASK : Process Identifier Mask
bits : 16 - 23 (8 bit)
access : read-write
PID : Process Identifier
bits : 24 - 31 (8 bit)
access : read-write
Region Descriptor 12, Word 0
address_offset : 0x4C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 12, Word 1
address_offset : 0x4C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 12, Word 2
address_offset : 0x4C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor 12, Word 3
address_offset : 0x4CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Region descriptor is invalid
#1 : 1
Region descriptor is valid
End of enumeration elements list.
PIDMASK : Process Identifier Mask
bits : 16 - 23 (8 bit)
access : read-write
PID : Process Identifier
bits : 24 - 31 (8 bit)
access : read-write
Region Descriptor 13, Word 0
address_offset : 0x4D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 13, Word 1
address_offset : 0x4D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 13, Word 2
address_offset : 0x4D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor 13, Word 3
address_offset : 0x4DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Region descriptor is invalid
#1 : 1
Region descriptor is valid
End of enumeration elements list.
PIDMASK : Process Identifier Mask
bits : 16 - 23 (8 bit)
access : read-write
PID : Process Identifier
bits : 24 - 31 (8 bit)
access : read-write
Region Descriptor 14, Word 0
address_offset : 0x4E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 14, Word 1
address_offset : 0x4E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 14, Word 2
address_offset : 0x4E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor 14, Word 3
address_offset : 0x4EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Region descriptor is invalid
#1 : 1
Region descriptor is valid
End of enumeration elements list.
PIDMASK : Process Identifier Mask
bits : 16 - 23 (8 bit)
access : read-write
PID : Process Identifier
bits : 24 - 31 (8 bit)
access : read-write
Region Descriptor 15, Word 0
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 15, Word 1
address_offset : 0x4F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write
Region Descriptor 15, Word 2
address_offset : 0x4F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor 15, Word 3
address_offset : 0x4FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Region descriptor is invalid
#1 : 1
Region descriptor is valid
End of enumeration elements list.
PIDMASK : Process Identifier Mask
bits : 16 - 23 (8 bit)
access : read-write
PID : Process Identifier
bits : 24 - 31 (8 bit)
access : read-write
Region Descriptor Alternate Access Control 0
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access Control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor Alternate Access Control 1
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access Control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor Alternate Access Control 2
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access Control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor Alternate Access Control 3
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access Control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor Alternate Access Control 4
address_offset : 0x810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access Control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor Alternate Access Control 5
address_offset : 0x814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access Control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor Alternate Access Control 6
address_offset : 0x818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access Control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor Alternate Access Control 7
address_offset : 0x81C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access Control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor Alternate Access Control 8
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access Control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor Alternate Access Control 9
address_offset : 0x824 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access Control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor Alternate Access Control 10
address_offset : 0x828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access Control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor Alternate Access Control 11
address_offset : 0x82C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access Control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor Alternate Access Control 12
address_offset : 0x830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access Control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor Alternate Access Control 13
address_offset : 0x834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access Control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor Alternate Access Control 14
address_offset : 0x838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access Control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
Region Descriptor Alternate Access Control 15
address_offset : 0x83C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write
M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M0UM
End of enumeration elements list.
M0PE : Bus Master 0 Process Identifier Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write
M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M1UM
End of enumeration elements list.
M1PE : Bus Master 1 Process Identifier Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the process identifier in the evaluation
#1 : 1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
End of enumeration elements list.
M2UM : Bus Master 2 User Mode Access Control
bits : 12 - 14 (3 bit)
access : read-write
M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M2UM
End of enumeration elements list.
M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write
M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
r/w/x read, write and execute allowed
#01 : 1
r/x read and execute allowed, but no write
#10 : 10
r/w read and write allowed, but no execute
#11 : 11
Same as User mode defined in M3UM
End of enumeration elements list.
M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 4 writes allowed
End of enumeration elements list.
M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 4 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 4 reads allowed
End of enumeration elements list.
M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 5 writes allowed
End of enumeration elements list.
M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 5 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 5 reads allowed
End of enumeration elements list.
M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 6 writes allowed
End of enumeration elements list.
M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 6 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 6 reads allowed
End of enumeration elements list.
M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 writes terminate with an access error and the write is not performed
#1 : 1
Bus master 7 writes allowed
End of enumeration elements list.
M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus master 7 reads terminate with an access error and the read is not performed
#1 : 1
Bus master 7 reads allowed
End of enumeration elements list.
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