Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x78 byte (0x0)
mem_usage : registers
protection :
Version ID Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FEATURE : Module Identification Number
bits : 0 - 15 (16 bit)
access : read-only
Enumeration:
#100 : 0000000000000100
Standard feature set supporting 32-bit shift register.
End of enumeration elements list.
MINOR : Minor Version Number
bits : 16 - 23 (8 bit)
access : read-only
MAJOR : Major Version Number
bits : 24 - 31 (8 bit)
access : read-only
Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEN : Module Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Module is disabled.
#1 : 1
Module is enabled.
End of enumeration elements list.
RST : Software Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Master logic is not reset.
#1 : 1
Master logic is reset.
End of enumeration elements list.
DOZEN : Doze mode enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Module is enabled in Doze mode.
#1 : 1
Module is disabled in Doze mode.
End of enumeration elements list.
DBGEN : Debug Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Module is disabled in debug mode.
#1 : 1
Module is enabled in debug mode.
End of enumeration elements list.
RTF : Reset Transmit FIFO
bits : 8 - 8 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Transmit FIFO is reset.
End of enumeration elements list.
RRF : Reset Receive FIFO
bits : 9 - 9 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Receive FIFO is reset.
End of enumeration elements list.
Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDF : Transmit Data Flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit data not requested.
#1 : 1
Transmit data is requested.
End of enumeration elements list.
RDF : Receive Data Flag
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive Data is not ready.
#1 : 1
Receive data is ready.
End of enumeration elements list.
WCF : Word Complete Flag
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transfer word not completed.
#1 : 1
Transfer word completed.
End of enumeration elements list.
FCF : Frame Complete Flag
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame transfer has not completed.
#1 : 1
Frame transfer has completed.
End of enumeration elements list.
TCF : Transfer Complete Flag
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
All transfers have not completed.
#1 : 1
All transfers have completed.
End of enumeration elements list.
TEF : Transmit Error Flag
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit FIFO underrun has not occurred.
#1 : 1
Transmit FIFO underrun has occurred
End of enumeration elements list.
REF : Receive Error Flag
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive FIFO has not overflowed.
#1 : 1
Receive FIFO has overflowed.
End of enumeration elements list.
DMF : Data Match Flag
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Have not received matching data.
#1 : 1
Have received matching data.
End of enumeration elements list.
MBF : Module Busy Flag
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
LPSPI is idle.
#1 : 1
LPSPI is busy.
End of enumeration elements list.
Interrupt Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDIE : Transmit Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt disabled.
#1 : 1
Interrupt enabled
End of enumeration elements list.
RDIE : Receive Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt disabled.
#1 : 1
Interrupt enabled.
End of enumeration elements list.
WCIE : Word Complete Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt disabled.
#1 : 1
Interrupt enabled.
End of enumeration elements list.
FCIE : Frame Complete Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt disabled.
#1 : 1
Interrupt enabled.
End of enumeration elements list.
TCIE : Transfer Complete Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt disabled.
#1 : 1
Interrupt enabled.
End of enumeration elements list.
TEIE : Transmit Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt disabled.
#1 : 1
Interrupt enabled.
End of enumeration elements list.
REIE : Receive Error Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt disabled.
#1 : 1
Interrupt enabled.
End of enumeration elements list.
DMIE : Data Match Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt disabled.
#1 : 1
Interrupt enabled.
End of enumeration elements list.
DMA Enable Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDDE : Transmit Data DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA request disabled.
#1 : 1
DMA request enabled
End of enumeration elements list.
RDDE : Receive Data DMA Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA request disabled.
#1 : 1
DMA request enabled.
End of enumeration elements list.
Configuration Register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HREN : Host Request Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Host request is disabled.
#1 : 1
Host request is enabled.
End of enumeration elements list.
HRPOL : Host Request Polarity
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Active low.
#1 : 1
Active high.
End of enumeration elements list.
HRSEL : Host Request Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Host request input is pin LPSPI_HREQ.
#1 : 1
Host request input is input trigger.
End of enumeration elements list.
CIRFIFO : Circular FIFO Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Circular FIFO is disabled.
#1 : 1
Circular FIFO is enabled.
End of enumeration elements list.
RDMO : Receive Data Match Only
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Received data is stored in the receive FIFO as normal.
#1 : 1
Received data is discarded unless the DMF is set.
End of enumeration elements list.
Configuration Register 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASTER : Master Mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave mode.
#1 : 1
Master mode.
End of enumeration elements list.
SAMPLE : Sample Point
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input data sampled on SCK edge.
#1 : 1
Input data sampled on delayed SCK edge.
End of enumeration elements list.
AUTOPCS : Automatic PCS
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Automatic PCS generation disabled.
#1 : 1
Automatic PCS generation enabled.
End of enumeration elements list.
NOSTALL : No Stall
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transfers will stall when transmit FIFO is empty or receive FIFO is full.
#1 : 1
Transfers will not stall, allowing transmit FIFO underrun or receive FIFO overrun to occur.
End of enumeration elements list.
PCSPOL : Peripheral Chip Select Polarity
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
The PCSx is active low.
#0001 : 0001
The PCSx is active high.
End of enumeration elements list.
MATCFG : Match Configuration
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 000
Match is disabled.
#010 : 010
010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1)
#011 : 011
011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1)
#100 : 100
100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)]
#101 : 101
101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)]
#110 : 110
110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)]
#111 : 111
111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)]
End of enumeration elements list.
PINCFG : Pin Configuration
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
SIN is used for input data and SOUT for output data.
#01 : 01
SIN is used for both input and output data.
#10 : 10
SOUT is used for both input and output data.
#11 : 11
SOUT is used for input data and SIN for output data.
End of enumeration elements list.
OUTCFG : Output Config
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output data retains last value when chip select is negated.
#1 : 1
Output data is tristated when chip select is negated.
End of enumeration elements list.
PCSCFG : Peripheral Chip Select Configuration
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
PCS[3:2] are enabled.
#1 : 1
PCS[3:2] are disabled.
End of enumeration elements list.
Data Match Register 0
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH0 : Match 0 Value
bits : 0 - 31 (32 bit)
access : read-write
Data Match Register 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH1 : Match 1 Value
bits : 0 - 31 (32 bit)
access : read-write
Parameter Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXFIFO : Transmit FIFO Size
bits : 0 - 7 (8 bit)
access : read-only
RXFIFO : Receive FIFO Size
bits : 8 - 15 (8 bit)
access : read-only
Clock Configuration Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCKDIV : SCK Divider
bits : 0 - 7 (8 bit)
access : read-write
DBT : Delay Between Transfers
bits : 8 - 15 (8 bit)
access : read-write
PCSSCK : PCS to SCK Delay
bits : 16 - 23 (8 bit)
access : read-write
SCKPCS : SCK to PCS Delay
bits : 24 - 31 (8 bit)
access : read-write
FIFO Control Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXWATER : Transmit FIFO Watermark
bits : 0 - 1 (2 bit)
access : read-write
RXWATER : Receive FIFO Watermark
bits : 16 - 17 (2 bit)
access : read-write
FIFO Status Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXCOUNT : Transmit FIFO Count
bits : 0 - 2 (3 bit)
access : read-only
RXCOUNT : Receive FIFO Count
bits : 16 - 18 (3 bit)
access : read-only
Transmit Command Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRAMESZ : Frame Size
bits : 0 - 11 (12 bit)
access : read-write
WIDTH : Transfer Width
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
Single bit transfer.
#01 : 01
Two bit transfer.
#10 : 10
Four bit transfer.
End of enumeration elements list.
TXMSK : Transmit Data Mask
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal transfer.
#1 : 1
Mask transmit data.
End of enumeration elements list.
RXMSK : Receive Data Mask
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal transfer.
#1 : 1
Receive data is masked.
End of enumeration elements list.
CONTC : Continuing Command
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Command word for start of new transfer.
#1 : 1
Command word for continuing transfer.
End of enumeration elements list.
CONT : Continuous Transfer
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Continuous transfer disabled.
#1 : 1
Continuous transfer enabled.
End of enumeration elements list.
BYSW : Byte Swap
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Byte swap disabled.
#1 : 1
Byte swap enabled.
End of enumeration elements list.
LSBF : LSB First
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data is transferred MSB first.
#1 : 1
Data is transferred LSB first.
End of enumeration elements list.
PCS : Peripheral Chip Select
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
Transfer using LPSPI_PCS[0]
#01 : 01
Transfer using LPSPI_PCS[1]
#10 : 10
Transfer using LPSPI_PCS[2]
#11 : 11
Transfer using LPSPI_PCS[3]
End of enumeration elements list.
PRESCALE : Prescaler Value
bits : 27 - 29 (3 bit)
access : read-write
Enumeration:
#000 : 000
Divide by 1.
#001 : 001
Divide by 2.
#010 : 010
Divide by 4.
#011 : 011
Divide by 8.
#100 : 100
Divide by 16.
#101 : 101
Divide by 32.
#110 : 110
Divide by 64.
#111 : 111
Divide by 128.
End of enumeration elements list.
CPHA : Clock Phase
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data is captured on the leading edge of SCK and changed on the following edge.
#1 : 1
Data is changed on the leading edge of SCK and captured on the following edge.
End of enumeration elements list.
CPOL : Clock Polarity
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The inactive state value of SCK is low.
#1 : 1
The inactive state value of SCK is high.
End of enumeration elements list.
Transmit Data Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Transmit Data
bits : 0 - 31 (32 bit)
access : write-only
Receive Status Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SOF : Start Of Frame
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Subsequent data word received after LPSPI_PCS assertion.
#1 : 1
First data word received after LPSPI_PCS assertion.
End of enumeration elements list.
RXEMPTY : RX FIFO Empty
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
RX FIFO is not empty.
#1 : 1
RX FIFO is empty.
End of enumeration elements list.
Receive Data Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Receive Data
bits : 0 - 31 (32 bit)
access : read-only
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