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SIM

Peripheral Memory Blocks

address_offset : 0x4 Bytes (0x0)
size : 0x6C byte (0x0)
mem_usage : registers
protection :

Registers

LPOCLKS

ADCOPT

FTMOPT1

MISCTRL0

SDID

CHIPCTL

PLATCGC

FCFG1

UIDH

UIDMH

UIDML

UIDL

CLKDIV4

MISCTRL1

FTMOPT0


LPOCLKS

LPO Clock Select Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPOCLKS LPOCLKS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPO1KCLKEN LPO32KCLKEN LPOCLKSEL RTCCLKSEL

LPO1KCLKEN : 1 kHz LPO_CLK enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable 1 kHz LPO_CLK output

#1 : 1

Enable 1 kHz LPO_CLK output

End of enumeration elements list.

LPO32KCLKEN : 32 kHz LPO_CLK enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable 32 kHz LPO_CLK output

#1 : 1

Enable 32 kHz LPO_CLK output

End of enumeration elements list.

LPOCLKSEL : LPO clock source select
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 00

128 kHz LPO_CLK

#01 : 01

No clock

#10 : 10

32 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK

#11 : 11

1 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK

End of enumeration elements list.

RTCCLKSEL : 32 kHz clock source select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 00

SOSCDIV1_CLK

#01 : 01

32 kHz LPO_CLK

#10 : 10

RTC_CLKIN clock

#11 : 11

FIRCDIV1_CLK

End of enumeration elements list.


ADCOPT

ADC Options Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCOPT ADCOPT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC0TRGSEL ADC0SWPRETRG ADC0PRETRGSEL ADC1TRGSEL ADC1SWPRETRG ADC1PRETRGSEL

ADC0TRGSEL : ADC0 trigger source select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

PDB output

#1 : 1

TRGMUX output

End of enumeration elements list.

ADC0SWPRETRG : ADC0 software pretrigger sources
bits : 1 - 3 (3 bit)
access : read-write

Enumeration:

#000 : 000

Software pretrigger disabled

#001 : 001

Reserved (do not use)

#010 : 010

Reserved (do not use)

#011 : 011

Reserved (do not use)

#100 : 100

Software pretrigger 0

#101 : 101

Software pretrigger 1

#110 : 110

Software pretrigger 2

#111 : 111

Software pretrigger 3

End of enumeration elements list.

ADC0PRETRGSEL : ADC0 pretrigger source select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 00

PDB pretrigger (default)

#01 : 01

TRGMUX pretrigger

#10 : 10

Software pretrigger

End of enumeration elements list.

ADC1TRGSEL : ADC1 trigger source select
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

PDB output

#1 : 1

TRGMUX output

End of enumeration elements list.

ADC1SWPRETRG : ADC1 software pretrigger sources
bits : 9 - 11 (3 bit)
access : read-write

Enumeration:

#000 : 000

Software pretrigger disabled

#001 : 001

Reserved (do not use)

#010 : 010

Reserved (do not use)

#011 : 011

Reserved (do not use)

#100 : 100

Software pretrigger 0

#101 : 101

Software pretrigger 1

#110 : 110

Software pretrigger 2

#111 : 111

Software pretrigger 3

End of enumeration elements list.

ADC1PRETRGSEL : ADC1 pretrigger source select
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 00

PDB pretrigger (default)

#01 : 01

TRGMUX pretrigger

#10 : 10

Software pretrigger

End of enumeration elements list.


FTMOPT1

FTM Option Register 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FTMOPT1 FTMOPT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTM0SYNCBIT FTM1SYNCBIT FTM2SYNCBIT FTM3SYNCBIT FTM1CH0SEL FTM2CH0SEL FTM2CH1SEL FTMGLDOK FTM0_OUTSEL FTM3_OUTSEL

FTM0SYNCBIT : FTM0 Sync Bit
bits : 0 - 0 (1 bit)
access : read-write

FTM1SYNCBIT : FTM1 Sync Bit
bits : 1 - 1 (1 bit)
access : read-write

FTM2SYNCBIT : FTM2 Sync Bit
bits : 2 - 2 (1 bit)
access : read-write

FTM3SYNCBIT : FTM3 Sync Bit
bits : 3 - 3 (1 bit)
access : read-write

FTM1CH0SEL : FTM1 CH0 Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 00

FTM1_CH0 input

#01 : 01

CMP0 output

End of enumeration elements list.

FTM2CH0SEL : FTM2 CH0 Select
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 00

FTM2_CH0 input

#01 : 01

CMP0 output

End of enumeration elements list.

FTM2CH1SEL : FTM2 CH1 Select
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

FTM2_CH1 input

#1 : 1

exclusive OR of FTM2_CH0,FTM2_CH1,and FTM1_CH1

End of enumeration elements list.

FTMGLDOK : FTM global load enable
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

FTM Global load mechanism disabled.

#1 : 1

FTM Global load mechanism enabled

End of enumeration elements list.

FTM0_OUTSEL : FTM0 channel modulation select with FTM1_CH1
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

#0 : 00000000

No modulation with FTM1_CH1

#1 : 00000001

Modulation with FTM1_CH1

End of enumeration elements list.

FTM3_OUTSEL : FTM3 channel modulation select with FTM2_CH1
bits : 24 - 31 (8 bit)
access : read-write

Enumeration:

#0 : 00000000

No modulation with FTM2_CH1

#1 : 00000001

Modulation with FTM2_CH1

End of enumeration elements list.


MISCTRL0

Miscellaneous control register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MISCTRL0 MISCTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STOP1_MONITOR STOP2_MONITOR FTM0_OBE_CTRL FTM1_OBE_CTRL FTM2_OBE_CTRL FTM3_OBE_CTRL

STOP1_MONITOR : STOP1 monitor bit
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus clock enabled or STOP1 entry aborted

#1 : 1

STOP1 entry successful

End of enumeration elements list.

STOP2_MONITOR : STOP2 monitor bit
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

System clock enabled or STOP2 entry aborted

#1 : 1

STOP2 entry successful

End of enumeration elements list.

FTM0_OBE_CTRL : FTM0 OBE CTRL bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated.

#1 : 1

The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1].

End of enumeration elements list.

FTM1_OBE_CTRL : FTM1 OBE CTRL bit
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated.

#1 : 1

The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1].

End of enumeration elements list.

FTM2_OBE_CTRL : FTM2 OBE CTRL bit
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated.

#1 : 1

The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1].

End of enumeration elements list.

FTM3_OBE_CTRL : FTM3 OBE CTRL bit
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated.

#1 : 1

The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1].

End of enumeration elements list.


SDID

System Device Identification Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SDID SDID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FEATURES PACKAGE REVID RAMSIZE DERIVATE SUBSERIES GENERATION

FEATURES : Features
bits : 0 - 7 (8 bit)
access : read-only

PACKAGE : Package
bits : 8 - 11 (4 bit)
access : read-only

Enumeration:

#0010 : 0010

48 LQFP

#0011 : 0011

64 LQFP

#0100 : 0100

100 LQFP

#0110 : 0110

144 LQFP

#0111 : 0111

176 LQFP

#1000 : 1000

100 MAP BGA

End of enumeration elements list.

REVID : Device revision number
bits : 12 - 15 (4 bit)
access : read-only

RAMSIZE : RAM size
bits : 16 - 19 (4 bit)
access : read-only

Enumeration:

#1011 : 1011

192 KB (S32K148), 96 KB (S32K146), Reserved (others)

#1101 : 1101

48 KB (S32K144), Reserved (others)

#1111 : 1111

256 KB (S32K148), 128 KB (S32K146), 64 KB (S32K144), 32 KB (S32K142), 25 KB (S32K118), 17 KB (S32K116)

End of enumeration elements list.

DERIVATE : Derivate
bits : 20 - 23 (4 bit)
access : read-only

SUBSERIES : Subseries
bits : 24 - 27 (4 bit)
access : read-only

GENERATION : S32K product series generation
bits : 28 - 31 (4 bit)
access : read-only


CHIPCTL

Chip Control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIPCTL CHIPCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_INTERLEAVE_EN CLKOUTSEL CLKOUTDIV CLKOUTEN PDB_BB_SEL ADC_SUPPLY ADC_SUPPLYEN SRAMU_RETEN SRAML_RETEN

ADC_INTERLEAVE_EN : ADC interleave channel enable
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interleaving disabled. No channel pair interleaved. Interleaved channels are individually connected to pins. PTC0 is connected to ADC0_SE8. PTC1 is connected to ADC0_SE9. PTB15 is connected to ADC1_SE14. PTB16 is connected to ADC1_SE15. PTB0 is connected to ADC0_SE4. PTB1 is connected to ADC0_SE5. PTB13 is connected to ADC1_SE8. PTB14 is connected to ADC1_SE9.

#1xxx : 1xxx

PTB14 to ADC1_SE9 and ADC0_SE9

#x1xx : x1xx

PTB13 to ADC1_SE8 and ADC0_SE8

#xx1x : xx1x

PTB1 to ADC0_SE5 and ADC1_SE15

#xxx1 : xxx1

PTB0 to ADC0_SE4 and ADC1_SE14

End of enumeration elements list.

CLKOUTSEL : CLKOUT Select
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

SCG CLKOUT

#0010 : 0010

SOSC DIV2 CLK

#0100 : 0100

SIRC DIV2 CLK

#0101 : 0101

For S32K148: QSPI SFIF_CLK_HYP: Divide by 2 clock (configured through SCLKCONFIG[5]) for HyperRAM going to sfif clock to QSPI For others: Reserved

#0110 : 0110

FIRC DIV2 CLK

#0111 : 0111

HCLK

#1000 : 1000

SPLL DIV2 CLK

#1001 : 1001

BUS_CLK

#1010 : 1010

LPO128K_CLK

#1011 : 1011

For S32K148: QSPI IPG_CLK For others: Reserved

#1100 : 1100

LPO_CLK as selected by SIM_LPOCLKS[LPOCLKSEL]

#1101 : 1101

For S32K148: QSPI IPG_CLK_SFIF For others: Reserved

#1110 : 1110

RTC_CLK as selected by SIM_LPOCLKS[RTCCLKSEL]

#1111 : 1111

For S32K148: QSPI IPG_CLK_2XSFIF For others: Reserved

End of enumeration elements list.

CLKOUTDIV : CLKOUT Divide Ratio
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Divide by 1

#001 : 001

Divide by 2

#010 : 010

Divide by 3

#011 : 011

Divide by 4

#100 : 100

Divide by 5

#101 : 101

Divide by 6

#110 : 110

Divide by 7

#111 : 111

Divide by 8

End of enumeration elements list.

CLKOUTEN : CLKOUT enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clockout disable

#1 : 1

Clockout enable

End of enumeration elements list.

PDB_BB_SEL : PDB back-to-back select
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

PDB0 channel 0 back-to-back operation with ADC0 COCO[7:0] and PDB1 channel 0 back-to-back operation with ADC1 COCO[7:0]

#1 : 1

Channel 0 of PDB0 and PDB1 back-to-back operation with COCO[7:0] of ADC0 and ADC1.

End of enumeration elements list.

ADC_SUPPLY : ADC_SUPPLY
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#000 : 000

5 V input VDD supply (VDD)

#001 : 001

5 V input analog supply (VDDA)

#010 : 010

ADC Reference Supply (VREFH)

#011 : 011

3.3 V Oscillator Regulator Output (VDD_3V)

#100 : 100

3.3 V flash regulator output (VDD_flash_3V)

#101 : 101

1.2 V core regulator output (VDD_LV)

End of enumeration elements list.

ADC_SUPPLYEN : ADC_SUPPLYEN
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable internal supply monitoring

#1 : 1

Enable internal supply monitoring

End of enumeration elements list.

SRAMU_RETEN : SRAMU_RETEN
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

SRAMU contents are retained across resets

#1 : 1

No SRAMU retention

End of enumeration elements list.

SRAML_RETEN : SRAML_RETEN
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

SRAML contents are retained across resets

#1 : 1

No SRAML retention

End of enumeration elements list.


PLATCGC

Platform Clock Gating Control Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLATCGC PLATCGC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CGCMSCM CGCMPU CGCDMA CGCERM CGCEIM CGCGPIO

CGCMSCM : MSCM Clock Gating Control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock disabled

#1 : 1

Clock enabled

End of enumeration elements list.

CGCMPU : MPU Clock Gating Control
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock disabled

#1 : 1

Clock enabled

End of enumeration elements list.

CGCDMA : DMA Clock Gating Control
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock disabled

#1 : 1

Clock enabled

End of enumeration elements list.

CGCERM : ERM Clock Gating Control
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock disabled

#1 : 1

Clock enabled

End of enumeration elements list.

CGCEIM : EIM Clock Gating Control
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock disabled

#1 : 1

Clock enabled

End of enumeration elements list.

CGCGPIO : GPIO Clock Gating Control
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock disabled

#1 : 1

Clock enabled

End of enumeration elements list.


FCFG1

Flash Configuration Register 1
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCFG1 FCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEPART EEERAMSIZE

DEPART : FlexNVM partition
bits : 12 - 15 (4 bit)
access : read-only

EEERAMSIZE : EEE SRAM SIZE
bits : 16 - 19 (4 bit)
access : read-only

Enumeration:

#0010 : 0010

4 KB

#0011 : 0011

2 KB

#0100 : 0100

1 KB

#0101 : 0101

512 Bytes

#0110 : 0110

256 Bytes

#0111 : 0111

128 Bytes

#1000 : 1000

64 Bytes

#1001 : 1001

32 Bytes

#1111 : 1111

0 Bytes

End of enumeration elements list.


UIDH

Unique Identification Register High
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UIDH UIDH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UID127_96

UID127_96 : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only


UIDMH

Unique Identification Register Mid-High
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UIDMH UIDMH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UID95_64

UID95_64 : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only


UIDML

Unique Identification Register Mid Low
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UIDML UIDML read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UID63_32

UID63_32 : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only


UIDL

Unique Identification Register Low
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UIDL UIDL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UID31_0

UID31_0 : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only


CLKDIV4

System Clock Divider Register 4
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKDIV4 CLKDIV4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRACEFRAC TRACEDIV TRACEDIVEN

TRACEFRAC : Trace Clock Divider fraction To configure TRACEDIV and TRACEFRAC, you must first clear TRACEDIVEN to disable the trace clock divide function.
bits : 0 - 0 (1 bit)
access : read-write

TRACEDIV : Trace Clock Divider value To configure TRACEDIV, you must first disable TRACEDIVEN, then enable it after setting TRACEDIV.
bits : 1 - 3 (3 bit)
access : read-write

TRACEDIVEN : Debug Trace Divider control
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Debug trace divider disabled

#1 : 1

Debug trace divider enabled

End of enumeration elements list.


MISCTRL1

Miscellaneous Control register 1
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MISCTRL1 MISCTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW_TRG

SW_TRG : Software trigger to TRGMUX. Writing to this bit generates software trigger to peripherals through TRGMUX (Refer to Figure: Trigger interconnectivity).
bits : 0 - 0 (1 bit)
access : read-write


FTMOPT0

FTM Option Register 0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FTMOPT0 FTMOPT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTM0FLTxSEL FTM1FLTxSEL FTM2FLTxSEL FTM3FLTxSEL FTM0CLKSEL FTM1CLKSEL FTM2CLKSEL FTM3CLKSEL

FTM0FLTxSEL : FTM0 Fault X Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 000

FTM0_FLTx pin

#001 : 001

TRGMUX_FTM0 out

End of enumeration elements list.

FTM1FLTxSEL : FTM1 Fault X Select
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

#000 : 000

FTM1_FLTx pin

#001 : 001

TRGMUX_FTM1 out

End of enumeration elements list.

FTM2FLTxSEL : FTM2 Fault X Select
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

FTM2_FLTx pin

#001 : 001

TRGMUX_FTM2 out

End of enumeration elements list.

FTM3FLTxSEL : FTM3 Fault X Select
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 000

FTM3_FLTx pin

#001 : 001

TRGMUX_FTM3 out

End of enumeration elements list.

FTM0CLKSEL : FTM0 External Clock Pin Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 00

FTM0 external clock driven by TCLK0 pin.

#01 : 01

FTM0 external clock driven by TCLK1 pin.

#10 : 10

FTM0 external clock driven by TCLK2 pin.

#11 : 11

No clock input

End of enumeration elements list.

FTM1CLKSEL : FTM1 External Clock Pin Select
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

#00 : 00

FTM1 external clock driven by TCLK0 pin.

#01 : 01

FTM1 external clock driven by TCLK1 pin.

#10 : 10

FTM1 external clock driven by TCLK2 pin.

#11 : 11

No clock input

End of enumeration elements list.

FTM2CLKSEL : FTM2 External Clock Pin Select
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

#00 : 00

FTM2 external clock driven by TCLK0 pin.

#01 : 01

FTM2 external clock driven by TCLK1 pin.

#10 : 10

FTM2 external clock driven by TCLK2 pin.

#11 : 11

No clock input

End of enumeration elements list.

FTM3CLKSEL : FTM3 External Clock Pin Select
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

#00 : 00

FTM3 external clock driven by TCLK0 pin.

#01 : 01

FTM3 external clock driven by TCLK1 pin.

#10 : 10

FTM3 external clock driven by TCLK2 pin.

#11 : 11

No clock input

End of enumeration elements list.



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