\n
address_offset : 0x0 Bytes (0x0)
size : 0x68 byte (0x0)
mem_usage : registers
protection :
TRGMUX DMAMUX0 Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write
SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write
SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Register can be written.
#1 : 1
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX CMP0 Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Register can be written.
#1 : 1
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX FTM0 Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write
SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write
SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Register can be written.
#1 : 1
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX FTM1 Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write
SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write
SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Register can be written.
#1 : 1
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX PDB0 Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Register can be written.
#1 : 1
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX EXTOUT0 Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write
SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write
SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Register can be written.
#1 : 1
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX FLEXIO Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write
SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write
SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Register can be written.
#1 : 1
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX LPIT0 Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write
SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write
SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Register can be written.
#1 : 1
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX LPUART0 Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Register can be written.
#1 : 1
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX LPUART1 Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Register can be written.
#1 : 1
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX LPI2C0 Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Register can be written.
#1 : 1
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX LPSPI0 Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Register can be written.
#1 : 1
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX LPTMR0 Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Register can be written.
#1 : 1
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX EXTOUT1 Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write
SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write
SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Register can be written.
#1 : 1
Register cannot be written until the next system Reset.
End of enumeration elements list.
TRGMUX ADC0 Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write
SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write
SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write
SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write
LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Register can be written.
#1 : 1
Register cannot be written until the next system Reset.
End of enumeration elements list.
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