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MTB_DWT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

CTRL

COMP0

TBCTRL

MASK0

FCT0

COMP1

MASK1

FCT1

DEVICECFG

DEVICETYPID

PERIPHID4

PERIPHID5

PERIPHID6

PERIPHID7

PERIPHID0

PERIPHID1

PERIPHID2

PERIPHID3

COMPID0

COMPID1

COMPID2

COMPID3


CTRL

MTB DWT Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DWTCFGCTRL NUMCMP

DWTCFGCTRL : DWT configuration controls
bits : 0 - 27 (28 bit)
access : read-only

NUMCMP : Number of comparators
bits : 28 - 31 (4 bit)
access : read-only


COMP0

MTB_DWT Comparator Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP0 COMP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP

COMP : Reference value for comparison
bits : 0 - 31 (32 bit)
access : read-write


TBCTRL

MTB_DWT Trace Buffer Control Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TBCTRL TBCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACOMP0 ACOMP1 NUMCOMP

ACOMP0 : Action based on Comparator 0 match
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED].

#1 : 1

Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED].

End of enumeration elements list.

ACOMP1 : Action based on Comparator 1 match
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED].

#1 : 1

Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED].

End of enumeration elements list.

NUMCOMP : Number of Comparators
bits : 28 - 31 (4 bit)
access : read-only


MASK0

MTB_DWT Comparator Mask Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MASK0 MASK0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK

MASK : MASK
bits : 0 - 4 (5 bit)
access : read-write


FCT0

MTB_DWT Comparator Function Register 0
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCT0 FCT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FUNCTION DATAVMATCH DATAVSIZE DATAVADDR0 MATCHED

FUNCTION : Function
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Disabled.

#0100 : 0100

Instruction fetch.

#0101 : 0101

Data operand read.

#0110 : 0110

Data operand write.

#0111 : 0111

Data operand (read + write).

End of enumeration elements list.

DATAVMATCH : Data Value Match
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Perform address comparison.

#1 : 1

Perform data value comparison.

End of enumeration elements list.

DATAVSIZE : Data Value Size
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#00 : 00

Byte.

#01 : 01

Halfword.

#10 : 10

Word.

#11 : 11

Reserved. Any attempts to use this value results in UNPREDICTABLE behavior.

End of enumeration elements list.

DATAVADDR0 : Data Value Address 0
bits : 12 - 15 (4 bit)
access : read-write

MATCHED : Comparator match
bits : 24 - 24 (1 bit)
access : read-only

Enumeration:

#0 : 0

No match.

#1 : 1

Match occurred.

End of enumeration elements list.


COMP1

MTB_DWT Comparator Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP1 COMP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP

COMP : Reference value for comparison
bits : 0 - 31 (32 bit)
access : read-write


MASK1

MTB_DWT Comparator Mask Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MASK1 MASK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK

MASK : MASK
bits : 0 - 4 (5 bit)
access : read-write


FCT1

MTB_DWT Comparator Function Register 1
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCT1 FCT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FUNCTION MATCHED

FUNCTION : Function
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Disabled.

#0100 : 0100

Instruction fetch.

#0101 : 0101

Data operand read.

#0110 : 0110

Data operand write.

#0111 : 0111

Data operand (read + write).

End of enumeration elements list.

MATCHED : Comparator match
bits : 24 - 24 (1 bit)
access : read-only

Enumeration:

#0 : 0

No match.

#1 : 1

Match occurred.

End of enumeration elements list.


DEVICECFG

Device Configuration Register
address_offset : 0xFC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVICECFG DEVICECFG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEVICECFG

DEVICECFG : DEVICECFG
bits : 0 - 31 (32 bit)
access : read-only


DEVICETYPID

Device Type Identifier Register
address_offset : 0xFCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVICETYPID DEVICETYPID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEVICETYPID

DEVICETYPID : DEVICETYPID
bits : 0 - 31 (32 bit)
access : read-only


PERIPHID4

Peripheral ID Register
address_offset : 0xFD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PERIPHID4 PERIPHID4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIPHID

PERIPHID : PERIPHID
bits : 0 - 31 (32 bit)
access : read-only


PERIPHID5

Peripheral ID Register
address_offset : 0xFD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PERIPHID5 PERIPHID5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIPHID

PERIPHID : PERIPHID
bits : 0 - 31 (32 bit)
access : read-only


PERIPHID6

Peripheral ID Register
address_offset : 0xFD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PERIPHID6 PERIPHID6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIPHID

PERIPHID : PERIPHID
bits : 0 - 31 (32 bit)
access : read-only


PERIPHID7

Peripheral ID Register
address_offset : 0xFDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PERIPHID7 PERIPHID7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIPHID

PERIPHID : PERIPHID
bits : 0 - 31 (32 bit)
access : read-only


PERIPHID0

Peripheral ID Register
address_offset : 0xFE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PERIPHID0 PERIPHID0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIPHID

PERIPHID : PERIPHID
bits : 0 - 31 (32 bit)
access : read-only


PERIPHID1

Peripheral ID Register
address_offset : 0xFE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PERIPHID1 PERIPHID1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIPHID

PERIPHID : PERIPHID
bits : 0 - 31 (32 bit)
access : read-only


PERIPHID2

Peripheral ID Register
address_offset : 0xFE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PERIPHID2 PERIPHID2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIPHID

PERIPHID : PERIPHID
bits : 0 - 31 (32 bit)
access : read-only


PERIPHID3

Peripheral ID Register
address_offset : 0xFEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PERIPHID3 PERIPHID3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIPHID

PERIPHID : PERIPHID
bits : 0 - 31 (32 bit)
access : read-only


COMPID0

Component ID Register
address_offset : 0xFF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

COMPID0 COMPID0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPID

COMPID : Component ID
bits : 0 - 31 (32 bit)
access : read-only


COMPID1

Component ID Register
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

COMPID1 COMPID1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPID

COMPID : Component ID
bits : 0 - 31 (32 bit)
access : read-only


COMPID2

Component ID Register
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

COMPID2 COMPID2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPID

COMPID : Component ID
bits : 0 - 31 (32 bit)
access : read-only


COMPID3

Component ID Register
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

COMPID3 COMPID3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPID

COMPID : Component ID
bits : 0 - 31 (32 bit)
access : read-only



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