Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x224 byte (0x0)
mem_usage : registers
protection :
Status And Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Prescale Factor Selection
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 000
Divide by 1
#001 : 001
Divide by 2
#010 : 010
Divide by 4
#011 : 011
Divide by 8
#100 : 100
Divide by 16
#101 : 101
Divide by 32
#110 : 110
Divide by 64
#111 : 111
Divide by 128
End of enumeration elements list.
CLKS : Clock Source Selection
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 00
No clock selected. This in effect disables the FTM counter.
#01 : 01
FTM input clock
#10 : 10
Fixed frequency clock
#11 : 11
External clock
End of enumeration elements list.
CPWMS : Center-Aligned PWM Select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM counter operates in Up Counting mode.
#1 : 1
FTM counter operates in Up-Down Counting mode.
End of enumeration elements list.
RIE : Reload Point Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reload point interrupt is disabled.
#1 : 1
Reload point interrupt is enabled.
End of enumeration elements list.
RF : Reload Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
A selected reload point did not happen.
#1 : 1
A selected reload point happened.
End of enumeration elements list.
TOIE : Timer Overflow Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable TOF interrupts. Use software polling.
#1 : 1
Enable TOF interrupts. An interrupt is generated when TOF equals one.
End of enumeration elements list.
TOF : Timer Overflow Flag
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
FTM counter has not overflowed.
#1 : 1
FTM counter has overflowed.
End of enumeration elements list.
PWMEN0 : Channel 0 PWM enable bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output port is disabled
#1 : 1
Channel output port is enabled
End of enumeration elements list.
PWMEN1 : Channel 1 PWM enable bit
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output port is disabled
#1 : 1
Channel output port is enabled
End of enumeration elements list.
PWMEN2 : Channel 2 PWM enable bit
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output port is disabled
#1 : 1
Channel output port is enabled
End of enumeration elements list.
PWMEN3 : Channel 3 PWM enable bit
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output port is disabled
#1 : 1
Channel output port is enabled
End of enumeration elements list.
PWMEN4 : Channel 4 PWM enable bit
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output port is disabled
#1 : 1
Channel output port is enabled
End of enumeration elements list.
PWMEN5 : Channel 5 PWM enable bit
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output port is disabled
#1 : 1
Channel output port is enabled
End of enumeration elements list.
PWMEN6 : Channel 6 PWM enable bit
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output port is disabled
#1 : 1
Channel output port is enabled
End of enumeration elements list.
PWMEN7 : Channel 7 PWM enable bit
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output port is disabled
#1 : 1
Channel output port is enabled
End of enumeration elements list.
FLTPS : Filter Prescaler
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide by 1
#0001 : 0001
Divide by 2
#0010 : 0010
Divide by 3
#0011 : 0011
Divide by 4
#0100 : 0100
Divide by 5
#0101 : 0101
Divide by 6
#0110 : 0110
Divide by 7
#0111 : 0111
Divide by 8
#1000 : 1000
Divide by 9
#1001 : 1001
Divide by 10
#1010 : 1010
Divide by 11
#1011 : 1011
Divide by 12
#1100 : 1100
Divide by 13
#1101 : 1101
Divide by 14
#1110 : 1110
Divide by 15
#1111 : 1111
Divide by 16
End of enumeration elements list.
Channel (n) Value
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write
Channel (n) Status And Control
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA : DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable DMA transfers.
#1 : 1
Enable DMA transfers.
End of enumeration elements list.
ICRST : FTM counter reset by the selected input capture event.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM counter is not reset when the selected channel (n) input event is detected.
#1 : 1
FTM counter is reset when the selected channel (n) input event is detected.
End of enumeration elements list.
ELSA : Channel (n) Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write
ELSB : Channel (n) Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write
MSA : Channel (n) Mode Select
bits : 4 - 4 (1 bit)
access : read-write
MSB : Channel (n) Mode Select
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel (n) Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel (n) interrupt. Use software polling.
#1 : 1
Enable channel (n) interrupt.
End of enumeration elements list.
CHF : Channel (n) Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
No channel (n) event has occurred.
#1 : 1
A channel (n) event has occurred.
End of enumeration elements list.
TRIGMODE : Trigger mode control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel outputs will generate the normal PWM outputs without generating a pulse.
#1 : 1
If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.
End of enumeration elements list.
CHIS : Channel (n) Input State
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
The channel (n) input is zero.
#1 : 1
The channel (n) input is one.
End of enumeration elements list.
CHOV : Channel (n) Output Value
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
The channel (n) output is zero.
#1 : 1
The channel (n) output is one.
End of enumeration elements list.
Channel (n) Value
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write
Channel (n) Status And Control
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA : DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable DMA transfers.
#1 : 1
Enable DMA transfers.
End of enumeration elements list.
ICRST : FTM counter reset by the selected input capture event.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM counter is not reset when the selected channel (n) input event is detected.
#1 : 1
FTM counter is reset when the selected channel (n) input event is detected.
End of enumeration elements list.
ELSA : Channel (n) Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write
ELSB : Channel (n) Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write
MSA : Channel (n) Mode Select
bits : 4 - 4 (1 bit)
access : read-write
MSB : Channel (n) Mode Select
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel (n) Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel (n) interrupt. Use software polling.
#1 : 1
Enable channel (n) interrupt.
End of enumeration elements list.
CHF : Channel (n) Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
No channel (n) event has occurred.
#1 : 1
A channel (n) event has occurred.
End of enumeration elements list.
TRIGMODE : Trigger mode control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel outputs will generate the normal PWM outputs without generating a pulse.
#1 : 1
If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.
End of enumeration elements list.
CHIS : Channel (n) Input State
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
The channel (n) input is zero.
#1 : 1
The channel (n) input is one.
End of enumeration elements list.
CHOV : Channel (n) Output Value
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
The channel (n) output is zero.
#1 : 1
The channel (n) output is one.
End of enumeration elements list.
Channel (n) Value
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write
Mirror of Modulo Value
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACMOD : Modulo Fractional Value
bits : 11 - 15 (5 bit)
access : read-write
MOD : Mirror of the Modulo Integer Value
bits : 16 - 31 (16 bit)
access : read-write
Mirror of Channel (n) Match Value
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL : Channel (n) Match Fractional Value
bits : 11 - 15 (5 bit)
access : read-write
VAL : Mirror of the Channel (n) Match Integer Value
bits : 16 - 31 (16 bit)
access : read-write
Mirror of Channel (n) Match Value
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL : Channel (n) Match Fractional Value
bits : 11 - 15 (5 bit)
access : read-write
VAL : Mirror of the Channel (n) Match Integer Value
bits : 16 - 31 (16 bit)
access : read-write
Mirror of Channel (n) Match Value
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL : Channel (n) Match Fractional Value
bits : 11 - 15 (5 bit)
access : read-write
VAL : Mirror of the Channel (n) Match Integer Value
bits : 16 - 31 (16 bit)
access : read-write
Mirror of Channel (n) Match Value
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL : Channel (n) Match Fractional Value
bits : 11 - 15 (5 bit)
access : read-write
VAL : Mirror of the Channel (n) Match Integer Value
bits : 16 - 31 (16 bit)
access : read-write
Mirror of Channel (n) Match Value
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL : Channel (n) Match Fractional Value
bits : 11 - 15 (5 bit)
access : read-write
VAL : Mirror of the Channel (n) Match Integer Value
bits : 16 - 31 (16 bit)
access : read-write
Mirror of Channel (n) Match Value
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL : Channel (n) Match Fractional Value
bits : 11 - 15 (5 bit)
access : read-write
VAL : Mirror of the Channel (n) Match Integer Value
bits : 16 - 31 (16 bit)
access : read-write
Mirror of Channel (n) Match Value
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL : Channel (n) Match Fractional Value
bits : 11 - 15 (5 bit)
access : read-write
VAL : Mirror of the Channel (n) Match Integer Value
bits : 16 - 31 (16 bit)
access : read-write
Mirror of Channel (n) Match Value
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL : Channel (n) Match Fractional Value
bits : 11 - 15 (5 bit)
access : read-write
VAL : Mirror of the Channel (n) Match Integer Value
bits : 16 - 31 (16 bit)
access : read-write
Channel (n) Status And Control
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA : DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable DMA transfers.
#1 : 1
Enable DMA transfers.
End of enumeration elements list.
ICRST : FTM counter reset by the selected input capture event.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM counter is not reset when the selected channel (n) input event is detected.
#1 : 1
FTM counter is reset when the selected channel (n) input event is detected.
End of enumeration elements list.
ELSA : Channel (n) Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write
ELSB : Channel (n) Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write
MSA : Channel (n) Mode Select
bits : 4 - 4 (1 bit)
access : read-write
MSB : Channel (n) Mode Select
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel (n) Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel (n) interrupt. Use software polling.
#1 : 1
Enable channel (n) interrupt.
End of enumeration elements list.
CHF : Channel (n) Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
No channel (n) event has occurred.
#1 : 1
A channel (n) event has occurred.
End of enumeration elements list.
TRIGMODE : Trigger mode control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel outputs will generate the normal PWM outputs without generating a pulse.
#1 : 1
If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.
End of enumeration elements list.
CHIS : Channel (n) Input State
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
The channel (n) input is zero.
#1 : 1
The channel (n) input is one.
End of enumeration elements list.
CHOV : Channel (n) Output Value
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
The channel (n) output is zero.
#1 : 1
The channel (n) output is one.
End of enumeration elements list.
Channel (n) Value
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write
Channel (n) Status And Control
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA : DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable DMA transfers.
#1 : 1
Enable DMA transfers.
End of enumeration elements list.
ICRST : FTM counter reset by the selected input capture event.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM counter is not reset when the selected channel (n) input event is detected.
#1 : 1
FTM counter is reset when the selected channel (n) input event is detected.
End of enumeration elements list.
ELSA : Channel (n) Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write
ELSB : Channel (n) Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write
MSA : Channel (n) Mode Select
bits : 4 - 4 (1 bit)
access : read-write
MSB : Channel (n) Mode Select
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel (n) Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel (n) interrupt. Use software polling.
#1 : 1
Enable channel (n) interrupt.
End of enumeration elements list.
CHF : Channel (n) Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
No channel (n) event has occurred.
#1 : 1
A channel (n) event has occurred.
End of enumeration elements list.
TRIGMODE : Trigger mode control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel outputs will generate the normal PWM outputs without generating a pulse.
#1 : 1
If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.
End of enumeration elements list.
CHIS : Channel (n) Input State
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
The channel (n) input is zero.
#1 : 1
The channel (n) input is one.
End of enumeration elements list.
CHOV : Channel (n) Output Value
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
The channel (n) output is zero.
#1 : 1
The channel (n) output is one.
End of enumeration elements list.
Channel (n) Value
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write
Channel (n) Status And Control
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA : DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable DMA transfers.
#1 : 1
Enable DMA transfers.
End of enumeration elements list.
ICRST : FTM counter reset by the selected input capture event.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM counter is not reset when the selected channel (n) input event is detected.
#1 : 1
FTM counter is reset when the selected channel (n) input event is detected.
End of enumeration elements list.
ELSA : Channel (n) Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write
ELSB : Channel (n) Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write
MSA : Channel (n) Mode Select
bits : 4 - 4 (1 bit)
access : read-write
MSB : Channel (n) Mode Select
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel (n) Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel (n) interrupt. Use software polling.
#1 : 1
Enable channel (n) interrupt.
End of enumeration elements list.
CHF : Channel (n) Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
No channel (n) event has occurred.
#1 : 1
A channel (n) event has occurred.
End of enumeration elements list.
TRIGMODE : Trigger mode control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel outputs will generate the normal PWM outputs without generating a pulse.
#1 : 1
If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.
End of enumeration elements list.
CHIS : Channel (n) Input State
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
The channel (n) input is zero.
#1 : 1
The channel (n) input is one.
End of enumeration elements list.
CHOV : Channel (n) Output Value
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
The channel (n) output is zero.
#1 : 1
The channel (n) output is one.
End of enumeration elements list.
Channel (n) Value
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write
Channel (n) Status And Control
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA : DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable DMA transfers.
#1 : 1
Enable DMA transfers.
End of enumeration elements list.
ICRST : FTM counter reset by the selected input capture event.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM counter is not reset when the selected channel (n) input event is detected.
#1 : 1
FTM counter is reset when the selected channel (n) input event is detected.
End of enumeration elements list.
ELSA : Channel (n) Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write
ELSB : Channel (n) Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write
MSA : Channel (n) Mode Select
bits : 4 - 4 (1 bit)
access : read-write
MSB : Channel (n) Mode Select
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel (n) Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel (n) interrupt. Use software polling.
#1 : 1
Enable channel (n) interrupt.
End of enumeration elements list.
CHF : Channel (n) Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
No channel (n) event has occurred.
#1 : 1
A channel (n) event has occurred.
End of enumeration elements list.
TRIGMODE : Trigger mode control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel outputs will generate the normal PWM outputs without generating a pulse.
#1 : 1
If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.
End of enumeration elements list.
CHIS : Channel (n) Input State
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
The channel (n) input is zero.
#1 : 1
The channel (n) input is one.
End of enumeration elements list.
CHOV : Channel (n) Output Value
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
The channel (n) output is zero.
#1 : 1
The channel (n) output is one.
End of enumeration elements list.
Counter
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Counter Value
bits : 0 - 15 (16 bit)
access : read-write
Channel (n) Value
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write
Channel (n) Status And Control
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA : DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable DMA transfers.
#1 : 1
Enable DMA transfers.
End of enumeration elements list.
ICRST : FTM counter reset by the selected input capture event.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM counter is not reset when the selected channel (n) input event is detected.
#1 : 1
FTM counter is reset when the selected channel (n) input event is detected.
End of enumeration elements list.
ELSA : Channel (n) Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write
ELSB : Channel (n) Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write
MSA : Channel (n) Mode Select
bits : 4 - 4 (1 bit)
access : read-write
MSB : Channel (n) Mode Select
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel (n) Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel (n) interrupt. Use software polling.
#1 : 1
Enable channel (n) interrupt.
End of enumeration elements list.
CHF : Channel (n) Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
No channel (n) event has occurred.
#1 : 1
A channel (n) event has occurred.
End of enumeration elements list.
TRIGMODE : Trigger mode control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel outputs will generate the normal PWM outputs without generating a pulse.
#1 : 1
If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.
End of enumeration elements list.
CHIS : Channel (n) Input State
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
The channel (n) input is zero.
#1 : 1
The channel (n) input is one.
End of enumeration elements list.
CHOV : Channel (n) Output Value
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
The channel (n) output is zero.
#1 : 1
The channel (n) output is one.
End of enumeration elements list.
Channel (n) Value
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write
Counter Initial Value
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT : INIT
bits : 0 - 15 (16 bit)
access : read-write
Capture And Compare Status
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH0F : Channel 0 Flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
CH1F : Channel 1 Flag
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
CH2F : Channel 2 Flag
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
CH3F : Channel 3 Flag
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
CH4F : Channel 4 Flag
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
CH5F : Channel 5 Flag
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
CH6F : Channel 6 Flag
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
CH7F : Channel 7 Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
Features Mode Selection
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTMEN : FTM Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
TPM compatibility. Free running counter and synchronization compatible with TPM.
#1 : 1
Free running counter and synchronization are different from TPM behavior.
End of enumeration elements list.
INIT : Initialize The Channels Output
bits : 1 - 1 (1 bit)
access : write-only
WPDIS : Write Protection Disable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Write protection is enabled.
#1 : 1
Write protection is disabled.
End of enumeration elements list.
PWMSYNC : PWM Synchronization Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.
#1 : 1
Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.
End of enumeration elements list.
CAPTEST : Capture Test Mode Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture test mode is disabled.
#1 : 1
Capture test mode is enabled.
End of enumeration elements list.
FAULTM : Fault Control Mode
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
#00 : 00
Fault control is disabled for all channels.
#01 : 01
Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.
#10 : 10
Fault control is enabled for all channels, and the selected mode is the manual fault clearing.
#11 : 11
Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.
End of enumeration elements list.
FAULTIE : Fault Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault control interrupt is disabled.
#1 : 1
Fault control interrupt is enabled.
End of enumeration elements list.
Synchronization
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTMIN : Minimum Loading Point Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minimum loading point is disabled.
#1 : 1
The minimum loading point is enabled.
End of enumeration elements list.
CNTMAX : Maximum Loading Point Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The maximum loading point is disabled.
#1 : 1
The maximum loading point is enabled.
End of enumeration elements list.
REINIT : FTM Counter Reinitialization by Synchronization
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM counter continues to count normally.
#1 : 1
FTM counter is updated with its initial value when the selected trigger is detected.
End of enumeration elements list.
SYNCHOM : Output Mask Synchronization
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
OUTMASK register is updated with the value of its buffer in all rising edges of the FTM input clock.
#1 : 1
OUTMASK register is updated with the value of its buffer only by the PWM synchronization.
End of enumeration elements list.
TRIG0 : PWM Synchronization Hardware Trigger 0
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trigger is disabled.
#1 : 1
Trigger is enabled.
End of enumeration elements list.
TRIG1 : PWM Synchronization Hardware Trigger 1
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trigger is disabled.
#1 : 1
Trigger is enabled.
End of enumeration elements list.
TRIG2 : PWM Synchronization Hardware Trigger 2
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trigger is disabled.
#1 : 1
Trigger is enabled.
End of enumeration elements list.
SWSYNC : PWM Synchronization Software Trigger
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Software trigger is not selected.
#1 : 1
Software trigger is selected.
End of enumeration elements list.
Initial State For Channels Output
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0OI : Channel 0 Output Initialization Value
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
End of enumeration elements list.
CH1OI : Channel 1 Output Initialization Value
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
End of enumeration elements list.
CH2OI : Channel 2 Output Initialization Value
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
End of enumeration elements list.
CH3OI : Channel 3 Output Initialization Value
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
End of enumeration elements list.
CH4OI : Channel 4 Output Initialization Value
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
End of enumeration elements list.
CH5OI : Channel 5 Output Initialization Value
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
End of enumeration elements list.
CH6OI : Channel 6 Output Initialization Value
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
End of enumeration elements list.
CH7OI : Channel 7 Output Initialization Value
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
End of enumeration elements list.
Output Mask
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0OM : Channel 0 Output Mask
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH1OM : Channel 1 Output Mask
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH2OM : Channel 2 Output Mask
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH3OM : Channel 3 Output Mask
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH4OM : Channel 4 Output Mask
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH5OM : Channel 5 Output Mask
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH6OM : Channel 6 Output Mask
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH7OM : Channel 7 Output Mask
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
Function For Linked Channels
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMBINE0 : Combine Channels For n = 0
bits : 0 - 0 (1 bit)
access : read-write
COMP0 : Complement Of Channel (n) For n = 0
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel (n+1) output is the same as the channel (n) output.
#1 : 1
The channel (n+1) output is the complement of the channel (n) output.
End of enumeration elements list.
DECAPEN0 : Dual Edge Capture Mode Enable For n = 0
bits : 2 - 2 (1 bit)
access : read-write
DECAP0 : Dual Edge Capture Mode Captures For n = 0
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The dual edge captures are inactive.
#1 : 1
The dual edge captures are active.
End of enumeration elements list.
DTEN0 : Deadtime Enable For n = 0
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The deadtime insertion in this pair of channels is disabled.
#1 : 1
The deadtime insertion in this pair of channels is enabled.
End of enumeration elements list.
SYNCEN0 : Synchronization Enable For n = 0
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PWM synchronization in this pair of channels is disabled.
#1 : 1
The PWM synchronization in this pair of channels is enabled.
End of enumeration elements list.
FAULTEN0 : Fault Control Enable For n = 0
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault control in this pair of channels is disabled.
#1 : 1
The fault control in this pair of channels is enabled.
End of enumeration elements list.
MCOMBINE0 : Modified Combine Mode For n = 0
bits : 7 - 7 (1 bit)
access : read-write
COMBINE1 : Combine Channels For n = 2
bits : 8 - 8 (1 bit)
access : read-write
COMP1 : Complement Of Channel (n) For n = 2
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel (n+1) output is the same as the channel (n) output.
#1 : 1
The channel (n+1) output is the complement of the channel (n) output.
End of enumeration elements list.
DECAPEN1 : Dual Edge Capture Mode Enable For n = 2
bits : 10 - 10 (1 bit)
access : read-write
DECAP1 : Dual Edge Capture Mode Captures For n = 2
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
The dual edge captures are inactive.
#1 : 1
The dual edge captures are active.
End of enumeration elements list.
DTEN1 : Deadtime Enable For n = 2
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
The deadtime insertion in this pair of channels is disabled.
#1 : 1
The deadtime insertion in this pair of channels is enabled.
End of enumeration elements list.
SYNCEN1 : Synchronization Enable For n = 2
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PWM synchronization in this pair of channels is disabled.
#1 : 1
The PWM synchronization in this pair of channels is enabled.
End of enumeration elements list.
FAULTEN1 : Fault Control Enable For n = 2
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault control in this pair of channels is disabled.
#1 : 1
The fault control in this pair of channels is enabled.
End of enumeration elements list.
MCOMBINE1 : Modified Combine Mode For n = 2
bits : 15 - 15 (1 bit)
access : read-write
COMBINE2 : Combine Channels For n = 4
bits : 16 - 16 (1 bit)
access : read-write
COMP2 : Complement Of Channel (n) For n = 4
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel (n+1) output is the same as the channel (n) output.
#1 : 1
The channel (n+1) output is the complement of the channel (n) output.
End of enumeration elements list.
DECAPEN2 : Dual Edge Capture Mode Enable For n = 4
bits : 18 - 18 (1 bit)
access : read-write
DECAP2 : Dual Edge Capture Mode Captures For n = 4
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
The dual edge captures are inactive.
#1 : 1
The dual edge captures are active.
End of enumeration elements list.
DTEN2 : Deadtime Enable For n = 4
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
The deadtime insertion in this pair of channels is disabled.
#1 : 1
The deadtime insertion in this pair of channels is enabled.
End of enumeration elements list.
SYNCEN2 : Synchronization Enable For n = 4
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PWM synchronization in this pair of channels is disabled.
#1 : 1
The PWM synchronization in this pair of channels is enabled.
End of enumeration elements list.
FAULTEN2 : Fault Control Enable For n = 4
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault control in this pair of channels is disabled.
#1 : 1
The fault control in this pair of channels is enabled.
End of enumeration elements list.
MCOMBINE2 : Modified Combine Mode For n = 4
bits : 23 - 23 (1 bit)
access : read-write
COMBINE3 : Combine Channels For n = 6
bits : 24 - 24 (1 bit)
access : read-write
COMP3 : Complement Of Channel (n) for n = 6
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel (n+1) output is the same as the channel (n) output.
#1 : 1
The channel (n+1) output is the complement of the channel (n) output.
End of enumeration elements list.
DECAPEN3 : Dual Edge Capture Mode Enable For n = 6
bits : 26 - 26 (1 bit)
access : read-write
DECAP3 : Dual Edge Capture Mode Captures For n = 6
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
The dual edge captures are inactive.
#1 : 1
The dual edge captures are active.
End of enumeration elements list.
DTEN3 : Deadtime Enable For n = 6
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
The deadtime insertion in this pair of channels is disabled.
#1 : 1
The deadtime insertion in this pair of channels is enabled.
End of enumeration elements list.
SYNCEN3 : Synchronization Enable For n = 6
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PWM synchronization in this pair of channels is disabled.
#1 : 1
The PWM synchronization in this pair of channels is enabled.
End of enumeration elements list.
FAULTEN3 : Fault Control Enable For n = 6
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault control in this pair of channels is disabled.
#1 : 1
The fault control in this pair of channels is enabled.
End of enumeration elements list.
MCOMBINE3 : Modified Combine Mode For n = 6
bits : 31 - 31 (1 bit)
access : read-write
Deadtime Configuration
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTVAL : Deadtime Value
bits : 0 - 5 (6 bit)
access : read-write
DTPS : Deadtime Prescaler Value
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#0x : 0x
Divide the FTM input clock by 1.
#10 : 10
Divide the FTM input clock by 4.
#11 : 11
Divide the FTM input clock by 16.
End of enumeration elements list.
DTVALEX : Extended Deadtime Value
bits : 16 - 19 (4 bit)
access : read-write
FTM External Trigger
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH2TRIG : Channel 2 External Trigger Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of this external trigger is disabled.
#1 : 1
The generation of this external trigger is enabled.
End of enumeration elements list.
CH3TRIG : Channel 3 External Trigger Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of this external trigger is disabled.
#1 : 1
The generation of this external trigger is enabled.
End of enumeration elements list.
CH4TRIG : Channel 4 External Trigger Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of this external trigger is disabled.
#1 : 1
The generation of this external trigger is enabled.
End of enumeration elements list.
CH5TRIG : Channel 5 External Trigger Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of this external trigger is disabled.
#1 : 1
The generation of this external trigger is enabled.
End of enumeration elements list.
CH0TRIG : Channel 0 External Trigger Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of this external trigger is disabled.
#1 : 1
The generation of this external trigger is enabled.
End of enumeration elements list.
CH1TRIG : Channel 1 External Trigger Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of this external trigger is disabled.
#1 : 1
The generation of this external trigger is enabled.
End of enumeration elements list.
INITTRIGEN : Initialization Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of initialization trigger is disabled.
#1 : 1
The generation of initialization trigger is enabled.
End of enumeration elements list.
TRIGF : Channel Trigger Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
No channel trigger was generated.
#1 : 1
A channel trigger was generated.
End of enumeration elements list.
CH6TRIG : Channel 6 External Trigger Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of this external trigger is disabled.
#1 : 1
The generation of this external trigger is enabled.
End of enumeration elements list.
CH7TRIG : Channel 7 External Trigger Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of this external trigger is disabled.
#1 : 1
The generation of this external trigger is enabled.
End of enumeration elements list.
Channels Polarity
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POL0 : Channel 0 Polarity
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
POL1 : Channel 1 Polarity
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
POL2 : Channel 2 Polarity
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
POL3 : Channel 3 Polarity
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
POL4 : Channel 4 Polarity
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
POL5 : Channel 5 Polarity
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
POL6 : Channel 6 Polarity
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
POL7 : Channel 7 Polarity
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
Fault Mode Status
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FAULTF0 : Fault Detection Flag 0
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
No fault condition was detected at the fault input.
#1 : 1
A fault condition was detected at the fault input.
End of enumeration elements list.
FAULTF1 : Fault Detection Flag 1
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
No fault condition was detected at the fault input.
#1 : 1
A fault condition was detected at the fault input.
End of enumeration elements list.
FAULTF2 : Fault Detection Flag 2
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
No fault condition was detected at the fault input.
#1 : 1
A fault condition was detected at the fault input.
End of enumeration elements list.
FAULTF3 : Fault Detection Flag 3
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
No fault condition was detected at the fault input.
#1 : 1
A fault condition was detected at the fault input.
End of enumeration elements list.
FAULTIN : Fault Inputs
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
The logic OR of the enabled fault inputs is 0.
#1 : 1
The logic OR of the enabled fault inputs is 1.
End of enumeration elements list.
WPEN : Write Protection Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Write protection is disabled. Write protected bits can be written.
#1 : 1
Write protection is enabled. Write protected bits cannot be written.
End of enumeration elements list.
FAULTF : Fault Detection Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
No fault condition was detected.
#1 : 1
A fault condition was detected.
End of enumeration elements list.
Input Capture Filter Control
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0FVAL : Channel 0 Input Filter
bits : 0 - 3 (4 bit)
access : read-write
CH1FVAL : Channel 1 Input Filter
bits : 4 - 7 (4 bit)
access : read-write
CH2FVAL : Channel 2 Input Filter
bits : 8 - 11 (4 bit)
access : read-write
CH3FVAL : Channel 3 Input Filter
bits : 12 - 15 (4 bit)
access : read-write
Fault Control
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FAULT0EN : Fault Input 0 Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input is disabled.
#1 : 1
Fault input is enabled.
End of enumeration elements list.
FAULT1EN : Fault Input 1 Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input is disabled.
#1 : 1
Fault input is enabled.
End of enumeration elements list.
FAULT2EN : Fault Input 2 Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input is disabled.
#1 : 1
Fault input is enabled.
End of enumeration elements list.
FAULT3EN : Fault Input 3 Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input is disabled.
#1 : 1
Fault input is enabled.
End of enumeration elements list.
FFLTR0EN : Fault Input 0 Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input filter is disabled.
#1 : 1
Fault input filter is enabled.
End of enumeration elements list.
FFLTR1EN : Fault Input 1 Filter Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input filter is disabled.
#1 : 1
Fault input filter is enabled.
End of enumeration elements list.
FFLTR2EN : Fault Input 2 Filter Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input filter is disabled.
#1 : 1
Fault input filter is enabled.
End of enumeration elements list.
FFLTR3EN : Fault Input 3 Filter Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input filter is disabled.
#1 : 1
Fault input filter is enabled.
End of enumeration elements list.
FFVAL : Fault Input Filter
bits : 8 - 11 (4 bit)
access : read-write
FSTATE : Fault output state
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM outputs will be placed into safe values when fault events in ongoing (defined by POL bits).
#1 : 1
FTM outputs will be tri-stated when fault event is ongoing
End of enumeration elements list.
Modulo
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD : MOD
bits : 0 - 15 (16 bit)
access : read-write
Quadrature Decoder Control And Status
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QUADEN : Quadrature Decoder Mode Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Quadrature Decoder mode is disabled.
#1 : 1
Quadrature Decoder mode is enabled.
End of enumeration elements list.
TOFDIR : Timer Overflow Direction In Quadrature Decoder Mode
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register).
#1 : 1
TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).
End of enumeration elements list.
QUADIR : FTM Counter Direction In Quadrature Decoder Mode
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Counting direction is decreasing (FTM counter decrement).
#1 : 1
Counting direction is increasing (FTM counter increment).
End of enumeration elements list.
QUADMODE : Quadrature Decoder Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Phase A and phase B encoding mode.
#1 : 1
Count and direction encoding mode.
End of enumeration elements list.
PHBPOL : Phase B Input Polarity
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal.
#1 : 1
Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.
End of enumeration elements list.
PHAPOL : Phase A Input Polarity
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal.
#1 : 1
Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.
End of enumeration elements list.
PHBFLTREN : Phase B Input Filter Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Phase B input filter is disabled.
#1 : 1
Phase B input filter is enabled.
End of enumeration elements list.
PHAFLTREN : Phase A Input Filter Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Phase A input filter is disabled.
#1 : 1
Phase A input filter is enabled.
End of enumeration elements list.
Configuration
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LDFQ : Frequency of the Reload Opportunities
bits : 0 - 4 (5 bit)
access : read-write
BDMMODE : Debug Mode
bits : 6 - 7 (2 bit)
access : read-write
GTBEEN : Global Time Base Enable
bits : 9 - 9 (1 bit)
access : read-write
GTBEOUT : Global Time Base Output
bits : 10 - 10 (1 bit)
access : read-write
ITRIGR : Initialization trigger on Reload Point
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Initialization trigger is generated on counter wrap events.
#1 : 1
Initialization trigger is generated when a reload point is reached.
End of enumeration elements list.
FTM Fault Input Polarity
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLT0POL : Fault Input 0 Polarity
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#1 : 1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
End of enumeration elements list.
FLT1POL : Fault Input 1 Polarity
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#1 : 1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
End of enumeration elements list.
FLT2POL : Fault Input 2 Polarity
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#1 : 1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
End of enumeration elements list.
FLT3POL : Fault Input 3 Polarity
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#1 : 1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
End of enumeration elements list.
Synchronization Configuration
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HWTRIGMODE : Hardware Trigger Mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
#1 : 1
FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
End of enumeration elements list.
CNTINC : CNTIN Register Synchronization
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
CNTIN register is updated with its buffer value at all rising edges of FTM input clock.
#1 : 1
CNTIN register is updated with its buffer value by the PWM synchronization.
End of enumeration elements list.
INVC : INVCTRL Register Synchronization
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
INVCTRL register is updated with its buffer value at all rising edges of FTM input clock.
#1 : 1
INVCTRL register is updated with its buffer value by the PWM synchronization.
End of enumeration elements list.
SWOC : SWOCTRL Register Synchronization
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
SWOCTRL register is updated with its buffer value at all rising edges of FTM input clock.
#1 : 1
SWOCTRL register is updated with its buffer value by the PWM synchronization.
End of enumeration elements list.
SYNCMODE : Synchronization Mode
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Legacy PWM synchronization is selected.
#1 : 1
Enhanced PWM synchronization is selected.
End of enumeration elements list.
SWRSTCNT : FTM counter synchronization is activated by the software trigger
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software trigger does not activate the FTM counter synchronization.
#1 : 1
The software trigger activates the FTM counter synchronization.
End of enumeration elements list.
SWWRBUF : MOD, HCR, CNTIN, and CV registers synchronization is activated by the software trigger
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization.
#1 : 1
The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization.
End of enumeration elements list.
SWOM : Output mask synchronization is activated by the software trigger
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software trigger does not activate the OUTMASK register synchronization.
#1 : 1
The software trigger activates the OUTMASK register synchronization.
End of enumeration elements list.
SWINVC : Inverting control synchronization is activated by the software trigger
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software trigger does not activate the INVCTRL register synchronization.
#1 : 1
The software trigger activates the INVCTRL register synchronization.
End of enumeration elements list.
SWSOC : Software output control synchronization is activated by the software trigger
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software trigger does not activate the SWOCTRL register synchronization.
#1 : 1
The software trigger activates the SWOCTRL register synchronization.
End of enumeration elements list.
HWRSTCNT : FTM counter synchronization is activated by a hardware trigger
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
A hardware trigger does not activate the FTM counter synchronization.
#1 : 1
A hardware trigger activates the FTM counter synchronization.
End of enumeration elements list.
HWWRBUF : MOD, HCR, CNTIN, and CV registers synchronization is activated by a hardware trigger
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization.
#1 : 1
A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization.
End of enumeration elements list.
HWOM : Output mask synchronization is activated by a hardware trigger
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
A hardware trigger does not activate the OUTMASK register synchronization.
#1 : 1
A hardware trigger activates the OUTMASK register synchronization.
End of enumeration elements list.
HWINVC : Inverting control synchronization is activated by a hardware trigger
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
A hardware trigger does not activate the INVCTRL register synchronization.
#1 : 1
A hardware trigger activates the INVCTRL register synchronization.
End of enumeration elements list.
HWSOC : Software output control synchronization is activated by a hardware trigger
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
A hardware trigger does not activate the SWOCTRL register synchronization.
#1 : 1
A hardware trigger activates the SWOCTRL register synchronization.
End of enumeration elements list.
FTM Inverting Control
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INV0EN : Pair Channels 0 Inverting Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverting is disabled.
#1 : 1
Inverting is enabled.
End of enumeration elements list.
INV1EN : Pair Channels 1 Inverting Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverting is disabled.
#1 : 1
Inverting is enabled.
End of enumeration elements list.
INV2EN : Pair Channels 2 Inverting Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverting is disabled.
#1 : 1
Inverting is enabled.
End of enumeration elements list.
INV3EN : Pair Channels 3 Inverting Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverting is disabled.
#1 : 1
Inverting is enabled.
End of enumeration elements list.
FTM Software Output Control
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0OC : Channel 0 Software Output Control Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
End of enumeration elements list.
CH1OC : Channel 1 Software Output Control Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
End of enumeration elements list.
CH2OC : Channel 2 Software Output Control Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
End of enumeration elements list.
CH3OC : Channel 3 Software Output Control Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
End of enumeration elements list.
CH4OC : Channel 4 Software Output Control Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
End of enumeration elements list.
CH5OC : Channel 5 Software Output Control Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
End of enumeration elements list.
CH6OC : Channel 6 Software Output Control Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
End of enumeration elements list.
CH7OC : Channel 7 Software Output Control Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
End of enumeration elements list.
CH0OCV : Channel 0 Software Output Control Value
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH1OCV : Channel 1 Software Output Control Value
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH2OCV : Channel 2 Software Output Control Value
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH3OCV : Channel 3 Software Output Control Value
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH4OCV : Channel 4 Software Output Control Value
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH5OCV : Channel 5 Software Output Control Value
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH6OCV : Channel 6 Software Output Control Value
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH7OCV : Channel 7 Software Output Control Value
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
End of enumeration elements list.
FTM PWM Load
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0SEL : Channel 0 Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel match is not included as a reload opportunity.
#1 : 1
Channel match is included as a reload opportunity.
End of enumeration elements list.
CH1SEL : Channel 1 Select
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel match is not included as a reload opportunity.
#1 : 1
Channel match is included as a reload opportunity.
End of enumeration elements list.
CH2SEL : Channel 2 Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel match is not included as a reload opportunity.
#1 : 1
Channel match is included as a reload opportunity.
End of enumeration elements list.
CH3SEL : Channel 3 Select
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel match is not included as a reload opportunity.
#1 : 1
Channel match is included as a reload opportunity.
End of enumeration elements list.
CH4SEL : Channel 4 Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel match is not included as a reload opportunity.
#1 : 1
Channel match is included as a reload opportunity.
End of enumeration elements list.
CH5SEL : Channel 5 Select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel match is not included as a reload opportunity.
#1 : 1
Channel match is included as a reload opportunity.
End of enumeration elements list.
CH6SEL : Channel 6 Select
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel match is not included as a reload opportunity.
#1 : 1
Channel match is included as a reload opportunity.
End of enumeration elements list.
CH7SEL : Channel 7 Select
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel match is not included as a reload opportunity.
#1 : 1
Channel match is included as a reload opportunity.
End of enumeration elements list.
HCSEL : Half Cycle Select
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Half cycle reload is disabled and it is not considered as a reload opportunity.
#1 : 1
Half cycle reload is enabled and it is considered as a reload opportunity.
End of enumeration elements list.
LDOK : Load Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Loading updated values is disabled.
#1 : 1
Loading updated values is enabled.
End of enumeration elements list.
GLEN : Global Load Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Global Load Ok disabled.
#1 : 1
Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit.
End of enumeration elements list.
GLDOK : Global Load OK
bits : 11 - 11 (1 bit)
access : write-only
Enumeration:
#0 : 0
No action.
#1 : 1
LDOK bit is set.
End of enumeration elements list.
Half Cycle Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCVAL : Half Cycle Value
bits : 0 - 15 (16 bit)
access : read-write
Pair 0 Deadtime Configuration
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTVAL : Deadtime Value
bits : 0 - 5 (6 bit)
access : read-write
DTPS : Deadtime Prescaler Value
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#0x : 0x
Divide the FTM input clock by 1.
#10 : 10
Divide the FTM input clock by 4.
#11 : 11
Divide the FTM input clock by 16.
End of enumeration elements list.
DTVALEX : Extended Deadtime Value
bits : 16 - 19 (4 bit)
access : read-write
Pair 1 Deadtime Configuration
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTVAL : Deadtime Value
bits : 0 - 5 (6 bit)
access : read-write
DTPS : Deadtime Prescaler Value
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#0x : 0x
Divide the FTM input clock by 1.
#10 : 10
Divide the FTM input clock by 4.
#11 : 11
Divide the FTM input clock by 16.
End of enumeration elements list.
DTVALEX : Extended Deadtime Value
bits : 16 - 19 (4 bit)
access : read-write
Pair 2 Deadtime Configuration
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTVAL : Deadtime Value
bits : 0 - 5 (6 bit)
access : read-write
DTPS : Deadtime Prescaler Value
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#0x : 0x
Divide the FTM input clock by 1.
#10 : 10
Divide the FTM input clock by 4.
#11 : 11
Divide the FTM input clock by 16.
End of enumeration elements list.
DTVALEX : Extended Deadtime Value
bits : 16 - 19 (4 bit)
access : read-write
Pair 3 Deadtime Configuration
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTVAL : Deadtime Value
bits : 0 - 5 (6 bit)
access : read-write
DTPS : Deadtime Prescaler Value
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#0x : 0x
Divide the FTM input clock by 1.
#10 : 10
Divide the FTM input clock by 4.
#11 : 11
Divide the FTM input clock by 16.
End of enumeration elements list.
DTVALEX : Extended Deadtime Value
bits : 16 - 19 (4 bit)
access : read-write
Channel (n) Status And Control
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA : DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable DMA transfers.
#1 : 1
Enable DMA transfers.
End of enumeration elements list.
ICRST : FTM counter reset by the selected input capture event.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM counter is not reset when the selected channel (n) input event is detected.
#1 : 1
FTM counter is reset when the selected channel (n) input event is detected.
End of enumeration elements list.
ELSA : Channel (n) Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write
ELSB : Channel (n) Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write
MSA : Channel (n) Mode Select
bits : 4 - 4 (1 bit)
access : read-write
MSB : Channel (n) Mode Select
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel (n) Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel (n) interrupt. Use software polling.
#1 : 1
Enable channel (n) interrupt.
End of enumeration elements list.
CHF : Channel (n) Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
No channel (n) event has occurred.
#1 : 1
A channel (n) event has occurred.
End of enumeration elements list.
TRIGMODE : Trigger mode control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel outputs will generate the normal PWM outputs without generating a pulse.
#1 : 1
If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.
End of enumeration elements list.
CHIS : Channel (n) Input State
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
The channel (n) input is zero.
#1 : 1
The channel (n) input is one.
End of enumeration elements list.
CHOV : Channel (n) Output Value
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
The channel (n) output is zero.
#1 : 1
The channel (n) output is one.
End of enumeration elements list.
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