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MCM

Peripheral Memory Blocks

address_offset : 0x8 Bytes (0x0)
size : 0x4A0 byte (0x0)
mem_usage : registers
protection :

Registers

PID

CPO

LMDR0

LMDR1

LMPECR

LMPEIR

LMFAR

LMFATR

LMFDHR

LMFDLR

PLASC

PLAMC

CPCR


PID

Process ID Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PID PID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID

PID : M0_PID and M1_PID for MPU
bits : 0 - 7 (8 bit)
access : read-write


CPO

Compute Operation Control Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPO CPO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPOREQ CPOACK CPOWOI

CPOREQ : Compute Operation Request
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Request is cleared.

#1 : 1

Request Compute Operation.

End of enumeration elements list.

CPOACK : Compute Operation Acknowledge
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Compute operation entry has not completed or compute operation exit has completed.

#1 : 1

Compute operation entry has completed or compute operation exit has not completed.

End of enumeration elements list.

CPOWOI : Compute Operation Wakeup On Interrupt
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect.

#1 : 1

When set, the CPOREQ is cleared on any interrupt or exception vector fetch.

End of enumeration elements list.


LMDR0

Local Memory Descriptor Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LMDR0 LMDR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CF0 MT DPW WY LMSZ LMSZH V

CF0 : Control Field 0 LMDR0[CF0] bit field is Reserved and Read-Only 0 for S32K11x variants.
bits : 0 - 3 (4 bit)
access : read-write

MT : Memory Type
bits : 13 - 15 (3 bit)
access : read-only

Enumeration:

#000 : 000

SRAM_L

#001 : 001

SRAM_U

End of enumeration elements list.

DPW : LMEM Data Path Width. This field defines the width of the local memory.
bits : 17 - 19 (3 bit)
access : read-only

Enumeration:

#010 : 010

LMEMn 32-bits wide

#011 : 011

LMEMn 64-bits wide

End of enumeration elements list.

WY : Level 1 Cache Ways
bits : 20 - 23 (4 bit)
access : read-only

Enumeration:

#0000 : 0000

No Cache

#0010 : 0010

2-Way Set Associative

#0100 : 0100

4-Way Set Associative

End of enumeration elements list.

LMSZ : LMEM Size
bits : 24 - 27 (4 bit)
access : read-only

Enumeration:

#0000 : 0000

no LMEMn (0 KB)

#0001 : 0001

1 KB LMEMn

#0010 : 0010

2 KB LMEMn

#0011 : 0011

4 KB LMEMn

#0100 : 0100

8 KB LMEMn

#0101 : 0101

16 KB LMEMn

#0110 : 0110

32 KB LMEMn

#0111 : 0111

64 KB LMEMn

#1000 : 1000

128 KB LMEMn

#1001 : 1001

256 KB LMEMn

#1010 : 1010

512 KB LMEMn

#1011 : 1011

1024 KB LMEMn

#1100 : 1100

2048 KB LMEMn

#1101 : 1101

4096 KB LMEMn

#1110 : 1110

8192 KB LMEMn

#1111 : 1111

16384 KB LMEMn

End of enumeration elements list.

LMSZH : LMEM Size Hole
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#0 : 0

LMEMn is a power-of-2 capacity.

#1 : 1

LMEMn is not a power-of-2, with a capacity is 0.75 * LMSZ.

End of enumeration elements list.

V : Local Memory Valid
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

#0 : 0

LMEMn is not present.

#1 : 1

LMEMn is present.

End of enumeration elements list.


LMDR1

Local Memory Descriptor Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LMDR1 LMDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CF0 MT DPW WY LMSZ LMSZH V

CF0 : Control Field 0 LMDR0[CF0] bit field is Reserved and Read-Only 0 for S32K11x variants.
bits : 0 - 3 (4 bit)
access : read-write

MT : Memory Type
bits : 13 - 15 (3 bit)
access : read-only

Enumeration:

#000 : 000

SRAM_L

#001 : 001

SRAM_U

End of enumeration elements list.

DPW : LMEM Data Path Width. This field defines the width of the local memory.
bits : 17 - 19 (3 bit)
access : read-only

Enumeration:

#010 : 010

LMEMn 32-bits wide

#011 : 011

LMEMn 64-bits wide

End of enumeration elements list.

WY : Level 1 Cache Ways
bits : 20 - 23 (4 bit)
access : read-only

Enumeration:

#0000 : 0000

No Cache

#0010 : 0010

2-Way Set Associative

#0100 : 0100

4-Way Set Associative

End of enumeration elements list.

LMSZ : LMEM Size
bits : 24 - 27 (4 bit)
access : read-only

Enumeration:

#0000 : 0000

no LMEMn (0 KB)

#0001 : 0001

1 KB LMEMn

#0010 : 0010

2 KB LMEMn

#0011 : 0011

4 KB LMEMn

#0100 : 0100

8 KB LMEMn

#0101 : 0101

16 KB LMEMn

#0110 : 0110

32 KB LMEMn

#0111 : 0111

64 KB LMEMn

#1000 : 1000

128 KB LMEMn

#1001 : 1001

256 KB LMEMn

#1010 : 1010

512 KB LMEMn

#1011 : 1011

1024 KB LMEMn

#1100 : 1100

2048 KB LMEMn

#1101 : 1101

4096 KB LMEMn

#1110 : 1110

8192 KB LMEMn

#1111 : 1111

16384 KB LMEMn

End of enumeration elements list.

LMSZH : LMEM Size Hole
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#0 : 0

LMEMn is a power-of-2 capacity.

#1 : 1

LMEMn is not a power-of-2, with a capacity is 0.75 * LMSZ.

End of enumeration elements list.

V : Local Memory Valid
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

#0 : 0

LMEMn is not present.

#1 : 1

LMEMn is present.

End of enumeration elements list.


LMPECR

LMEM Parity and ECC Control Register
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LMPECR LMPECR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LMPEIR

LMEM Parity and ECC Interrupt Register
address_offset : 0x488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LMPEIR LMPEIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENC E1B PEELOC V

ENC : ENCn = ECC Noncorrectable Error n
bits : 0 - 7 (8 bit)
access : read-write

E1B : E1Bn = ECC 1-bit Error n
bits : 8 - 15 (8 bit)
access : read-write

PEELOC : Parity or ECC Error Location
bits : 24 - 28 (5 bit)
access : read-only

Enumeration:

#00000 : 00

Non-correctable ECC event from SRAM_L

#00001 : 01

Non-correctable ECC event from SRAM_U

End of enumeration elements list.

V : Valid Bit
bits : 31 - 31 (1 bit)
access : read-only


LMFAR

LMEM Fault Address Register
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LMFAR LMFAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EFADD

EFADD : ECC Fault Address
bits : 0 - 31 (32 bit)
access : read-only


LMFATR

LMEM Fault Attribute Register
address_offset : 0x494 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LMFATR LMFATR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PEFPRT PEFSIZE PEFW PEFMST OVR

PEFPRT : Parity/ECC Fault Protection
bits : 0 - 3 (4 bit)
access : read-only

PEFSIZE : Parity/ECC Fault Master Size
bits : 4 - 6 (3 bit)
access : read-only

Enumeration:

#000 : 000

8-bit access

#001 : 001

16-bit access

#010 : 010

32-bit access

#011 : 011

64-bit access

End of enumeration elements list.

PEFW : Parity/ECC Fault Write
bits : 7 - 7 (1 bit)
access : read-only

PEFMST : Parity/ECC Fault Master Number
bits : 8 - 15 (8 bit)
access : read-only

OVR : Overrun
bits : 31 - 31 (1 bit)
access : read-only


LMFDHR

LMEM Fault Data High Register
address_offset : 0x4A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LMFDHR LMFDHR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PEFDH

PEFDH : Parity or ECC Fault Data High
bits : 0 - 31 (32 bit)
access : read-only


LMFDLR

LMEM Fault Data Low Register
address_offset : 0x4A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LMFDLR LMFDLR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PEFDL

PEFDL : Parity or ECC Fault Data Low
bits : 0 - 31 (32 bit)
access : read-only


PLASC

Crossbar Switch (AXBS) Slave Configuration
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PLASC PLASC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASC

ASC : Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port.
bits : 0 - 7 (8 bit)
access : read-only

Enumeration:

#0 : 0

A bus slave connection to AXBS input port n is absent

#1 : 1

A bus slave connection to AXBS input port n is present

End of enumeration elements list.


PLAMC

Crossbar Switch (AXBS) Master Configuration
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PLAMC PLAMC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMC

AMC : Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.
bits : 0 - 7 (8 bit)
access : read-only

Enumeration:

#0 : 0

A bus master connection to AXBS input port n is absent

#1 : 1

A bus master connection to AXBS input port n is present

End of enumeration elements list.


CPCR

Core Platform Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPCR CPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HLT_FSM_ST AXBS_HLT_REQ AXBS_HLTD FMC_PF_IDLE PBRIDGE_IDLE CBRR

HLT_FSM_ST : AXBS Halt State Machine Status
bits : 0 - 1 (2 bit)
access : read-only

Enumeration:

#00 : 00

Waiting for request

#01 : 01

Waiting for platform idle

#11 : 11

Platform stalled

#10 : 10

Unused state

End of enumeration elements list.

AXBS_HLT_REQ : AXBS Halt Request
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

AXBS is not receiving halt request

#1 : 1

AXBS is receiving halt request

End of enumeration elements list.

AXBS_HLTD : AXBS Halted
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

#0 : 0

AXBS is not currently halted

#1 : 1

AXBS is currently halted

End of enumeration elements list.

FMC_PF_IDLE : Flash Memory Controller Program Flash Idle
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

FMC program flash is not idle

#1 : 1

FMC program flash is currently idle

End of enumeration elements list.

PBRIDGE_IDLE : Peripheral Bridge Idle
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

PBRIDGE is not idle

#1 : 1

PBRIDGE is currently idle

End of enumeration elements list.

CBRR : Crossbar Round-robin Arbitration Enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fixed-priority arbitration

#1 : 1

Round-robin arbitration

End of enumeration elements list.



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