\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
No Description
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPVERSION : IP version ID
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASTER : Master mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SLAVE
Slave mode
1 : MASTER
Master mode
End of enumeration elements list.
CLKPOL : Clock Polarity
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : IDLELOW
The bus clock used in synchronous mode has a low base value
1 : IDLEHIGH
The bus clock used in synchronous mode has a high base value
End of enumeration elements list.
CLKPHA : Clock Edge for Setup/Sample
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SAMPLELEADING
Data is sampled on the leading edge and set-up on the trailing edge of the bus clock in synchronous mode
1 : SAMPLETRAILING
Data is set-up on the leading edge and sampled on the trailing edge of the bus clock in synchronous mode
End of enumeration elements list.
CSINV : Chip Select Invert
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : AL
Chip select is active low
1 : AH
Chip select is active high
End of enumeration elements list.
AUTOTX : Always Transmit When RXFIFO Not Full
bits : 4 - 4 (1 bit)
access : read-write
AUTOCS : Automatic Chip Select
bits : 5 - 5 (1 bit)
access : read-write
CLKPRSEN : PRS CLK Enable
bits : 6 - 6 (1 bit)
access : read-write
FORCELOAD : Force Load to Shift Register
bits : 7 - 7 (1 bit)
access : read-write
SDIV : Sync Clock Div
bits : 24 - 31 (8 bit)
access : read-write
No Description
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATABITS : Data-Bit Mode
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
1 : SEVEN
Each frame contains 7 data bits
2 : EIGHT
Each frame contains 8 data bits
3 : NINE
Each frame contains 9 data bits
4 : TEN
Each frame contains 10 data bits
5 : ELEVEN
Each frame contains 11 data bits
6 : TWELVE
Each frame contains 12 data bits
7 : THIRTEEN
Each frame contains 13 data bits
8 : FOURTEEN
Each frame contains 14 data bits
9 : FIFTEEN
Each frame contains 15 data bits
10 : SIXTEEN
Each frame contains 16 data bits
End of enumeration elements list.
PARITY : Parity-Bit Mode
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : NONE
Parity bits are not used
2 : EVEN
Even parity are used. Parity bits are automatically generated and checked by hardware.
3 : ODD
Odd parity is used. Parity bits are automatically generated and checked by hardware.
End of enumeration elements list.
STOPBITS : Stop-Bit Mode
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : HALF
The transmitter generates a half stop bit. Stop-bits are not verified by receiver
1 : ONE
One stop bit is generated and verified
2 : ONEANDAHALF
The transmitter generates one and a half stop bit. The receiver verifies the first stop bit
3 : TWO
The transmitter generates two stop bits. The receiver checks the first stop-bit only
End of enumeration elements list.
No Description
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTXDAT : Default TX DATA
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRHFEN : Enable IrDA Module
bits : 0 - 0 (1 bit)
access : read-write
IRHFPW : IrDA TX Pulse Width
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : ONE
IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1
1 : TWO
IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1
2 : THREE
IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1
3 : FOUR
IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1
End of enumeration elements list.
IRHFFILT : IrDA RX Filter
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
No filter enabled
1 : ENABLE
Filter enabled. IrDA pulse must be high for at least 5 consecutive clock cycles to be detected
End of enumeration elements list.
No Description
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXDELAY : TX Delay Transmission
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : NONE
Frames are transmitted immediately.
1 : SINGLE
Transmission of new frames is delayed by a single bit period.
2 : DOUBLE
Transmission of new frames is delayed by a two bit periods.
3 : TRIPPLE
Transmission of new frames is delayed by a three bit periods.
End of enumeration elements list.
CSSETUP : Chip Select Setup
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : ZERO
CS is asserted half or 1 baud-time before the start of transmission depending on CLKPHASE equal to 1 or 0 respectively
1 : ONE
CS is asserted 1 additional baud-time before start of transmission
2 : TWO
CS is asserted 2 additional baud-times before start of transmission
3 : THREE
CS is asserted 3 additional baud-times before start of transmission
4 : FOUR
CS is asserted 4 additional baud-times before start of transmission
5 : FIVE
CS is asserted 5 additional baud-times before start of transmission
6 : SIX
CS is asserted 6 additional baud-times before start of transmission
7 : SEVEN
CS is asserted 7 additional baud-times before start of transmission
End of enumeration elements list.
CSHOLD : Chip Select Hold
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : ZERO
CS is de-asserted half or 1 baud-time after the end of transmission depending on CLKPHASE equal to 1 or 0 respectively
1 : ONE
CS is de-asserted 1 additional baud-time after the end of transmission
2 : TWO
CS is de-asserted 2 additional baud-times after the end of transmission
3 : THREE
CS is de-asserted 3 additional baud-times after the end of transmission
4 : FOUR
CS is de-asserted 4 additional baud-times after the end of transmission
5 : FIVE
CS is de-asserted 5 additional baud-times after the end of transmission
6 : SIX
CS is de-asserted 6 additional baud-times after the end of transmission
7 : SEVEN
CS is de-asserted 7 additional baud-times after the end of transmission
End of enumeration elements list.
ICS : Inter-Character Spacing
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : ZERO
There is no space between charcters
1 : ONE
Create a space of 1 baud-times between frames
2 : TWO
Create a space of 2 baud-times between frames
3 : THREE
Create a space of 3 baud-times between frames
4 : FOUR
Create a space of 4 baud-times between frames
5 : FIVE
Create a space of 5 baud-times between frames
6 : SIX
Create a space of 6 baud-times between frames
7 : SEVEN
Create a space of 7 baud-times between frames
End of enumeration elements list.
SETUPWINDOW : Setup Window
bits : 16 - 19 (4 bit)
access : read-write
No Description
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STARTFRAME : Start Frame
bits : 0 - 8 (9 bit)
access : read-write
No Description
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGFRAME : Signal Frame Value
bits : 0 - 8 (9 bit)
access : read-write
No Description
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Fractional Clock Divider
bits : 3 - 22 (20 bit)
access : read-write
No Description
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXTEN : Receive Trigger Enable
bits : 0 - 0 (1 bit)
access : read-write
TXTEN : Transmit Trigger Enable
bits : 1 - 1 (1 bit)
access : read-write
AUTOTXTEN : AUTOTX Trigger Enable
bits : 2 - 2 (1 bit)
access : read-write
No Description
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXEN : Receiver Enable
bits : 0 - 0 (1 bit)
access : write-only
RXDIS : Receiver Disable
bits : 1 - 1 (1 bit)
access : write-only
TXEN : Transmitter Enable
bits : 2 - 2 (1 bit)
access : write-only
TXDIS : Transmitter Disable
bits : 3 - 3 (1 bit)
access : write-only
RXBLOCKEN : Receiver Block Enable
bits : 4 - 4 (1 bit)
access : write-only
RXBLOCKDIS : Receiver Block Disable
bits : 5 - 5 (1 bit)
access : write-only
TXTRIEN : Transmitter Tristate Enable
bits : 6 - 6 (1 bit)
access : write-only
TXTRIDIS : Transmitter Tristate Disable
bits : 7 - 7 (1 bit)
access : write-only
CLEARTX : Clear TX FIFO
bits : 8 - 8 (1 bit)
access : write-only
No Description
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data and Control bits
bits : 0 - 15 (16 bit)
access : read-only
No Description
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Module enable
bits : 0 - 0 (1 bit)
access : read-write
DISABLING : Disablement busy status
bits : 1 - 1 (1 bit)
access : read-only
No Description
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATAP : RX Data Peek
bits : 0 - 15 (16 bit)
access : read-only
No Description
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data and Control bits
bits : 0 - 15 (16 bit)
access : write-only
No Description
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXENS : Receiver Enable Status
bits : 0 - 0 (1 bit)
access : read-only
TXENS : Transmitter Enable Status
bits : 1 - 1 (1 bit)
access : read-only
RXBLOCK : Block Incoming Data
bits : 3 - 3 (1 bit)
access : read-only
TXTRI : Transmitter Tristated
bits : 4 - 4 (1 bit)
access : read-only
TXC : TX Complete
bits : 5 - 5 (1 bit)
access : read-only
TXFL : TX FIFO Level
bits : 6 - 6 (1 bit)
access : read-only
RXFL : RX FIFO Level
bits : 7 - 7 (1 bit)
access : read-only
RXFULL : RX FIFO Full
bits : 8 - 8 (1 bit)
access : read-only
RXIDLE : RX Idle
bits : 12 - 12 (1 bit)
access : read-only
TXIDLE : TX Idle
bits : 13 - 13 (1 bit)
access : read-only
TXFCNT : Valid entries in TX FIFO
bits : 16 - 20 (5 bit)
access : read-only
AUTOBAUDDONE : Auto Baud Rate Detection Completed
bits : 24 - 24 (1 bit)
access : read-only
CLEARTXBUSY : TX FIFO Clear Busy
bits : 25 - 25 (1 bit)
access : read-only
No Description
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXC : TX Complete Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write
TXFL : TX FIFO Level Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write
RXFL : RX FIFO Level Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-write
RXFULL : RX FIFO Full Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-write
RXOF : RX FIFO Overflow Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-write
RXUF : RX FIFO Underflow Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-write
TXOF : TX FIFO Overflow Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-write
TXUF : TX FIFO Underflow Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-write
PERR : Parity Error Interrupt Flag
bits : 8 - 8 (1 bit)
access : read-write
FERR : Framing Error Interrupt Flag
bits : 9 - 9 (1 bit)
access : read-write
MPAF : Multi-Processor Address Frame Interrupt
bits : 10 - 10 (1 bit)
access : read-write
LOADERR : Load Error Interrupt Flag
bits : 11 - 11 (1 bit)
access : read-write
CCF : Collision Check Fail Interrupt Flag
bits : 12 - 12 (1 bit)
access : read-write
TXIDLE : TX Idle Interrupt Flag
bits : 13 - 13 (1 bit)
access : read-write
STARTF : Start Frame Interrupt Flag
bits : 18 - 18 (1 bit)
access : read-write
SIGF : Signal Frame Interrupt Flag
bits : 19 - 19 (1 bit)
access : read-write
AUTOBAUDDONE : Auto Baud Complete Interrupt Flag
bits : 24 - 24 (1 bit)
access : read-write
RXTO : RX Timeout Interrupt Flag
bits : 25 - 25 (1 bit)
access : read-write
No Description
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXC : TX Complete IEN
bits : 0 - 0 (1 bit)
access : read-write
TXFL : TX FIFO Level IEN
bits : 1 - 1 (1 bit)
access : read-write
RXFL : RX FIFO Level IEN
bits : 2 - 2 (1 bit)
access : read-write
RXFULL : RX FIFO Full IEN
bits : 3 - 3 (1 bit)
access : read-write
RXOF : RX FIFO Overflow IEN
bits : 4 - 4 (1 bit)
access : read-write
RXUF : RX FIFO Underflow IEN
bits : 5 - 5 (1 bit)
access : read-write
TXOF : TX FIFO Overflow IEN
bits : 6 - 6 (1 bit)
access : read-write
TXUF : TX FIFO Underflow IEN
bits : 7 - 7 (1 bit)
access : read-write
PERR : Parity Error IEN
bits : 8 - 8 (1 bit)
access : read-write
FERR : Framing Error IEN
bits : 9 - 9 (1 bit)
access : read-write
MPAF : Multi-Processor Addr Frame IEN
bits : 10 - 10 (1 bit)
access : read-write
LOADERR : Load Error IEN
bits : 11 - 11 (1 bit)
access : read-write
CCF : Collision Check Fail IEN
bits : 12 - 12 (1 bit)
access : read-write
TXIDLE : TX IDLE IEN
bits : 13 - 13 (1 bit)
access : read-write
STARTF : Start Frame IEN
bits : 18 - 18 (1 bit)
access : read-write
SIGF : Signal Frame IEN
bits : 19 - 19 (1 bit)
access : read-write
AUTOBAUDDONE : Auto Baud Complete IEN
bits : 24 - 24 (1 bit)
access : read-write
RXTO : RX Timeout IEN
bits : 25 - 25 (1 bit)
access : read-write
No Description
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DIV : SYNCBUSY for DIV in CLKDIV
bits : 0 - 0 (1 bit)
access : read-only
RXTEN : SYNCBUSY for RXTEN in TRIGCTRL
bits : 1 - 1 (1 bit)
access : read-only
TXTEN : SYNCBUSY for TXTEN in TRIGCTRL
bits : 2 - 2 (1 bit)
access : read-only
RXEN : SYNCBUSY for RXEN in CMD
bits : 3 - 3 (1 bit)
access : read-only
RXDIS : SYNCBUSY for RXDIS in CMD
bits : 4 - 4 (1 bit)
access : read-only
TXEN : SYNCBUSY for TXEN in CMD
bits : 5 - 5 (1 bit)
access : read-only
TXDIS : SYNCBUSY for TXDIS in CMD
bits : 6 - 6 (1 bit)
access : read-only
RXBLOCKEN : SYNCBUSY for RXBLOCKEN in CMD
bits : 7 - 7 (1 bit)
access : read-only
RXBLOCKDIS : SYNCBUSY for RXBLOCKDIS in CMD
bits : 8 - 8 (1 bit)
access : read-only
TXTRIEN : SYNCBUSY for TXTRIEN in CMD
bits : 9 - 9 (1 bit)
access : read-only
TXTRIDIS : SYNCBUSY in TXTRIDIS in CMD
bits : 10 - 10 (1 bit)
access : read-only
AUTOTXTEN : SYNCBUSY for AUTOTXTEN in TRIGCTRL
bits : 11 - 11 (1 bit)
access : read-only
No Description
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNC : Synchronous Mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ASYNC
The USART operates in asynchronous mode
1 : SYNC
The USART operates in synchronous mode
End of enumeration elements list.
LOOPBK : Loopback Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The receiver is connected to and receives data from UARTn_RX
1 : ENABLE
The receiver is connected to and receives data from UARTn_TX
End of enumeration elements list.
CCEN : Collision Check Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Collision check is disabled
1 : ENABLE
Collision check is enabled. The receiver must be enabled for the check to be performed
End of enumeration elements list.
MPM : Multi-Processor Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The 9th bit of incoming frames has no special function
1 : ENABLE
An incoming frame with the 9th bit equal to MPAB will be loaded into the RX FIFO regardless of RXBLOCK and will result in the MPAB interrupt flag being set
End of enumeration elements list.
MPAB : Multi-Processor Address-Bit
bits : 4 - 4 (1 bit)
access : read-write
OVS : Oversampling
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
0 : X16
16X oversampling
1 : X8
8X oversampling
2 : X6
6X oversampling
3 : X4
4X oversampling
4 : DISABLE
Disable oversampling (for LF operation)
End of enumeration elements list.
MSBF : Most Significant Bit First
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Data is sent with the least significant bit first
1 : ENABLE
Data is sent with the most significant bit first
End of enumeration elements list.
RXINV : Receiver Input Invert
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Input is passed directly to the receiver
1 : ENABLE
Input is inverted before it is passed to the receiver
End of enumeration elements list.
TXINV : Transmitter output Invert
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Output from the transmitter is passed unchanged to UARTn_TX
1 : ENABLE
Output from the transmitter is inverted before it is passed to UARTn_TX
End of enumeration elements list.
AUTOTRI : Automatic TX Tristate
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The output on UARTn_TX when the transmitter is idle is defined by TXINV
1 : ENABLE
UARTn_TX is tristated whenever the transmitter is idle
End of enumeration elements list.
SKIPPERRF : Skip Parity Error Frames
bits : 20 - 20 (1 bit)
access : read-write
ERRSDMA : Halt DMA Read On Error
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Framing and parity errors have no effect on DMA requests from the EUSART
1 : ENABLE
DMA requests from the EUSART are blocked while the PERR or FERR interrupt flags are set
End of enumeration elements list.
ERRSRX : Disable RX On Error
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Framing and parity errors have no effect on receiver
1 : ENABLE
Framing and parity errors disable the receiver
End of enumeration elements list.
ERRSTX : Disable TX On Error
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Received framing and parity errors have no effect on transmitter
1 : ENABLE
Received framing and parity errors disable the transmitter
End of enumeration elements list.
MVDIS : Majority Vote Disable
bits : 30 - 30 (1 bit)
access : read-write
AUTOBAUDEN : AUTOBAUD detection enable
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGHALT : Debug halt
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Continue normal EUSART operation even if core is halted
1 : ENABLE
If core is halted, receive one frame and then halt reception by deactivating RTS. Next frame reception happens when the core is unhalted during single stepping.
End of enumeration elements list.
CTSINV : Clear-to-send Invert Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The CTS pin is active low
1 : ENABLE
The CTS pin is active high
End of enumeration elements list.
CTSEN : Clear-to-send Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Ignore CTS
1 : ENABLE
Stop transmitting when CTS is inactive
End of enumeration elements list.
RTSINV : Request-to-send Invert Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The RTS pin is active low
1 : ENABLE
The RTS pin is active high
End of enumeration elements list.
RXTIMEOUT : RX Timeout
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : DISABLED
1 : ONEFRAME
2 : TWOFRAMES
3 : THREEFRAMES
4 : FOURFRAMES
5 : FIVEFRAMES
6 : SIXFRAMES
7 : SEVENFRAMES
End of enumeration elements list.
SFUBRX : Start Frame Unblock Receiver
bits : 11 - 11 (1 bit)
access : read-write
RXPRSEN : PRS RX Enable
bits : 15 - 15 (1 bit)
access : read-write
TXFIW : TX FIFO Interrupt Watermark
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : ONEFRAME
TXFL status flag and IF are set when the TX FIFO has space for at least one more frame.
1 : TWOFRAMES
TXFL status flag and IF are set when the TX FIFO has space for at least two more frames.
2 : THREEFRAMES
TXFL status flag and IF are set when the TX FIFO has space for at least three more frames.
3 : FOURFRAMES
TXFL status flag and IF are set when the TX FIFO has space for at least four more frames.
4 : FIVEFRAMES
TXFL status flag and IF are set when the TX FIFO has space for at least five more frames.
5 : SIXFRAMES
TXFL status flag and IF are set when the TX FIFO has space for at least six more frames.
6 : SEVENFRAMES
TXFL status flag and IF are set when the TX FIFO has space for at least seven more frames.
7 : EIGHTFRAMES
TXFL status flag and IF are set when the TX FIFO has space for at least eight more frames.
8 : NINEFRAMES
TXFL status flag and IF are set when the TX FIFO has space for at least nine more frames.
9 : TENFRAMES
TXFL status flag and IF are set when the TX FIFO has space for at least ten more frames.
10 : ELEVENFRAMES
TXFL status flag and IF are set when the TX FIFO has space for at least eleven more frames.
11 : TWELVEFRAMES
TXFL status flag and IF are set when the TX FIFO has space for at least twelve more frames.
12 : THIRTEENFRAMES
TXFL status flag and IF are set when the TX FIFO has space for at least thriteen more frames.
13 : FOURTEENFRAMES
TXFL status flag and IF are set when the TX FIFO has space for at least fourteen more frames.
14 : FIFTEENFRAMES
TXFL status flag and IF are set when the TX FIFO has space for at least fifteen more frames.
15 : SIXTEENFRAMES
TXFL status flag and IF are set when the TX FIFO has space for at least sixteen more frames.
End of enumeration elements list.
RTSRXFW : Request-to-send RX FIFO Watermark
bits : 22 - 25 (4 bit)
access : read-write
Enumeration:
0 : ONEFRAME
RTS is set if there is space for at least one more frame in the RX FIFO.
1 : TWOFRAMES
RTS is set if there is space for at least two more frames in the RX FIFO.
2 : THREEFRAMES
RTS is set if there is space for at least three more frames in the RX FIFO.
3 : FOURFRAMES
RTS is set if there is space for four more frames in the RX FIFO.
4 : FIVEFRAMES
RTS is set if there is space for five more frames in the RX FIFO.
5 : SIXFRAMES
RTS is set if there is space for six more frames in the RX FIFO.
6 : SEVENFRAMES
RTS is set if there is space for seven more frames in the RX FIFO.
7 : EIGHTFRAMES
RTS is set if there is space for eight more frames in the RX FIFO.
8 : NINEFRAMES
RTS is set if there is space for nine more frames in the RX FIFO.
9 : TENFRAMES
RTS is set if there is space for ten more frames in the RX FIFO.
10 : ELEVENFRAMES
RTS is set if there is space for eleven more frames in the RX FIFO.
11 : TWELVEFRAMES
RTS is set if there is space for twelve more frames in the RX FIFO.
12 : THIRTEENFRAMES
RTS is set if there is space for thirteen more frames in the RX FIFO.
13 : FOURTEENFRAMES
RTS is set if there is space for fourteen more frames in the RX FIFO.
14 : FIFTEENFRAMES
RTS is set if there is space for fifteen more frames in the RX FIFO.
15 : SIXTEENFRAMES
RTS is set if there is space for sixteen more frames in the RX FIFO.
End of enumeration elements list.
RXFIW : RX FIFO Interrupt Watermark
bits : 27 - 30 (4 bit)
access : read-write
Enumeration:
0 : ONEFRAME
RXFL status flag and IF are set when the RX FIFO has at least one frame in it.
1 : TWOFRAMES
RXFL status flag and IF are set when the RX FIFO has at least two frames in it.
2 : THREEFRAMES
RXFL status flag and IF are set when the RX FIFO has at least three frames in it.
3 : FOURFRAMES
RXFL status flag and IF are set when the RX FIFO has at least four frames in it.
4 : FIVEFRAMES
RXFL status flag and IF are set when the RX FIFO has at least five frames in it.
5 : SIXFRAMES
RXFL status flag and IF are set when the RX FIFO has at least six frames in it.
6 : SEVENFRAMES
RXFL status flag and IF are set when the RX FIFO has at least seven frames in it.
7 : EIGHTFRAMES
RXFL status flag and IF are set when the RX FIFO has at least eight frames in it.
8 : NINEFRAMES
RXFL status flag and IF are set when the RX FIFO has at least nine frames in it.
9 : TENFRAMES
RXFL status flag and IF are set when the RX FIFO has at least ten frames in it.
10 : ELEVENFRAMES
RXFL status flag and IF are set when the RX FIFO has at least eleven frames in it.
11 : TWELVEFRAMES
RXFL status flag and IF are set when the RX FIFO has at least twelve frames in it.
12 : THIRTEENFRAMES
RXFL status flag and IF are set when the RX FIFO has at least thriteen frames in it.
13 : FOURTEENFRAMES
RXFL status flag and IF are set when the RX FIFO has at least fourteen frames in it.
14 : FIFTEENFRAMES
RXFL status flag and IF are set when the RX FIFO has at least fifteen frames in it.
15 : SIXTEENFRAMES
RXFL status flag and IF are set when the RX FIFO has at least sixteen frames in it.
End of enumeration elements list.
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