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SERCOM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection :

Registers

CTRLA

INTENCLR

INTENSET

INTFLAG

STATUS

SYNCBUSY

ADDR

DATA

DBGCTRL

CTRLB

BAUD

BAUD_FRAC_MODE

BAUD_FRACFP_MODE

BAUD_USARTFP_MODE

RXPL


CTRLA

SPI Control A
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLA CTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE MODE RUNSTDBY IBON SAMPR PINOUT DOPO TXPO SDAHOLD DIPO RXPO MEXTTOEN SAMPA SEXTTOEN SPEED FORM SCLSM INACTOUT CPHA CMODE CPOL LOWTOUTEN DORD

SWRST : Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Enable
bits : 1 - 1 (1 bit)

MODE : Operating Mode
bits : 2 - 4 (3 bit)

Enumeration: MODESelect

0x0 : USART_EXT_CLK

USART mode with external clock

0x1 : USART_INT_CLK

USART mode with internal clock

0x2 : SPI_SLAVE

SPI mode with external clock

0x3 : SPI_MASTER

SPI mode with internal clock

0x4 : I2C_SLAVE

I2C mode with external clock

0x5 : I2C_MASTER

I2C mode with internal clock

End of enumeration elements list.

RUNSTDBY : Run during Standby
bits : 7 - 7 (1 bit)

IBON : Immediate Buffer Overflow Notification
bits : 8 - 8 (1 bit)

SAMPR : Sample
bits : 13 - 15 (3 bit)

PINOUT : Pin Usage
bits : 16 - 16 (1 bit)

DOPO : Data Out Pinout
bits : 16 - 17 (2 bit)

TXPO : Transmit Data Pinout
bits : 16 - 17 (2 bit)

SDAHOLD : SDA Hold Time
bits : 20 - 21 (2 bit)

DIPO : Data In Pinout
bits : 20 - 21 (2 bit)

RXPO : Receive Data Pinout
bits : 20 - 21 (2 bit)

MEXTTOEN : Master SCL Low Extend Timeout
bits : 22 - 22 (1 bit)

SAMPA : Sample Adjustment
bits : 22 - 23 (2 bit)

SEXTTOEN : Slave SCL Low Extend Timeout
bits : 23 - 23 (1 bit)

SPEED : Transfer Speed
bits : 24 - 25 (2 bit)

FORM : Frame Format
bits : 24 - 27 (4 bit)

SCLSM : SCL Clock Stretch Mode
bits : 27 - 27 (1 bit)

INACTOUT : Inactive Time-Out
bits : 28 - 29 (2 bit)

CPHA : Clock Phase
bits : 28 - 28 (1 bit)

CMODE : Communication Mode
bits : 28 - 28 (1 bit)

CPOL : Clock Polarity
bits : 29 - 29 (1 bit)

LOWTOUTEN : SCL Low Timeout Enable
bits : 30 - 30 (1 bit)

DORD : Data Order
bits : 30 - 30 (1 bit)


INTENCLR

SPI Interrupt Enable Clear
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MB PREC DRE SB AMATCH TXC DRDY RXC SSL RXS CTSIC RXBRK ERROR

MB : Master On Bus Interrupt Disable
bits : 0 - 0 (1 bit)

PREC : Stop Received Interrupt Disable
bits : 0 - 0 (1 bit)

DRE : Data Register Empty Interrupt Disable
bits : 0 - 0 (1 bit)

SB : Slave On Bus Interrupt Disable
bits : 1 - 1 (1 bit)

AMATCH : Address Match Interrupt Disable
bits : 1 - 1 (1 bit)

TXC : Transmit Complete Interrupt Disable
bits : 1 - 1 (1 bit)

DRDY : Data Interrupt Disable
bits : 2 - 2 (1 bit)

RXC : Receive Complete Interrupt Disable
bits : 2 - 2 (1 bit)

SSL : Slave Select Low Interrupt Disable
bits : 3 - 3 (1 bit)

RXS : Receive Start Interrupt Disable
bits : 3 - 3 (1 bit)

CTSIC : Clear To Send Input Change Interrupt Disable
bits : 4 - 4 (1 bit)

RXBRK : Break Received Interrupt Disable
bits : 5 - 5 (1 bit)

ERROR : Combined Error Interrupt Disable
bits : 7 - 7 (1 bit)


INTENSET

SPI Interrupt Enable Set
address_offset : 0x16 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MB PREC DRE SB AMATCH TXC DRDY RXC SSL RXS CTSIC RXBRK ERROR

MB : Master On Bus Interrupt Enable
bits : 0 - 0 (1 bit)

PREC : Stop Received Interrupt Enable
bits : 0 - 0 (1 bit)

DRE : Data Register Empty Interrupt Enable
bits : 0 - 0 (1 bit)

SB : Slave On Bus Interrupt Enable
bits : 1 - 1 (1 bit)

AMATCH : Address Match Interrupt Enable
bits : 1 - 1 (1 bit)

TXC : Transmit Complete Interrupt Enable
bits : 1 - 1 (1 bit)

DRDY : Data Interrupt Enable
bits : 2 - 2 (1 bit)

RXC : Receive Complete Interrupt Enable
bits : 2 - 2 (1 bit)

SSL : Slave Select Low Interrupt Enable
bits : 3 - 3 (1 bit)

RXS : Receive Start Interrupt Enable
bits : 3 - 3 (1 bit)

CTSIC : Clear To Send Input Change Interrupt Enable
bits : 4 - 4 (1 bit)

RXBRK : Break Received Interrupt Enable
bits : 5 - 5 (1 bit)

ERROR : Combined Error Interrupt Enable
bits : 7 - 7 (1 bit)


INTFLAG

SPI Interrupt Flag Status and Clear
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAG INTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MB PREC DRE SB AMATCH TXC DRDY RXC SSL RXS CTSIC RXBRK ERROR

MB : Master On Bus Interrupt
bits : 0 - 0 (1 bit)

PREC : Stop Received Interrupt
bits : 0 - 0 (1 bit)

DRE : Data Register Empty Interrupt
bits : 0 - 0 (1 bit)
access : read-only

SB : Slave On Bus Interrupt
bits : 1 - 1 (1 bit)

AMATCH : Address Match Interrupt
bits : 1 - 1 (1 bit)

TXC : Transmit Complete Interrupt
bits : 1 - 1 (1 bit)

DRDY : Data Interrupt
bits : 2 - 2 (1 bit)

RXC : Receive Complete Interrupt
bits : 2 - 2 (1 bit)
access : read-only

SSL : Slave Select Low Interrupt Flag
bits : 3 - 3 (1 bit)

RXS : Receive Start Interrupt
bits : 3 - 3 (1 bit)
access : write-only

CTSIC : Clear To Send Input Change Interrupt
bits : 4 - 4 (1 bit)

RXBRK : Break Received Interrupt
bits : 5 - 5 (1 bit)

ERROR : Combined Error Interrupt
bits : 7 - 7 (1 bit)


STATUS

SPI Status
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSERR PERR ARBLOST FERR RXNACK BUFOVF DIR CTS BUSSTATE SR ISF COLL LOWTOUT CLKHOLD MEXTTOUT SEXTTOUT LENERR HS

BUSERR : Bus Error
bits : 0 - 0 (1 bit)

PERR : Parity Error
bits : 0 - 0 (1 bit)

ARBLOST : Arbitration Lost
bits : 1 - 1 (1 bit)

FERR : Frame Error
bits : 1 - 1 (1 bit)

RXNACK : Received Not Acknowledge
bits : 2 - 2 (1 bit)
access : read-only

BUFOVF : Buffer Overflow
bits : 2 - 2 (1 bit)

DIR : Read/Write Direction
bits : 3 - 3 (1 bit)
access : read-only

CTS : Clear To Send
bits : 3 - 3 (1 bit)
access : read-only

BUSSTATE : Bus State
bits : 4 - 5 (2 bit)

SR : Repeated Start
bits : 4 - 4 (1 bit)
access : read-only

ISF : Inconsistent Sync Field
bits : 4 - 4 (1 bit)

COLL : Collision Detected
bits : 5 - 5 (1 bit)

LOWTOUT : SCL Low Timeout
bits : 6 - 6 (1 bit)

CLKHOLD : Clock Hold
bits : 7 - 7 (1 bit)
access : read-only

MEXTTOUT : Master SCL Low Extend Timeout
bits : 8 - 8 (1 bit)

SEXTTOUT : Slave SCL Low Extend Timeout
bits : 9 - 9 (1 bit)

LENERR : Length Error
bits : 10 - 10 (1 bit)

HS : High Speed
bits : 10 - 10 (1 bit)


SYNCBUSY

SPI Synchronization Busy
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYNCBUSY SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE SYSOP CTRLB

SWRST : Software Reset Synchronization Busy
bits : 0 - 0 (1 bit)
access : read-only

ENABLE : SERCOM Enable Synchronization Busy
bits : 1 - 1 (1 bit)
access : read-only

SYSOP : System Operation Synchronization Busy
bits : 2 - 2 (1 bit)
access : read-only

CTRLB : CTRLB Synchronization Busy
bits : 2 - 2 (1 bit)
access : read-only


ADDR

I2CS Address
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR GENCEN LENEN HS TENBITEN LEN ADDRMASK

ADDR : Address Value
bits : 0 - 7 (8 bit)

GENCEN : General Call Address Enable
bits : 0 - 0 (1 bit)

LENEN : Length Enable
bits : 13 - 13 (1 bit)

HS : High Speed Mode
bits : 14 - 14 (1 bit)

TENBITEN : Ten Bit Addressing Enable
bits : 15 - 15 (1 bit)

LEN : Length
bits : 16 - 23 (8 bit)

ADDRMASK : Address Mask
bits : 16 - 23 (8 bit)


DATA

SPI Data
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data Value
bits : 0 - 8 (9 bit)


DBGCTRL

SPI Debug Control
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGCTRL DBGCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DBGSTOP

DBGSTOP : Debug Mode
bits : 0 - 0 (1 bit)


CTRLB

SPI Control B
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLB CTRLB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHSIZE PLOADEN SBMODE SMEN COLDEN QCEN GCMD SSDE SFDE AACKEN ENC MSSEN PMODE AMODE CMD TXEN RXEN ACKACT

CHSIZE : Character Size
bits : 0 - 2 (3 bit)

PLOADEN : Data Preload Enable
bits : 6 - 6 (1 bit)

SBMODE : Stop Bit Mode
bits : 6 - 6 (1 bit)

SMEN : Smart Mode Enable
bits : 8 - 8 (1 bit)

COLDEN : Collision Detection Enable
bits : 8 - 8 (1 bit)

QCEN : Quick Command Enable
bits : 9 - 9 (1 bit)

GCMD : PMBus Group Command
bits : 9 - 9 (1 bit)

SSDE : Slave Select Low Detect Enable
bits : 9 - 9 (1 bit)

SFDE : Start of Frame Detection Enable
bits : 9 - 9 (1 bit)

AACKEN : Automatic Address Acknowledge
bits : 10 - 10 (1 bit)

ENC : Encoding Format
bits : 10 - 10 (1 bit)

MSSEN : Master Slave Select Enable
bits : 13 - 13 (1 bit)

PMODE : Parity Mode
bits : 13 - 13 (1 bit)

AMODE : Address Mode
bits : 14 - 15 (2 bit)

CMD : Command
bits : 16 - 17 (2 bit)
access : write-only

TXEN : Transmitter Enable
bits : 16 - 16 (1 bit)

RXEN : Receiver Enable
bits : 17 - 17 (1 bit)

ACKACT : Acknowledge Action
bits : 18 - 18 (1 bit)


BAUD

SPI Baud Rate
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BAUD BAUD read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BAUD BAUDLOW HSBAUD HSBAUDLOW

BAUD : Baud Rate Value
bits : 0 - 15 (16 bit)

BAUDLOW : Baud Rate Value Low
bits : 8 - 15 (8 bit)

HSBAUD : High Speed Baud Rate Value
bits : 16 - 23 (8 bit)

HSBAUDLOW : High Speed Baud Rate Value Low
bits : 24 - 31 (8 bit)


BAUD_FRAC_MODE

USART Baud Rate
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : BAUD
reset_Mask : 0x0

BAUD_FRAC_MODE BAUD_FRAC_MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BAUD FP

BAUD : Baud Rate Value
bits : 0 - 12 (13 bit)

FP : Fractional Part
bits : 13 - 15 (3 bit)


BAUD_FRACFP_MODE

USART Baud Rate
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : BAUD
reset_Mask : 0x0

BAUD_FRACFP_MODE BAUD_FRACFP_MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BAUD FP

BAUD : Baud Rate Value
bits : 0 - 12 (13 bit)

FP : Fractional Part
bits : 13 - 15 (3 bit)


BAUD_USARTFP_MODE

USART Baud Rate
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : BAUD
reset_Mask : 0x0

BAUD_USARTFP_MODE BAUD_USARTFP_MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BAUD

BAUD : Baud Rate Value
bits : 0 - 15 (16 bit)


RXPL

USART Receive Pulse Length
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXPL RXPL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RXPL

RXPL : Receive Pulse Length
bits : 0 - 7 (8 bit)



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