\n
address_offset : 0x0 Bytes (0x0)
size : 0x39 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x0 Bytes (0x0)
size : 0x39 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x0 Bytes (0x0)
size : 0x39 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x0 Bytes (0x0)
size : 0x39 byte (0x0)
mem_usage : registers
protection :
Control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Sleep Mode
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDLE : Idle Mode Configuration
bits : 0 - 1 (2 bit)
Enumeration: IDLESelect
0 : CPU
The CPU clock domain is stopped
1 : AHB
The CPU and AHB clock domains are stopped
2 : APB
The CPU, AHB and APB clock domains are stopped
End of enumeration elements list.
AHB Mask
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HPB0_ : HPB0 AHB Clock Mask
bits : 0 - 0 (1 bit)
HPB1_ : HPB1 AHB Clock Mask
bits : 1 - 1 (1 bit)
HPB2_ : HPB2 AHB Clock Mask
bits : 2 - 2 (1 bit)
DSU_ : DSU AHB Clock Mask
bits : 3 - 3 (1 bit)
NVMCTRL_ : NVMCTRL AHB Clock Mask
bits : 4 - 4 (1 bit)
DMAC_ : DMAC AHB Clock Mask
bits : 5 - 5 (1 bit)
USB_ : USB AHB Clock Mask
bits : 6 - 6 (1 bit)
APBA Mask
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PAC0_ : PAC0 APB Clock Enable
bits : 0 - 0 (1 bit)
PM_ : PM APB Clock Enable
bits : 1 - 1 (1 bit)
SYSCTRL_ : SYSCTRL APB Clock Enable
bits : 2 - 2 (1 bit)
GCLK_ : GCLK APB Clock Enable
bits : 3 - 3 (1 bit)
WDT_ : WDT APB Clock Enable
bits : 4 - 4 (1 bit)
RTC_ : RTC APB Clock Enable
bits : 5 - 5 (1 bit)
EIC_ : EIC APB Clock Enable
bits : 6 - 6 (1 bit)
APBB Mask
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PAC1_ : PAC1 APB Clock Enable
bits : 0 - 0 (1 bit)
DSU_ : DSU APB Clock Enable
bits : 1 - 1 (1 bit)
NVMCTRL_ : NVMCTRL APB Clock Enable
bits : 2 - 2 (1 bit)
PORT_ : PORT APB Clock Enable
bits : 3 - 3 (1 bit)
DMAC_ : DMAC APB Clock Enable
bits : 4 - 4 (1 bit)
USB_ : USB APB Clock Enable
bits : 5 - 5 (1 bit)
HMATRIX_ : HMATRIX APB Clock Enable
bits : 6 - 6 (1 bit)
External Reset Controller
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETDIS : External Reset Disable
bits : 0 - 0 (1 bit)
APBC Mask
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PAC2_ : PAC2 APB Clock Enable
bits : 0 - 0 (1 bit)
EVSYS_ : EVSYS APB Clock Enable
bits : 1 - 1 (1 bit)
SERCOM0_ : SERCOM0 APB Clock Enable
bits : 2 - 2 (1 bit)
SERCOM1_ : SERCOM1 APB Clock Enable
bits : 3 - 3 (1 bit)
SERCOM2_ : SERCOM2 APB Clock Enable
bits : 4 - 4 (1 bit)
SERCOM3_ : SERCOM3 APB Clock Enable
bits : 5 - 5 (1 bit)
SERCOM4_ : SERCOM4 APB Clock Enable
bits : 6 - 6 (1 bit)
SERCOM5_ : SERCOM5 APB Clock Enable
bits : 7 - 7 (1 bit)
TCC0_ : TCC0 APB Clock Enable
bits : 8 - 8 (1 bit)
TCC1_ : TCC1 APB Clock Enable
bits : 9 - 9 (1 bit)
TCC2_ : TCC2 APB Clock Enable
bits : 10 - 10 (1 bit)
TC3_ : TC3 APB Clock Enable
bits : 11 - 11 (1 bit)
TC4_ : TC4 APB Clock Enable
bits : 12 - 12 (1 bit)
TC5_ : TC5 APB Clock Enable
bits : 13 - 13 (1 bit)
TC6_ : TC6 APB Clock Enable
bits : 14 - 14 (1 bit)
TC7_ : TC7 APB Clock Enable
bits : 15 - 15 (1 bit)
ADC_ : ADC APB Clock Enable
bits : 16 - 16 (1 bit)
AC_ : AC APB Clock Enable
bits : 17 - 17 (1 bit)
DAC_ : DAC APB Clock Enable
bits : 18 - 18 (1 bit)
PTC_ : PTC APB Clock Enable
bits : 19 - 19 (1 bit)
I2S_ : I2S APB Clock Enable
bits : 20 - 20 (1 bit)
Interrupt Enable Clear
address_offset : 0x34 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKRDY : Clock Ready Interrupt Enable
bits : 0 - 0 (1 bit)
Interrupt Enable Set
address_offset : 0x35 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKRDY : Clock Ready Interrupt Enable
bits : 0 - 0 (1 bit)
Interrupt Flag Status and Clear
address_offset : 0x36 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKRDY : Clock Ready
bits : 0 - 0 (1 bit)
Reset Cause
address_offset : 0x38 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
POR : Power On Reset
bits : 0 - 0 (1 bit)
BOD12 : Brown Out 12 Detector Reset
bits : 1 - 1 (1 bit)
BOD33 : Brown Out 33 Detector Reset
bits : 2 - 2 (1 bit)
EXT : External Reset
bits : 4 - 4 (1 bit)
WDT : Watchdog Reset
bits : 5 - 5 (1 bit)
SYST : System Reset Request
bits : 6 - 6 (1 bit)
CPU Clock Select
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPUDIV : CPU Prescaler Selection
bits : 0 - 2 (3 bit)
Enumeration: CPUDIVSelect
0 : DIV1
Divide by 1
1 : DIV2
Divide by 2
2 : DIV4
Divide by 4
3 : DIV8
Divide by 8
4 : DIV16
Divide by 16
5 : DIV32
Divide by 32
6 : DIV64
Divide by 64
7 : DIV128
Divide by 128
End of enumeration elements list.
APBA Clock Select
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APBADIV : APBA Prescaler Selection
bits : 0 - 2 (3 bit)
Enumeration: APBADIVSelect
0 : DIV1
Divide by 1
1 : DIV2
Divide by 2
2 : DIV4
Divide by 4
3 : DIV8
Divide by 8
4 : DIV16
Divide by 16
5 : DIV32
Divide by 32
6 : DIV64
Divide by 64
7 : DIV128
Divide by 128
End of enumeration elements list.
APBB Clock Select
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APBBDIV : APBB Prescaler Selection
bits : 0 - 2 (3 bit)
Enumeration: APBBDIVSelect
0 : DIV1
Divide by 1
1 : DIV2
Divide by 2
2 : DIV4
Divide by 4
3 : DIV8
Divide by 8
4 : DIV16
Divide by 16
5 : DIV32
Divide by 32
6 : DIV64
Divide by 64
7 : DIV128
Divide by 128
End of enumeration elements list.
APBC Clock Select
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APBCDIV : APBC Prescaler Selection
bits : 0 - 2 (3 bit)
Enumeration: APBCDIVSelect
0 : DIV1
Divide by 1
1 : DIV2
Divide by 2
2 : DIV4
Divide by 4
3 : DIV8
Divide by 8
4 : DIV16
Divide by 16
5 : DIV32
Divide by 32
6 : DIV64
Divide by 64
7 : DIV128
Divide by 128
End of enumeration elements list.
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