Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x0 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x0 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x0 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection :
Control A
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Enable
bits : 1 - 1 (1 bit)
RESOLUTION : Enhanced Resolution
bits : 5 - 6 (2 bit)
Enumeration: RESOLUTIONSelect
0 : NONE
Dithering is disabled
1 : DITH4
Dithering is done every 16 PWM frames
2 : DITH5
Dithering is done every 32 PWM frames
3 : DITH6
Dithering is done every 64 PWM frames
End of enumeration elements list.
PRESCALER : Prescaler
bits : 8 - 10 (3 bit)
Enumeration: PRESCALERSelect
0 : DIV1
No division
1 : DIV2
Divide by 2
2 : DIV4
Divide by 4
3 : DIV8
Divide by 8
4 : DIV16
Divide by 16
5 : DIV64
Divide by 64
6 : DIV256
Divide by 256
7 : DIV1024
Divide by 1024
End of enumeration elements list.
RUNSTDBY : Run in Standby
bits : 11 - 11 (1 bit)
PRESCSYNC : Prescaler and Counter Synchronization Selection
bits : 12 - 13 (2 bit)
Enumeration: PRESCSYNCSelect
0 : GCLK
Reload or reset counter on next GCLK
1 : PRESC
Reload or reset counter on next prescaler clock
2 : RESYNC
Reload or reset counter on next GCLK and reset prescaler counter
End of enumeration elements list.
ALOCK : Auto Lock
bits : 14 - 14 (1 bit)
CPTEN0 : Capture Channel 0 Enable
bits : 24 - 24 (1 bit)
CPTEN1 : Capture Channel 1 Enable
bits : 25 - 25 (1 bit)
CPTEN2 : Capture Channel 2 Enable
bits : 26 - 26 (1 bit)
CPTEN3 : Capture Channel 3 Enable
bits : 27 - 27 (1 bit)
Recoverable Fault B Configuration
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC : Fault B Source
bits : 0 - 1 (2 bit)
Enumeration: SRCSelect
0 : DISABLE
Fault input disabled
1 : ENABLE
MCEx (x=0,1) event input
2 : INVERT
Inverted MCEx (x=0,1) event input
3 : ALTFAULT
Alternate fault (A or B) state at the end of the previous period
End of enumeration elements list.
KEEP : Fault B Keeper
bits : 3 - 3 (1 bit)
QUAL : Fault B Qualification
bits : 4 - 4 (1 bit)
BLANK : Fault B Blanking Mode
bits : 5 - 6 (2 bit)
Enumeration: BLANKSelect
0 : NONE
No blanking applied
1 : RISE
Blanking applied from rising edge of the output waveform
2 : FALL
Blanking applied from falling edge of the output waveform
3 : BOTH
Blanking applied from each toggle of the output waveform
End of enumeration elements list.
RESTART : Fault B Restart
bits : 7 - 7 (1 bit)
HALT : Fault B Halt Mode
bits : 8 - 9 (2 bit)
Enumeration: HALTSelect
0 : DISABLE
Halt action disabled
1 : HW
Hardware halt action
2 : SW
Software halt action
3 : NR
Non-recoverable fault
End of enumeration elements list.
CHSEL : Fault B Capture Channel
bits : 10 - 11 (2 bit)
Enumeration: CHSELSelect
0 : CC0
Capture value stored in channel 0
1 : CC1
Capture value stored in channel 1
2 : CC2
Capture value stored in channel 2
3 : CC3
Capture value stored in channel 3
End of enumeration elements list.
CAPTURE : Fault B Capture Action
bits : 12 - 14 (3 bit)
Enumeration: CAPTURESelect
0 : DISABLE
No capture
1 : CAPT
Capture on fault
2 : CAPTMIN
Minimum capture
3 : CAPTMAX
Maximum capture
4 : LOCMIN
Minimum local detection
5 : LOCMAX
Maximum local detection
6 : DERIV0
Minimum and maximum local detection
End of enumeration elements list.
BLANKVAL : Fault B Blanking Time
bits : 16 - 23 (8 bit)
FILTERVAL : Fault B Filter Value
bits : 24 - 27 (4 bit)
Waveform Extension Configuration
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OTMX : Output Matrix
bits : 0 - 1 (2 bit)
DTIEN0 : Dead-time Insertion Generator 0 Enable
bits : 8 - 8 (1 bit)
DTIEN1 : Dead-time Insertion Generator 1 Enable
bits : 9 - 9 (1 bit)
DTIEN2 : Dead-time Insertion Generator 2 Enable
bits : 10 - 10 (1 bit)
DTIEN3 : Dead-time Insertion Generator 3 Enable
bits : 11 - 11 (1 bit)
DTLS : Dead-time Low Side Outputs Value
bits : 16 - 23 (8 bit)
DTHS : Dead-time High Side Outputs Value
bits : 24 - 31 (8 bit)
Driver Control
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NRE0 : Non-Recoverable State 0 Output Enable
bits : 0 - 0 (1 bit)
NRE1 : Non-Recoverable State 1 Output Enable
bits : 1 - 1 (1 bit)
NRE2 : Non-Recoverable State 2 Output Enable
bits : 2 - 2 (1 bit)
NRE3 : Non-Recoverable State 3 Output Enable
bits : 3 - 3 (1 bit)
NRE4 : Non-Recoverable State 4 Output Enable
bits : 4 - 4 (1 bit)
NRE5 : Non-Recoverable State 5 Output Enable
bits : 5 - 5 (1 bit)
NRE6 : Non-Recoverable State 6 Output Enable
bits : 6 - 6 (1 bit)
NRE7 : Non-Recoverable State 7 Output Enable
bits : 7 - 7 (1 bit)
NRV0 : Non-Recoverable State 0 Output Value
bits : 8 - 8 (1 bit)
NRV1 : Non-Recoverable State 1 Output Value
bits : 9 - 9 (1 bit)
NRV2 : Non-Recoverable State 2 Output Value
bits : 10 - 10 (1 bit)
NRV3 : Non-Recoverable State 3 Output Value
bits : 11 - 11 (1 bit)
NRV4 : Non-Recoverable State 4 Output Value
bits : 12 - 12 (1 bit)
NRV5 : Non-Recoverable State 5 Output Value
bits : 13 - 13 (1 bit)
NRV6 : Non-Recoverable State 6 Output Value
bits : 14 - 14 (1 bit)
NRV7 : Non-Recoverable State 7 Output Value
bits : 15 - 15 (1 bit)
INVEN0 : Output Waveform 0 Inversion
bits : 16 - 16 (1 bit)
INVEN1 : Output Waveform 1 Inversion
bits : 17 - 17 (1 bit)
INVEN2 : Output Waveform 2 Inversion
bits : 18 - 18 (1 bit)
INVEN3 : Output Waveform 3 Inversion
bits : 19 - 19 (1 bit)
INVEN4 : Output Waveform 4 Inversion
bits : 20 - 20 (1 bit)
INVEN5 : Output Waveform 5 Inversion
bits : 21 - 21 (1 bit)
INVEN6 : Output Waveform 6 Inversion
bits : 22 - 22 (1 bit)
INVEN7 : Output Waveform 7 Inversion
bits : 23 - 23 (1 bit)
FILTERVAL0 : Non-Recoverable Fault Input 0 Filter Value
bits : 24 - 27 (4 bit)
FILTERVAL1 : Non-Recoverable Fault Input 1 Filter Value
bits : 28 - 31 (4 bit)
Debug Control
address_offset : 0x1E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGRUN : Debug Running Mode
bits : 0 - 0 (1 bit)
FDDBD : Fault Detection on Debug Break Detection
bits : 2 - 2 (1 bit)
Event Control
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT0 : Timer/counter Input Event0 Action
bits : 0 - 2 (3 bit)
Enumeration: EVACT0Select
0 : OFF
Event action disabled
1 : RETRIGGER
Start, restart or re-trigger counter on event
2 : COUNTEV
Count on event
3 : START
Start counter on event
4 : INC
Increment counter on event
5 : COUNT
Count on active state of asynchronous event
7 : FAULT
Non-recoverable fault
End of enumeration elements list.
EVACT1 : Timer/counter Input Event1 Action
bits : 3 - 5 (3 bit)
Enumeration: EVACT1Select
0 : OFF
Event action disabled
1 : RETRIGGER
Re-trigger counter on event
2 : DIR
Direction control
3 : STOP
Stop counter on event
4 : DEC
Decrement counter on event
5 : PPW
Period capture value in CC0 register, pulse width capture value in CC1 register
6 : PWP
Period capture value in CC1 register, pulse width capture value in CC0 register
7 : FAULT
Non-recoverable fault
End of enumeration elements list.
CNTSEL : Timer/counter Output Event Mode
bits : 6 - 7 (2 bit)
Enumeration: CNTSELSelect
0 : START
An interrupt/event is generated when a new counter cycle starts
1 : END
An interrupt/event is generated when a counter cycle ends
2 : BETWEEN
An interrupt/event is generated when a counter cycle ends, except for the first and last cycles
3 : BOUNDARY
An interrupt/event is generated when a new counter cycle starts or a counter cycle ends
End of enumeration elements list.
OVFEO : Overflow/Underflow Output Event Enable
bits : 8 - 8 (1 bit)
TRGEO : Retrigger Output Event Enable
bits : 9 - 9 (1 bit)
CNTEO : Timer/counter Output Event Enable
bits : 10 - 10 (1 bit)
TCINV0 : Inverted Event 0 Input Enable
bits : 12 - 12 (1 bit)
TCINV1 : Inverted Event 1 Input Enable
bits : 13 - 13 (1 bit)
TCEI0 : Timer/counter Event 0 Input Enable
bits : 14 - 14 (1 bit)
TCEI1 : Timer/counter Event 1 Input Enable
bits : 15 - 15 (1 bit)
MCEI0 : Match or Capture Channel 0 Event Input Enable
bits : 16 - 16 (1 bit)
MCEI1 : Match or Capture Channel 1 Event Input Enable
bits : 17 - 17 (1 bit)
MCEI2 : Match or Capture Channel 2 Event Input Enable
bits : 18 - 18 (1 bit)
MCEI3 : Match or Capture Channel 3 Event Input Enable
bits : 19 - 19 (1 bit)
MCEO0 : Match or Capture Channel 0 Event Output Enable
bits : 24 - 24 (1 bit)
MCEO1 : Match or Capture Channel 1 Event Output Enable
bits : 25 - 25 (1 bit)
MCEO2 : Match or Capture Channel 2 Event Output Enable
bits : 26 - 26 (1 bit)
MCEO3 : Match or Capture Channel 3 Event Output Enable
bits : 27 - 27 (1 bit)
Interrupt Enable Clear
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : Overflow Interrupt Enable
bits : 0 - 0 (1 bit)
TRG : Retrigger Interrupt Enable
bits : 1 - 1 (1 bit)
CNT : Counter Interrupt Enable
bits : 2 - 2 (1 bit)
ERR : Error Interrupt Enable
bits : 3 - 3 (1 bit)
DFS : Non-Recoverable Debug Fault Interrupt Enable
bits : 11 - 11 (1 bit)
FAULTA : Recoverable Fault A Interrupt Enable
bits : 12 - 12 (1 bit)
FAULTB : Recoverable Fault B Interrupt Enable
bits : 13 - 13 (1 bit)
FAULT0 : Non-Recoverable Fault 0 Interrupt Enable
bits : 14 - 14 (1 bit)
FAULT1 : Non-Recoverable Fault 1 Interrupt Enable
bits : 15 - 15 (1 bit)
MC0 : Match or Capture Channel 0 Interrupt Enable
bits : 16 - 16 (1 bit)
MC1 : Match or Capture Channel 1 Interrupt Enable
bits : 17 - 17 (1 bit)
MC2 : Match or Capture Channel 2 Interrupt Enable
bits : 18 - 18 (1 bit)
MC3 : Match or Capture Channel 3 Interrupt Enable
bits : 19 - 19 (1 bit)
Interrupt Enable Set
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : Overflow Interrupt Enable
bits : 0 - 0 (1 bit)
TRG : Retrigger Interrupt Enable
bits : 1 - 1 (1 bit)
CNT : Counter Interrupt Enable
bits : 2 - 2 (1 bit)
ERR : Error Interrupt Enable
bits : 3 - 3 (1 bit)
DFS : Non-Recoverable Debug Fault Interrupt Enable
bits : 11 - 11 (1 bit)
FAULTA : Recoverable Fault A Interrupt Enable
bits : 12 - 12 (1 bit)
FAULTB : Recoverable Fault B Interrupt Enable
bits : 13 - 13 (1 bit)
FAULT0 : Non-Recoverable Fault 0 Interrupt Enable
bits : 14 - 14 (1 bit)
FAULT1 : Non-Recoverable Fault 1 Interrupt Enable
bits : 15 - 15 (1 bit)
MC0 : Match or Capture Channel 0 Interrupt Enable
bits : 16 - 16 (1 bit)
MC1 : Match or Capture Channel 1 Interrupt Enable
bits : 17 - 17 (1 bit)
MC2 : Match or Capture Channel 2 Interrupt Enable
bits : 18 - 18 (1 bit)
MC3 : Match or Capture Channel 3 Interrupt Enable
bits : 19 - 19 (1 bit)
Interrupt Flag Status and Clear
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : Overflow
bits : 0 - 0 (1 bit)
TRG : Retrigger
bits : 1 - 1 (1 bit)
CNT : Counter
bits : 2 - 2 (1 bit)
ERR : Error
bits : 3 - 3 (1 bit)
DFS : Non-Recoverable Debug Fault
bits : 11 - 11 (1 bit)
FAULTA : Recoverable Fault A
bits : 12 - 12 (1 bit)
FAULTB : Recoverable Fault B
bits : 13 - 13 (1 bit)
FAULT0 : Non-Recoverable Fault 0
bits : 14 - 14 (1 bit)
FAULT1 : Non-Recoverable Fault 1
bits : 15 - 15 (1 bit)
MC0 : Match or Capture 0
bits : 16 - 16 (1 bit)
MC1 : Match or Capture 1
bits : 17 - 17 (1 bit)
MC2 : Match or Capture 2
bits : 18 - 18 (1 bit)
MC3 : Match or Capture 3
bits : 19 - 19 (1 bit)
Status
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOP : Stop
bits : 0 - 0 (1 bit)
access : read-only
IDX : Ramp
bits : 1 - 1 (1 bit)
access : read-only
DFS : Non-Recoverable Debug Fault State
bits : 3 - 3 (1 bit)
SLAVE : Slave
bits : 4 - 4 (1 bit)
access : read-only
PATTBV : Pattern Buffer Valid
bits : 5 - 5 (1 bit)
WAVEBV : Wave Buffer Valid
bits : 6 - 6 (1 bit)
PERBV : Period Buffer Valid
bits : 7 - 7 (1 bit)
FAULTAIN : Recoverable Fault A Input
bits : 8 - 8 (1 bit)
access : read-only
FAULTBIN : Recoverable Fault B Input
bits : 9 - 9 (1 bit)
access : read-only
FAULT0IN : Non-Recoverable Fault0 Input
bits : 10 - 10 (1 bit)
access : read-only
FAULT1IN : Non-Recoverable Fault1 Input
bits : 11 - 11 (1 bit)
access : read-only
FAULTA : Recoverable Fault A State
bits : 12 - 12 (1 bit)
FAULTB : Recoverable Fault B State
bits : 13 - 13 (1 bit)
FAULT0 : Non-Recoverable Fault 0 State
bits : 14 - 14 (1 bit)
FAULT1 : Non-Recoverable Fault 1 State
bits : 15 - 15 (1 bit)
CCBV0 : Compare Channel 0 Buffer Valid
bits : 16 - 16 (1 bit)
CCBV1 : Compare Channel 1 Buffer Valid
bits : 17 - 17 (1 bit)
CCBV2 : Compare Channel 2 Buffer Valid
bits : 18 - 18 (1 bit)
CCBV3 : Compare Channel 3 Buffer Valid
bits : 19 - 19 (1 bit)
CMP0 : Compare Channel 0 Value
bits : 24 - 24 (1 bit)
access : read-only
CMP1 : Compare Channel 1 Value
bits : 25 - 25 (1 bit)
access : read-only
CMP2 : Compare Channel 2 Value
bits : 26 - 26 (1 bit)
access : read-only
CMP3 : Compare Channel 3 Value
bits : 27 - 27 (1 bit)
access : read-only
Count
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Counter Value
bits : 0 - 23 (24 bit)
Count
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : COUNT
reset_Mask : 0x0
COUNT : Counter Value
bits : 4 - 23 (20 bit)
Count
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : COUNT
reset_Mask : 0x0
COUNT : Counter Value
bits : 5 - 23 (19 bit)
Count
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : COUNT
reset_Mask : 0x0
COUNT : Counter Value
bits : 6 - 23 (18 bit)
Count
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : COUNT
reset_Mask : 0x0
COUNT : Counter Value
bits : 4 - 23 (20 bit)
Count
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : COUNT
reset_Mask : 0x0
COUNT : Counter Value
bits : 5 - 23 (19 bit)
Count
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : COUNT
reset_Mask : 0x0
COUNT : Counter Value
bits : 6 - 23 (18 bit)
Pattern
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PGE0 : Pattern Generator 0 Output Enable
bits : 0 - 0 (1 bit)
PGE1 : Pattern Generator 1 Output Enable
bits : 1 - 1 (1 bit)
PGE2 : Pattern Generator 2 Output Enable
bits : 2 - 2 (1 bit)
PGE3 : Pattern Generator 3 Output Enable
bits : 3 - 3 (1 bit)
PGE4 : Pattern Generator 4 Output Enable
bits : 4 - 4 (1 bit)
PGE5 : Pattern Generator 5 Output Enable
bits : 5 - 5 (1 bit)
PGE6 : Pattern Generator 6 Output Enable
bits : 6 - 6 (1 bit)
PGE7 : Pattern Generator 7 Output Enable
bits : 7 - 7 (1 bit)
PGV0 : Pattern Generator 0 Output Value
bits : 8 - 8 (1 bit)
PGV1 : Pattern Generator 1 Output Value
bits : 9 - 9 (1 bit)
PGV2 : Pattern Generator 2 Output Value
bits : 10 - 10 (1 bit)
PGV3 : Pattern Generator 3 Output Value
bits : 11 - 11 (1 bit)
PGV4 : Pattern Generator 4 Output Value
bits : 12 - 12 (1 bit)
PGV5 : Pattern Generator 5 Output Value
bits : 13 - 13 (1 bit)
PGV6 : Pattern Generator 6 Output Value
bits : 14 - 14 (1 bit)
PGV7 : Pattern Generator 7 Output Value
bits : 15 - 15 (1 bit)
Waveform Control
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAVEGEN : Waveform Generation
bits : 0 - 2 (3 bit)
Enumeration: WAVEGENSelect
0 : NFRQ
Normal frequency
1 : MFRQ
Match frequency
2 : NPWM
Normal PWM
4 : DSCRITICAL
Dual-slope critical
5 : DSBOTTOM
Dual-slope with interrupt/event condition when COUNT reaches ZERO
6 : DSBOTH
Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP
7 : DSTOP
Dual-slope with interrupt/event condition when COUNT reaches TOP
End of enumeration elements list.
RAMP : Ramp Mode
bits : 4 - 5 (2 bit)
Enumeration: RAMPSelect
0 : RAMP1
RAMP1 operation
1 : RAMP2A
Alternative RAMP2 operation
2 : RAMP2
RAMP2 operation
End of enumeration elements list.
CIPEREN : Circular period Enable
bits : 7 - 7 (1 bit)
CICCEN0 : Circular Channel 0 Enable
bits : 8 - 8 (1 bit)
CICCEN1 : Circular Channel 1 Enable
bits : 9 - 9 (1 bit)
CICCEN2 : Circular Channel 2 Enable
bits : 10 - 10 (1 bit)
CICCEN3 : Circular Channel 3 Enable
bits : 11 - 11 (1 bit)
POL0 : Channel 0 Polarity
bits : 16 - 16 (1 bit)
POL1 : Channel 1 Polarity
bits : 17 - 17 (1 bit)
POL2 : Channel 2 Polarity
bits : 18 - 18 (1 bit)
POL3 : Channel 3 Polarity
bits : 19 - 19 (1 bit)
SWAP0 : Swap DTI Output Pair 0
bits : 24 - 24 (1 bit)
SWAP1 : Swap DTI Output Pair 1
bits : 25 - 25 (1 bit)
SWAP2 : Swap DTI Output Pair 2
bits : 26 - 26 (1 bit)
SWAP3 : Swap DTI Output Pair 3
bits : 27 - 27 (1 bit)
Control B Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Counter Direction
bits : 0 - 0 (1 bit)
LUPD : Lock Update
bits : 1 - 1 (1 bit)
ONESHOT : One-Shot
bits : 2 - 2 (1 bit)
IDXCMD : Ramp Index Command
bits : 3 - 4 (2 bit)
Enumeration: IDXCMDSelect
0 : DISABLE
Command disabled: Index toggles between cycles A and B
1 : SET
Set index: cycle B will be forced in the next cycle
2 : CLEAR
Clear index: cycle A will be forced in the next cycle
3 : HOLD
Hold index: the next cycle will be the same as the current cycle
End of enumeration elements list.
CMD : TCC Command
bits : 5 - 7 (3 bit)
Enumeration: CMDSelect
0 : NONE
No action
1 : RETRIGGER
Clear start, restart or retrigger
2 : STOP
Force stop
3 : UPDATE
Force update of double buffered registers
4 : READSYNC
Force COUNT read synchronization
End of enumeration elements list.
Period
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PER : Period Value
bits : 0 - 23 (24 bit)
Period
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PER
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 3 (4 bit)
PER : Period Value
bits : 4 - 23 (20 bit)
Period
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PER
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 4 (5 bit)
PER : Period Value
bits : 5 - 23 (19 bit)
Period
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PER
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 5 (6 bit)
PER : Period Value
bits : 6 - 23 (18 bit)
Period
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PER
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 3 (4 bit)
PER : Period Value
bits : 4 - 23 (20 bit)
Period
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PER
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 4 (5 bit)
PER : Period Value
bits : 5 - 23 (19 bit)
Period
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PER
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 5 (6 bit)
PER : Period Value
bits : 6 - 23 (18 bit)
Compare and Capture
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Channel Compare/Capture Value
bits : 0 - 23 (24 bit)
Compare and Capture
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC%s
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 3 (4 bit)
CC : Channel Compare/Capture Value
bits : 4 - 23 (20 bit)
Compare and Capture
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC%s
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 4 (5 bit)
CC : Channel Compare/Capture Value
bits : 5 - 23 (19 bit)
Compare and Capture
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC%s
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 5 (6 bit)
CC : Channel Compare/Capture Value
bits : 6 - 23 (18 bit)
Compare and Capture
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC[%s]
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 3 (4 bit)
CC : Channel Compare/Capture Value
bits : 4 - 23 (20 bit)
Compare and Capture
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC[%s]
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 4 (5 bit)
CC : Channel Compare/Capture Value
bits : 5 - 23 (19 bit)
Compare and Capture
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC[%s]
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 5 (6 bit)
CC : Channel Compare/Capture Value
bits : 6 - 23 (18 bit)
Compare and Capture
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Channel Compare/Capture Value
bits : 0 - 23 (24 bit)
Compare and Capture
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC%s
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 3 (4 bit)
CC : Channel Compare/Capture Value
bits : 4 - 23 (20 bit)
Compare and Capture
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC%s
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 4 (5 bit)
CC : Channel Compare/Capture Value
bits : 5 - 23 (19 bit)
Compare and Capture
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC%s
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 5 (6 bit)
CC : Channel Compare/Capture Value
bits : 6 - 23 (18 bit)
Compare and Capture
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC[%s]
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 3 (4 bit)
CC : Channel Compare/Capture Value
bits : 4 - 23 (20 bit)
Compare and Capture
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC[%s]
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 4 (5 bit)
CC : Channel Compare/Capture Value
bits : 5 - 23 (19 bit)
Compare and Capture
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC[%s]
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 5 (6 bit)
CC : Channel Compare/Capture Value
bits : 6 - 23 (18 bit)
Compare and Capture
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Channel Compare/Capture Value
bits : 0 - 23 (24 bit)
Compare and Capture
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC%s
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 3 (4 bit)
CC : Channel Compare/Capture Value
bits : 4 - 23 (20 bit)
Compare and Capture
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC%s
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 4 (5 bit)
CC : Channel Compare/Capture Value
bits : 5 - 23 (19 bit)
Compare and Capture
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC%s
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 5 (6 bit)
CC : Channel Compare/Capture Value
bits : 6 - 23 (18 bit)
Compare and Capture
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC[%s]
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 3 (4 bit)
CC : Channel Compare/Capture Value
bits : 4 - 23 (20 bit)
Compare and Capture
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC[%s]
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 4 (5 bit)
CC : Channel Compare/Capture Value
bits : 5 - 23 (19 bit)
Compare and Capture
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC[%s]
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 5 (6 bit)
CC : Channel Compare/Capture Value
bits : 6 - 23 (18 bit)
Control B Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Counter Direction
bits : 0 - 0 (1 bit)
LUPD : Lock Update
bits : 1 - 1 (1 bit)
ONESHOT : One-Shot
bits : 2 - 2 (1 bit)
IDXCMD : Ramp Index Command
bits : 3 - 4 (2 bit)
Enumeration: IDXCMDSelect
0 : DISABLE
Command disabled: Index toggles between cycles A and B
1 : SET
Set index: cycle B will be forced in the next cycle
2 : CLEAR
Clear index: cycle A will be forced in the next cycle
3 : HOLD
Hold index: the next cycle will be the same as the current cycle
End of enumeration elements list.
CMD : TCC Command
bits : 5 - 7 (3 bit)
Enumeration: CMDSelect
0 : NONE
No action
1 : RETRIGGER
Clear start, restart or retrigger
2 : STOP
Force stop
3 : UPDATE
Force update of double buffered registers
4 : READSYNC
Force COUNT read synchronization
End of enumeration elements list.
Compare and Capture
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Channel Compare/Capture Value
bits : 0 - 23 (24 bit)
Compare and Capture
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC%s
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 3 (4 bit)
CC : Channel Compare/Capture Value
bits : 4 - 23 (20 bit)
Compare and Capture
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC%s
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 4 (5 bit)
CC : Channel Compare/Capture Value
bits : 5 - 23 (19 bit)
Compare and Capture
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC%s
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 5 (6 bit)
CC : Channel Compare/Capture Value
bits : 6 - 23 (18 bit)
Compare and Capture
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC[%s]
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 3 (4 bit)
CC : Channel Compare/Capture Value
bits : 4 - 23 (20 bit)
Compare and Capture
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC[%s]
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 4 (5 bit)
CC : Channel Compare/Capture Value
bits : 5 - 23 (19 bit)
Compare and Capture
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC[%s]
reset_Mask : 0x0
DITHERCY : Dithering Cycle Number
bits : 0 - 5 (6 bit)
CC : Channel Compare/Capture Value
bits : 6 - 23 (18 bit)
Pattern Buffer
address_offset : 0x64 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PGEB0 : Pattern Generator 0 Output Enable Buffer
bits : 0 - 0 (1 bit)
PGEB1 : Pattern Generator 1 Output Enable Buffer
bits : 1 - 1 (1 bit)
PGEB2 : Pattern Generator 2 Output Enable Buffer
bits : 2 - 2 (1 bit)
PGEB3 : Pattern Generator 3 Output Enable Buffer
bits : 3 - 3 (1 bit)
PGEB4 : Pattern Generator 4 Output Enable Buffer
bits : 4 - 4 (1 bit)
PGEB5 : Pattern Generator 5 Output Enable Buffer
bits : 5 - 5 (1 bit)
PGEB6 : Pattern Generator 6 Output Enable Buffer
bits : 6 - 6 (1 bit)
PGEB7 : Pattern Generator 7 Output Enable Buffer
bits : 7 - 7 (1 bit)
PGVB0 : Pattern Generator 0 Output Enable
bits : 8 - 8 (1 bit)
PGVB1 : Pattern Generator 1 Output Enable
bits : 9 - 9 (1 bit)
PGVB2 : Pattern Generator 2 Output Enable
bits : 10 - 10 (1 bit)
PGVB3 : Pattern Generator 3 Output Enable
bits : 11 - 11 (1 bit)
PGVB4 : Pattern Generator 4 Output Enable
bits : 12 - 12 (1 bit)
PGVB5 : Pattern Generator 5 Output Enable
bits : 13 - 13 (1 bit)
PGVB6 : Pattern Generator 6 Output Enable
bits : 14 - 14 (1 bit)
PGVB7 : Pattern Generator 7 Output Enable
bits : 15 - 15 (1 bit)
Waveform Control Buffer
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAVEGENB : Waveform Generation Buffer
bits : 0 - 2 (3 bit)
Enumeration: WAVEGENBSelect
0 : NFRQ
Normal frequency
1 : MFRQ
Match frequency
2 : NPWM
Normal PWM
4 : DSCRITICAL
Dual-slope critical
5 : DSBOTTOM
Dual-slope with interrupt/event condition when COUNT reaches ZERO
6 : DSBOTH
Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP
7 : DSTOP
Dual-slope with interrupt/event condition when COUNT reaches TOP
End of enumeration elements list.
RAMPB : Ramp Mode Buffer
bits : 4 - 5 (2 bit)
Enumeration: RAMPBSelect
0 : RAMP1
RAMP1 operation
1 : RAMP2A
Alternative RAMP2 operation
2 : RAMP2
RAMP2 operation
End of enumeration elements list.
CIPERENB : Circular Period Enable Buffer
bits : 7 - 7 (1 bit)
CICCENB0 : Circular Channel 0 Enable Buffer
bits : 8 - 8 (1 bit)
CICCENB1 : Circular Channel 1 Enable Buffer
bits : 9 - 9 (1 bit)
CICCENB2 : Circular Channel 2 Enable Buffer
bits : 10 - 10 (1 bit)
CICCENB3 : Circular Channel 3 Enable Buffer
bits : 11 - 11 (1 bit)
POLB0 : Channel 0 Polarity Buffer
bits : 16 - 16 (1 bit)
POLB1 : Channel 1 Polarity Buffer
bits : 17 - 17 (1 bit)
POLB2 : Channel 2 Polarity Buffer
bits : 18 - 18 (1 bit)
POLB3 : Channel 3 Polarity Buffer
bits : 19 - 19 (1 bit)
SWAPB0 : Swap DTI Output Pair 0 Buffer
bits : 24 - 24 (1 bit)
SWAPB1 : Swap DTI Output Pair 1 Buffer
bits : 25 - 25 (1 bit)
SWAPB2 : Swap DTI Output Pair 2 Buffer
bits : 26 - 26 (1 bit)
SWAPB3 : Swap DTI Output Pair 3 Buffer
bits : 27 - 27 (1 bit)
Period Buffer
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERB : Period Buffer Value
bits : 0 - 23 (24 bit)
Period Buffer
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PERB
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 3 (4 bit)
PERB : Period Buffer Value
bits : 4 - 23 (20 bit)
Period Buffer
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PERB
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 4 (5 bit)
PERB : Period Buffer Value
bits : 5 - 23 (19 bit)
Period Buffer
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PERB
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 5 (6 bit)
PERB : Period Buffer Value
bits : 6 - 23 (18 bit)
Period Buffer
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PERB
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 3 (4 bit)
PERB : Period Buffer Value
bits : 4 - 23 (20 bit)
Period Buffer
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PERB
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 4 (5 bit)
PERB : Period Buffer Value
bits : 5 - 23 (19 bit)
Period Buffer
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PERB
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 5 (6 bit)
PERB : Period Buffer Value
bits : 6 - 23 (18 bit)
Compare and Capture Buffer
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCB : Channel Compare/Capture Buffer Value
bits : 0 - 23 (24 bit)
Compare and Capture Buffer
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCB%s
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 3 (4 bit)
CCB : Channel Compare/Capture Buffer Value
bits : 4 - 23 (20 bit)
Compare and Capture Buffer
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCB%s
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 4 (5 bit)
CCB : Channel Compare/Capture Buffer Value
bits : 5 - 23 (19 bit)
Compare and Capture Buffer
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCB%s
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 5 (6 bit)
CCB : Channel Compare/Capture Buffer Value
bits : 6 - 23 (18 bit)
Compare and Capture Buffer
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCB[%s]
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 3 (4 bit)
CCB : Channel Compare/Capture Buffer Value
bits : 4 - 23 (20 bit)
Compare and Capture Buffer
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCB[%s]
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 4 (5 bit)
CCB : Channel Compare/Capture Buffer Value
bits : 5 - 23 (19 bit)
Compare and Capture Buffer
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCB[%s]
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 5 (6 bit)
CCB : Channel Compare/Capture Buffer Value
bits : 6 - 23 (18 bit)
Compare and Capture Buffer
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCB : Channel Compare/Capture Buffer Value
bits : 0 - 23 (24 bit)
Compare and Capture Buffer
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCB%s
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 3 (4 bit)
CCB : Channel Compare/Capture Buffer Value
bits : 4 - 23 (20 bit)
Compare and Capture Buffer
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCB%s
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 4 (5 bit)
CCB : Channel Compare/Capture Buffer Value
bits : 5 - 23 (19 bit)
Compare and Capture Buffer
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCB%s
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 5 (6 bit)
CCB : Channel Compare/Capture Buffer Value
bits : 6 - 23 (18 bit)
Compare and Capture Buffer
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCB[%s]
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 3 (4 bit)
CCB : Channel Compare/Capture Buffer Value
bits : 4 - 23 (20 bit)
Compare and Capture Buffer
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCB[%s]
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 4 (5 bit)
CCB : Channel Compare/Capture Buffer Value
bits : 5 - 23 (19 bit)
Compare and Capture Buffer
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCB[%s]
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 5 (6 bit)
CCB : Channel Compare/Capture Buffer Value
bits : 6 - 23 (18 bit)
Compare and Capture Buffer
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCB : Channel Compare/Capture Buffer Value
bits : 0 - 23 (24 bit)
Compare and Capture Buffer
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCB%s
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 3 (4 bit)
CCB : Channel Compare/Capture Buffer Value
bits : 4 - 23 (20 bit)
Compare and Capture Buffer
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCB%s
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 4 (5 bit)
CCB : Channel Compare/Capture Buffer Value
bits : 5 - 23 (19 bit)
Compare and Capture Buffer
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCB%s
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 5 (6 bit)
CCB : Channel Compare/Capture Buffer Value
bits : 6 - 23 (18 bit)
Compare and Capture Buffer
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCB[%s]
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 3 (4 bit)
CCB : Channel Compare/Capture Buffer Value
bits : 4 - 23 (20 bit)
Compare and Capture Buffer
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCB[%s]
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 4 (5 bit)
CCB : Channel Compare/Capture Buffer Value
bits : 5 - 23 (19 bit)
Compare and Capture Buffer
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCB[%s]
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 5 (6 bit)
CCB : Channel Compare/Capture Buffer Value
bits : 6 - 23 (18 bit)
Compare and Capture Buffer
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCB : Channel Compare/Capture Buffer Value
bits : 0 - 23 (24 bit)
Compare and Capture Buffer
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCB%s
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 3 (4 bit)
CCB : Channel Compare/Capture Buffer Value
bits : 4 - 23 (20 bit)
Compare and Capture Buffer
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCB%s
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 4 (5 bit)
CCB : Channel Compare/Capture Buffer Value
bits : 5 - 23 (19 bit)
Compare and Capture Buffer
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCB%s
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 5 (6 bit)
CCB : Channel Compare/Capture Buffer Value
bits : 6 - 23 (18 bit)
Compare and Capture Buffer
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCB[%s]
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 3 (4 bit)
CCB : Channel Compare/Capture Buffer Value
bits : 4 - 23 (20 bit)
Compare and Capture Buffer
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCB[%s]
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 4 (5 bit)
CCB : Channel Compare/Capture Buffer Value
bits : 5 - 23 (19 bit)
Compare and Capture Buffer
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCB[%s]
reset_Mask : 0x0
DITHERCYB : Dithering Buffer Cycle Number
bits : 0 - 5 (6 bit)
CCB : Channel Compare/Capture Buffer Value
bits : 6 - 23 (18 bit)
Synchronization Busy
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Swrst Busy
bits : 0 - 0 (1 bit)
ENABLE : Enable Busy
bits : 1 - 1 (1 bit)
CTRLB : Ctrlb Busy
bits : 2 - 2 (1 bit)
STATUS : Status Busy
bits : 3 - 3 (1 bit)
COUNT : Count Busy
bits : 4 - 4 (1 bit)
PATT : Pattern Busy
bits : 5 - 5 (1 bit)
WAVE : Wave Busy
bits : 6 - 6 (1 bit)
PER : Period busy
bits : 7 - 7 (1 bit)
CC0 : Compare Channel 0 Busy
bits : 8 - 8 (1 bit)
CC1 : Compare Channel 1 Busy
bits : 9 - 9 (1 bit)
CC2 : Compare Channel 2 Busy
bits : 10 - 10 (1 bit)
CC3 : Compare Channel 3 Busy
bits : 11 - 11 (1 bit)
PATTB : Pattern Buffer Busy
bits : 16 - 16 (1 bit)
WAVEB : Wave Buffer Busy
bits : 17 - 17 (1 bit)
PERB : Period Buffer Busy
bits : 18 - 18 (1 bit)
CCB0 : Compare Channel Buffer 0 Busy
bits : 19 - 19 (1 bit)
CCB1 : Compare Channel Buffer 1 Busy
bits : 20 - 20 (1 bit)
CCB2 : Compare Channel Buffer 2 Busy
bits : 21 - 21 (1 bit)
CCB3 : Compare Channel Buffer 3 Busy
bits : 22 - 22 (1 bit)
Recoverable Fault A Configuration
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC : Fault A Source
bits : 0 - 1 (2 bit)
Enumeration: SRCSelect
0 : DISABLE
Fault input disabled
1 : ENABLE
MCEx (x=0,1) event input
2 : INVERT
Inverted MCEx (x=0,1) event input
3 : ALTFAULT
Alternate fault (A or B) state at the end of the previous period
End of enumeration elements list.
KEEP : Fault A Keeper
bits : 3 - 3 (1 bit)
QUAL : Fault A Qualification
bits : 4 - 4 (1 bit)
BLANK : Fault A Blanking Mode
bits : 5 - 6 (2 bit)
Enumeration: BLANKSelect
0 : NONE
No blanking applied
1 : RISE
Blanking applied from rising edge of the output waveform
2 : FALL
Blanking applied from falling edge of the output waveform
3 : BOTH
Blanking applied from each toggle of the output waveform
End of enumeration elements list.
RESTART : Fault A Restart
bits : 7 - 7 (1 bit)
HALT : Fault A Halt Mode
bits : 8 - 9 (2 bit)
Enumeration: HALTSelect
0 : DISABLE
Halt action disabled
1 : HW
Hardware halt action
2 : SW
Software halt action
3 : NR
Non-recoverable fault
End of enumeration elements list.
CHSEL : Fault A Capture Channel
bits : 10 - 11 (2 bit)
Enumeration: CHSELSelect
0 : CC0
Capture value stored in channel 0
1 : CC1
Capture value stored in channel 1
2 : CC2
Capture value stored in channel 2
3 : CC3
Capture value stored in channel 3
End of enumeration elements list.
CAPTURE : Fault A Capture Action
bits : 12 - 14 (3 bit)
Enumeration: CAPTURESelect
0 : DISABLE
No capture
1 : CAPT
Capture on fault
2 : CAPTMIN
Minimum capture
3 : CAPTMAX
Maximum capture
4 : LOCMIN
Minimum local detection
5 : LOCMAX
Maximum local detection
6 : DERIV0
Minimum and maximum local detection
End of enumeration elements list.
BLANKVAL : Fault A Blanking Time
bits : 16 - 23 (8 bit)
FILTERVAL : Fault A Filter Value
bits : 24 - 27 (4 bit)
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