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PM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection :

Registers

CTRL

SLEEP

AHBMASK

APBAMASK

APBBMASK

EXTCTRL

APBCMASK

INTENCLR

INTENSET

INTFLAG

RCAUSE

CPUSEL

APBASEL

APBBSEL

APBCSEL


CTRL

Control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

SLEEP

Sleep Mode
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLEEP SLEEP read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IDLE

IDLE : Idle Mode Configuration
bits : 0 - 1 (2 bit)

Enumeration: IDLESelect

0x0 : CPU

The CPU clock domain is stopped

0x1 : AHB

The CPU and AHB clock domains are stopped

0x2 : APB

The CPU, AHB and APB clock domains are stopped

End of enumeration elements list.


AHBMASK

AHB Mask
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBMASK AHBMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HPB0_ HPB1_ HPB2_ DSU_ NVMCTRL_ DMAC_

HPB0_ : HPB0 AHB Clock Mask
bits : 0 - 0 (1 bit)

HPB1_ : HPB1 AHB Clock Mask
bits : 1 - 1 (1 bit)

HPB2_ : HPB2 AHB Clock Mask
bits : 2 - 2 (1 bit)

DSU_ : DSU AHB Clock Mask
bits : 3 - 3 (1 bit)

NVMCTRL_ : NVMCTRL AHB Clock Mask
bits : 4 - 4 (1 bit)

DMAC_ : DMAC AHB Clock Mask
bits : 5 - 5 (1 bit)


APBAMASK

APBA Mask
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBAMASK APBAMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAC0_ PM_ SYSCTRL_ GCLK_ WDT_ RTC_ EIC_

PAC0_ : PAC0 APB Clock Enable
bits : 0 - 0 (1 bit)

PM_ : PM APB Clock Enable
bits : 1 - 1 (1 bit)

SYSCTRL_ : SYSCTRL APB Clock Enable
bits : 2 - 2 (1 bit)

GCLK_ : GCLK APB Clock Enable
bits : 3 - 3 (1 bit)

WDT_ : WDT APB Clock Enable
bits : 4 - 4 (1 bit)

RTC_ : RTC APB Clock Enable
bits : 5 - 5 (1 bit)

EIC_ : EIC APB Clock Enable
bits : 6 - 6 (1 bit)


APBBMASK

APBB Mask
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBBMASK APBBMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAC1_ DSU_ NVMCTRL_ PORT_ DMAC_ HMATRIX_

PAC1_ : PAC1 APB Clock Enable
bits : 0 - 0 (1 bit)

DSU_ : DSU APB Clock Enable
bits : 1 - 1 (1 bit)

NVMCTRL_ : NVMCTRL APB Clock Enable
bits : 2 - 2 (1 bit)

PORT_ : PORT APB Clock Enable
bits : 3 - 3 (1 bit)

DMAC_ : DMAC APB Clock Enable
bits : 4 - 4 (1 bit)

HMATRIX_ : HMATRIX APB Clock Enable
bits : 6 - 6 (1 bit)


EXTCTRL

External Reset Controller
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTCTRL EXTCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SETDIS

SETDIS : External Reset Disable
bits : 0 - 0 (1 bit)


APBCMASK

APBC Mask
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBCMASK APBCMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAC2_ EVSYS_ SERCOM0_ SERCOM1_ SERCOM2_ SERCOM3_ SERCOM4_ SERCOM5_ TCC0_ TCC1_ TCC2_ TC3_ TC4_ TC5_ TC6_ TC7_ ADC_ AC_ DAC_ PTC_ LINCTRL_

PAC2_ : PAC2 APB Clock Enable
bits : 0 - 0 (1 bit)

EVSYS_ : EVSYS APB Clock Enable
bits : 1 - 1 (1 bit)

SERCOM0_ : SERCOM0 APB Clock Enable
bits : 2 - 2 (1 bit)

SERCOM1_ : SERCOM1 APB Clock Enable
bits : 3 - 3 (1 bit)

SERCOM2_ : SERCOM2 APB Clock Enable
bits : 4 - 4 (1 bit)

SERCOM3_ : SERCOM3 APB Clock Enable
bits : 5 - 5 (1 bit)

SERCOM4_ : SERCOM4 APB Clock Enable
bits : 6 - 6 (1 bit)

SERCOM5_ : SERCOM5 APB Clock Enable
bits : 7 - 7 (1 bit)

TCC0_ : TCC0 APB Clock Enable
bits : 8 - 8 (1 bit)

TCC1_ : TCC1 APB Clock Enable
bits : 9 - 9 (1 bit)

TCC2_ : TCC2 APB Clock Enable
bits : 10 - 10 (1 bit)

TC3_ : TC3 APB Clock Enable
bits : 11 - 11 (1 bit)

TC4_ : TC4 APB Clock Enable
bits : 12 - 12 (1 bit)

TC5_ : TC5 APB Clock Enable
bits : 13 - 13 (1 bit)

TC6_ : TC6 APB Clock Enable
bits : 14 - 14 (1 bit)

TC7_ : TC7 APB Clock Enable
bits : 15 - 15 (1 bit)

ADC_ : ADC APB Clock Enable
bits : 16 - 16 (1 bit)

AC_ : AC APB Clock Enable
bits : 17 - 17 (1 bit)

DAC_ : DAC APB Clock Enable
bits : 18 - 18 (1 bit)

PTC_ : PTC APB Clock Enable
bits : 19 - 19 (1 bit)

LINCTRL_ : LINCTRL APB Clock Enable
bits : 22 - 22 (1 bit)


INTENCLR

Interrupt Enable Clear
address_offset : 0x34 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CKRDY

CKRDY : Clock Ready Interrupt Enable
bits : 0 - 0 (1 bit)


INTENSET

Interrupt Enable Set
address_offset : 0x35 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CKRDY

CKRDY : Clock Ready Interrupt Enable
bits : 0 - 0 (1 bit)


INTFLAG

Interrupt Flag Status and Clear
address_offset : 0x36 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAG INTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CKRDY

CKRDY : Clock Ready
bits : 0 - 0 (1 bit)


RCAUSE

Reset Cause
address_offset : 0x38 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RCAUSE RCAUSE read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 POR BOD12 BOD33 EXT WDT SYST

POR : Power On Reset
bits : 0 - 0 (1 bit)

BOD12 : Brown Out 12 Detector Reset
bits : 1 - 1 (1 bit)

BOD33 : Brown Out 33 Detector Reset
bits : 2 - 2 (1 bit)

EXT : External Reset
bits : 4 - 4 (1 bit)

WDT : Watchdog Reset
bits : 5 - 5 (1 bit)

SYST : System Reset Request
bits : 6 - 6 (1 bit)


CPUSEL

CPU Clock Select
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPUSEL CPUSEL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CPUDIV

CPUDIV : CPU Prescaler Selection
bits : 0 - 2 (3 bit)

Enumeration: CPUDIVSelect

0x0 : DIV1

Divide by 1

0x1 : DIV2

Divide by 2

0x2 : DIV4

Divide by 4

0x3 : DIV8

Divide by 8

0x4 : DIV16

Divide by 16

0x5 : DIV32

Divide by 32

0x6 : DIV64

Divide by 64

0x7 : DIV128

Divide by 128

End of enumeration elements list.


APBASEL

APBA Clock Select
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBASEL APBASEL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 APBADIV

APBADIV : APBA Prescaler Selection
bits : 0 - 2 (3 bit)

Enumeration: APBADIVSelect

0x0 : DIV1

Divide by 1

0x1 : DIV2

Divide by 2

0x2 : DIV4

Divide by 4

0x3 : DIV8

Divide by 8

0x4 : DIV16

Divide by 16

0x5 : DIV32

Divide by 32

0x6 : DIV64

Divide by 64

0x7 : DIV128

Divide by 128

End of enumeration elements list.


APBBSEL

APBB Clock Select
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBBSEL APBBSEL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 APBBDIV

APBBDIV : APBB Prescaler Selection
bits : 0 - 2 (3 bit)

Enumeration: APBBDIVSelect

0x0 : DIV1

Divide by 1

0x1 : DIV2

Divide by 2

0x2 : DIV4

Divide by 4

0x3 : DIV8

Divide by 8

0x4 : DIV16

Divide by 16

0x5 : DIV32

Divide by 32

0x6 : DIV64

Divide by 64

0x7 : DIV128

Divide by 128

End of enumeration elements list.


APBCSEL

APBC Clock Select
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBCSEL APBCSEL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 APBCDIV

APBCDIV : APBC Prescaler Selection
bits : 0 - 2 (3 bit)

Enumeration: APBCDIVSelect

0x0 : DIV1

Divide by 1

0x1 : DIV2

Divide by 2

0x2 : DIV4

Divide by 4

0x3 : DIV8

Divide by 8

0x4 : DIV16

Divide by 16

0x5 : DIV32

Divide by 32

0x6 : DIV64

Divide by 64

0x7 : DIV128

Divide by 128

End of enumeration elements list.



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