\n

EVSYS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2BC byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x0 Bytes (0x0)
size : 0x2BC byte (0x0)
mem_usage : registers
protection :

address_offset : 0x0 Bytes (0x0)
size : 0x2BC byte (0x0)
mem_usage : registers
protection :

Registers

CTRLA

CHANNEL

INTPEND

CHANNEL28

CHINTENCLR28

CHINTENSET28

CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHINTFLAG28

CHSTATUS28

CHANNEL29

CHINTENCLR29

CHINTENSET29

CHINTFLAG29

CHSTATUS29

USER[12]

CHANNEL30

CHINTENCLR30

CHINTENSET30

CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHINTFLAG30

CHSTATUS30

CHANNEL31

CHINTENCLR31

CHINTENSET31

CHINTFLAG31

CHSTATUS31

USER0

USER1

USER[13]

CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

USER2

USER3

USER4

USER5

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

USER6

CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

USER[14]

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

USER7

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

INTSTATUS

USER8

USER9

USER10

USER11

USER12

USER[15]

USER13

USER14

USER15

USER16

USER17

USER[16]

USER18

USER19

USER20

USER21

USER22

USER23

USER[17]

BUSYCH

USER24

USER25

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

USER26

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

USER27

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

USER28

USER[18]

USER29

USER30

USER31

USER32

USER33

USER34

USER[19]

USER35

USER36

USER37

USER38

USER39

READYUSR

USER40

USER[20]

USER41

USER42

USER43

USER44

USER45

USER[21]

USER46

USER47

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

USER48

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

USER49

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

USER50

USER51

USER[22]

USER52

USER53

USER54

USER55

CHANNEL[0]-CHANNEL

CHANNEL0

USER56

USER57

USER[23]

USER58

USER59

USER60

USER61

USER62

USER63

USER[24]

USER64

USER65

USER66

USER[25]

CHANNEL[0]-CHINTENCLR

CHINTENCLR0

CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

USER[0]

CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

USER[26]

CHANNEL[0]-CHINTENSET

CHINTENSET0

CHANNEL[0]-CHINTFLAG

CHINTFLAG0

USER[27]

CHANNEL[0]-CHSTATUS

CHSTATUS0

CHANNEL1

USER[28]

USER[29]

CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

USER[30]

CHINTENCLR1

USER[31]

CHINTENSET1

CHINTFLAG1

USER[32]

CHSTATUS1

CHANNEL2

USER[33]

CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

USER[34]

CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

USER[35]

CHINTENCLR2

CHINTENSET2

USER[36]

CHINTFLAG2

USER[1]

USER[37]

CHSTATUS2

CHANNEL3

USER[38]

CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

USER[39]

CHINTENCLR3

USER[40]

CHINTENSET3

USER[41]

CHINTFLAG3

CHSTATUS3

USER[42]

SWEVT

CHINTENCLR

CHANNEL4

CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

USER[43]

CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

USER[44]

CHINTENCLR4

CHINTENSET4

USER[45]

CHINTFLAG4

USER[46]

CHSTATUS4

CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL5

USER[2]

USER[47]

CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

USER[48]

CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHINTENCLR5

USER[49]

CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHINTENSET5

CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHINTFLAG5

USER[50]

CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHSTATUS5

CHINTENSET

CHANNEL6

USER[51]

USER[52]

CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHINTENCLR6

USER[53]

CHINTENSET6

CHINTFLAG6

USER[54]

CHSTATUS6

CHANNEL7

USER[55]

USER[56]

USER[3]

CHINTENCLR7

CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

USER[57]

CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHINTENSET7

CHINTFLAG7

USER[58]

CHSTATUS7

CHINTFLAG

CHANNEL8

USER[59]

USER[60]

CHINTENCLR8

USER[61]

CHINTENSET8

CHINTFLAG8

CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

USER[62]

CHSTATUS8

CHANNEL9

USER[63]

USER[64]

CHINTENCLR9

USER[65]

CHINTENSET9

CHINTFLAG9

USER[4]

CHSTATUS9

USER[66]

CHSTATUS

CHANNEL10

CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHINTENCLR10

CHINTENSET10

CHINTFLAG10

CHSTATUS10

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL11

CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHINTENCLR11

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHINTENSET11

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHINTFLAG11

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHSTATUS11

PRICTRL

CHANNEL12

USER[5]

CHINTENCLR12

CHINTENSET12

CHINTFLAG12

CHSTATUS12

CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHANNEL13

CHINTENCLR13

CHINTENSET13

CHINTFLAG13

CHSTATUS13

CHANNEL14

CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHINTENCLR14

CHINTENSET14

USER[6]

CHINTFLAG14

CHSTATUS14

CHANNEL15

CHINTENCLR15

CHINTENSET15

CHINTFLAG15

CHSTATUS15

CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHANNEL16

CHINTENCLR16

CHINTENSET16

CHINTFLAG16

CHSTATUS16

CHANNEL17

USER[7]

CHINTENCLR17

CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHINTENSET17

CHINTFLAG17

CHSTATUS17

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL18

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHINTENCLR18

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHINTENSET18

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHINTFLAG18

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHSTATUS18

CHANNEL19

CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHINTENCLR19

CHINTENSET19

USER[8]

CHINTFLAG19

CHSTATUS19

CHANNEL20

CHINTENCLR20

CHINTENSET20

CHINTFLAG20

CHSTATUS20

CHANNEL21

CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHINTENCLR21

CHINTENSET21

CHINTFLAG21

CHSTATUS21

CHANNEL22

USER[9]

CHINTENCLR22

CHINTENSET22

CHINTFLAG22

CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHSTATUS22

CHANNEL23

CHINTENCLR23

CHINTENSET23

CHINTFLAG23

CHSTATUS23

CHANNEL24

CHINTENCLR24

CHINTENSET24

CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

USER[10]

CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHINTFLAG24

CHSTATUS24

CHANNEL25

CHINTENCLR25

CHINTENSET25

CHINTFLAG25

CHSTATUS25

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL26

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHINTENCLR26

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHINTENSET26

CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHINTFLAG26

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHSTATUS26

CHANNEL27

USER[11]

CHINTENCLR27

CHINTENSET27

CHINTFLAG27

CHSTATUS27


CTRLA

Control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLA CTRLA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SWRST

SWRST : Software Reset
bits : 0 - 0 (1 bit)


CHANNEL

Channel n Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


INTPEND

Channel Pending Interrupt
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTPEND INTPEND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID OVR EVD READY BUSY

ID : Channel ID
bits : 0 - 3 (4 bit)

OVR : Channel Overrun
bits : 8 - 8 (1 bit)

EVD : Channel Event Detected
bits : 9 - 9 (1 bit)

READY : Ready
bits : 14 - 14 (1 bit)

BUSY : Busy
bits : 15 - 15 (1 bit)


CHANNEL28

Channel n Control
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL28 CHANNEL28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHINTENCLR28

Channel n Interrupt Enable Clear
address_offset : 0x104 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR28 CHINTENCLR28 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHINTENSET28

Channel n Interrupt Enable Set
address_offset : 0x105 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET28 CHINTENSET28 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x1050 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x1054 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x1055 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x1056 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x1057 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


CHINTFLAG28

Channel n Interrupt Flag Status and Clear
address_offset : 0x106 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG28 CHINTFLAG28 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHSTATUS28

Channel n Status
address_offset : 0x107 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS28 CHSTATUS28 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


CHANNEL29

Channel n Control
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL29 CHANNEL29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHINTENCLR29

Channel n Interrupt Enable Clear
address_offset : 0x10C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR29 CHINTENCLR29 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHINTENSET29

Channel n Interrupt Enable Set
address_offset : 0x10D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET29 CHINTENSET29 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHINTFLAG29

Channel n Interrupt Flag Status and Clear
address_offset : 0x10E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG29 CHINTFLAG29 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHSTATUS29

Channel n Status
address_offset : 0x10F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS29 CHSTATUS29 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


USER[12]

User Multiplexer n
address_offset : 0x10F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[12] USER[12] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL30

Channel n Control
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL30 CHANNEL30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHINTENCLR30

Channel n Interrupt Enable Clear
address_offset : 0x114 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR30 CHINTENCLR30 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHINTENSET30

Channel n Interrupt Enable Set
address_offset : 0x115 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET30 CHINTENSET30 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x1158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x115C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x115D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x115E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x115F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


CHINTFLAG30

Channel n Interrupt Flag Status and Clear
address_offset : 0x116 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG30 CHINTFLAG30 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHSTATUS30

Channel n Status
address_offset : 0x117 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS30 CHSTATUS30 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


CHANNEL31

Channel n Control
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL31 CHANNEL31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHINTENCLR31

Channel n Interrupt Enable Clear
address_offset : 0x11C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR31 CHINTENCLR31 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHINTENSET31

Channel n Interrupt Enable Set
address_offset : 0x11D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET31 CHINTENSET31 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHINTFLAG31

Channel n Interrupt Flag Status and Clear
address_offset : 0x11E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG31 CHINTFLAG31 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHSTATUS31

Channel n Status
address_offset : 0x11F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS31 CHSTATUS31 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


USER0

User Multiplexer n
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER0 USER0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER1

User Multiplexer n
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER1 USER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER[13]

User Multiplexer n
address_offset : 0x124C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[13] USER[13] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x1268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x126C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x126D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x126E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x126F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


USER2

User Multiplexer n
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER2 USER2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER3

User Multiplexer n
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER3 USER3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER4

User Multiplexer n
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER4 USER4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER5

User Multiplexer n
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER5 USER5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


USER6

User Multiplexer n
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER6 USER6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x1380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x1384 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x1385 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x1386 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x1387 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


USER[14]

User Multiplexer n
address_offset : 0x13A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[14] USER[14] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x13C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


USER7

User Multiplexer n
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER7 USER7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x13D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x13E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x13F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


INTSTATUS

Interrupt Status
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS INTSTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHINT0 CHINT1 CHINT2 CHINT3 CHINT4 CHINT5 CHINT6 CHINT7 CHINT8 CHINT9 CHINT10 CHINT11

CHINT0 : Channel 0 Pending Interrupt
bits : 0 - 0 (1 bit)

CHINT1 : Channel 1 Pending Interrupt
bits : 1 - 1 (1 bit)

CHINT2 : Channel 2 Pending Interrupt
bits : 2 - 2 (1 bit)

CHINT3 : Channel 3 Pending Interrupt
bits : 3 - 3 (1 bit)

CHINT4 : Channel 4 Pending Interrupt
bits : 4 - 4 (1 bit)

CHINT5 : Channel 5 Pending Interrupt
bits : 5 - 5 (1 bit)

CHINT6 : Channel 6 Pending Interrupt
bits : 6 - 6 (1 bit)

CHINT7 : Channel 7 Pending Interrupt
bits : 7 - 7 (1 bit)

CHINT8 : Channel 8 Pending Interrupt
bits : 8 - 8 (1 bit)

CHINT9 : Channel 9 Pending Interrupt
bits : 9 - 9 (1 bit)

CHINT10 : Channel 10 Pending Interrupt
bits : 10 - 10 (1 bit)

CHINT11 : Channel 11 Pending Interrupt
bits : 11 - 11 (1 bit)


USER8

User Multiplexer n
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER8 USER8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER9

User Multiplexer n
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER9 USER9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER10

User Multiplexer n
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER10 USER10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER11

User Multiplexer n
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER11 USER11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER12

User Multiplexer n
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER12 USER12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER[15]

User Multiplexer n
address_offset : 0x1500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[15] USER[15] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER13

User Multiplexer n
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER13 USER13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER14

User Multiplexer n
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER14 USER14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER15

User Multiplexer n
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER15 USER15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER16

User Multiplexer n
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER16 USER16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER17

User Multiplexer n
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER17 USER17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER[16]

User Multiplexer n
address_offset : 0x1660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[16] USER[16] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER18

User Multiplexer n
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER18 USER18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER19

User Multiplexer n
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER19 USER19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER20

User Multiplexer n
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER20 USER20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER21

User Multiplexer n
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER21 USER21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER22

User Multiplexer n
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER22 USER22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER23

User Multiplexer n
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER23 USER23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER[17]

User Multiplexer n
address_offset : 0x17C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[17] USER[17] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


BUSYCH

Busy Channels
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUSYCH BUSYCH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSYCH0 BUSYCH1 BUSYCH2 BUSYCH3 BUSYCH4 BUSYCH5 BUSYCH6 BUSYCH7 BUSYCH8 BUSYCH9 BUSYCH10 BUSYCH11

BUSYCH0 : Busy Channel 0
bits : 0 - 0 (1 bit)

BUSYCH1 : Busy Channel 1
bits : 1 - 1 (1 bit)

BUSYCH2 : Busy Channel 2
bits : 2 - 2 (1 bit)

BUSYCH3 : Busy Channel 3
bits : 3 - 3 (1 bit)

BUSYCH4 : Busy Channel 4
bits : 4 - 4 (1 bit)

BUSYCH5 : Busy Channel 5
bits : 5 - 5 (1 bit)

BUSYCH6 : Busy Channel 6
bits : 6 - 6 (1 bit)

BUSYCH7 : Busy Channel 7
bits : 7 - 7 (1 bit)

BUSYCH8 : Busy Channel 8
bits : 8 - 8 (1 bit)

BUSYCH9 : Busy Channel 9
bits : 9 - 9 (1 bit)

BUSYCH10 : Busy Channel 10
bits : 10 - 10 (1 bit)

BUSYCH11 : Busy Channel 11
bits : 11 - 11 (1 bit)


USER24

User Multiplexer n
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER24 USER24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER25

User Multiplexer n
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER25 USER25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


USER26

User Multiplexer n
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER26 USER26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x18C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


USER27

User Multiplexer n
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER27 USER27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x18D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x18E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x18F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


USER28

User Multiplexer n
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER28 USER28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER[18]

User Multiplexer n
address_offset : 0x192C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[18] USER[18] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER29

User Multiplexer n
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER29 USER29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER30

User Multiplexer n
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER30 USER30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER31

User Multiplexer n
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER31 USER31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER32

User Multiplexer n
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER32 USER32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER33

User Multiplexer n
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER33 USER33 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER34

User Multiplexer n
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER34 USER34 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER[19]

User Multiplexer n
address_offset : 0x1A98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[19] USER[19] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER35

User Multiplexer n
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER35 USER35 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER36

User Multiplexer n
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER36 USER36 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER37

User Multiplexer n
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER37 USER37 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER38

User Multiplexer n
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER38 USER38 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER39

User Multiplexer n
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER39 USER39 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


READYUSR

Ready Users
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

READYUSR READYUSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READYUSR0 READYUSR1 READYUSR2 READYUSR3 READYUSR4 READYUSR5 READYUSR6 READYUSR7 READYUSR8 READYUSR9 READYUSR10 READYUSR11

READYUSR0 : Ready User for Channel 0
bits : 0 - 0 (1 bit)

READYUSR1 : Ready User for Channel 1
bits : 1 - 1 (1 bit)

READYUSR2 : Ready User for Channel 2
bits : 2 - 2 (1 bit)

READYUSR3 : Ready User for Channel 3
bits : 3 - 3 (1 bit)

READYUSR4 : Ready User for Channel 4
bits : 4 - 4 (1 bit)

READYUSR5 : Ready User for Channel 5
bits : 5 - 5 (1 bit)

READYUSR6 : Ready User for Channel 6
bits : 6 - 6 (1 bit)

READYUSR7 : Ready User for Channel 7
bits : 7 - 7 (1 bit)

READYUSR8 : Ready User for Channel 8
bits : 8 - 8 (1 bit)

READYUSR9 : Ready User for Channel 9
bits : 9 - 9 (1 bit)

READYUSR10 : Ready User for Channel 10
bits : 10 - 10 (1 bit)

READYUSR11 : Ready User for Channel 11
bits : 11 - 11 (1 bit)


USER40

User Multiplexer n
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER40 USER40 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER[20]

User Multiplexer n
address_offset : 0x1C08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[20] USER[20] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER41

User Multiplexer n
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER41 USER41 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER42

User Multiplexer n
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER42 USER42 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER43

User Multiplexer n
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER43 USER43 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER44

User Multiplexer n
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER44 USER44 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER45

User Multiplexer n
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER45 USER45 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER[21]

User Multiplexer n
address_offset : 0x1D7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[21] USER[21] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER46

User Multiplexer n
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER46 USER46 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER47

User Multiplexer n
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER47 USER47 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


USER48

User Multiplexer n
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER48 USER48 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x1E4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


USER49

User Multiplexer n
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER49 USER49 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x1E5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x1E6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x1E7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


USER50

User Multiplexer n
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER50 USER50 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER51

User Multiplexer n
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER51 USER51 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER[22]

User Multiplexer n
address_offset : 0x1EF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[22] USER[22] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER52

User Multiplexer n
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER52 USER52 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER53

User Multiplexer n
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER53 USER53 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER54

User Multiplexer n
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER54 USER54 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER55

User Multiplexer n
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER55 USER55 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[0]-CHANNEL CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL0

Channel n Control
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL0 CHANNEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


USER56

User Multiplexer n
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER56 USER56 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER57

User Multiplexer n
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER57 USER57 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER[23]

User Multiplexer n
address_offset : 0x2070 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[23] USER[23] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER58

User Multiplexer n
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER58 USER58 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER59

User Multiplexer n
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER59 USER59 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER60

User Multiplexer n
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER60 USER60 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER61

User Multiplexer n
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER61 USER61 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER62

User Multiplexer n
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER62 USER62 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER63

User Multiplexer n
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER63 USER63 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER[24]

User Multiplexer n
address_offset : 0x21F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[24] USER[24] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER64

User Multiplexer n
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER64 USER64 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER65

User Multiplexer n
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER65 USER65 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER66

User Multiplexer n
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER66 USER66 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER[25]

User Multiplexer n
address_offset : 0x2374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[25] USER[25] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[0]-CHINTENCLR CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHINTENCLR0

Channel n Interrupt Enable Clear
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR0 CHINTENCLR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


USER[0]

User Multiplexer n
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[0] USER[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x244 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x245 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x246 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x247 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


USER[26]

User Multiplexer n
address_offset : 0x24FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[26] USER[26] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x25 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[0]-CHINTENSET CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHINTENSET0

Channel n Interrupt Enable Set
address_offset : 0x25 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET0 CHINTENSET0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x26 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[0]-CHINTFLAG CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHINTFLAG0

Channel n Interrupt Flag Status and Clear
address_offset : 0x26 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG0 CHINTFLAG0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


USER[27]

User Multiplexer n
address_offset : 0x2688 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[27] USER[27] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x27 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[0]-CHSTATUS CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


CHSTATUS0

Channel n Status
address_offset : 0x27 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS0 CHSTATUS0 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


CHANNEL1

Channel n Control
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL1 CHANNEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


USER[28]

User Multiplexer n
address_offset : 0x2818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[28] USER[28] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER[29]

User Multiplexer n
address_offset : 0x29AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[29] USER[29] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x2AC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x2AD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x2AE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x2AF Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


USER[30]

User Multiplexer n
address_offset : 0x2B44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[30] USER[30] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHINTENCLR1

Channel n Interrupt Enable Clear
address_offset : 0x2C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR1 CHINTENCLR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


USER[31]

User Multiplexer n
address_offset : 0x2CE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[31] USER[31] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHINTENSET1

Channel n Interrupt Enable Set
address_offset : 0x2D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET1 CHINTENSET1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHINTFLAG1

Channel n Interrupt Flag Status and Clear
address_offset : 0x2E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG1 CHINTFLAG1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


USER[32]

User Multiplexer n
address_offset : 0x2E80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[32] USER[32] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHSTATUS1

Channel n Status
address_offset : 0x2F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS1 CHSTATUS1 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


CHANNEL2

Channel n Control
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL2 CHANNEL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


USER[33]

User Multiplexer n
address_offset : 0x3024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[33] USER[33] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x31C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


USER[34]

User Multiplexer n
address_offset : 0x31CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[34] USER[34] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x31D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x31E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x31F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


USER[35]

User Multiplexer n
address_offset : 0x3378 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[35] USER[35] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHINTENCLR2

Channel n Interrupt Enable Clear
address_offset : 0x34 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR2 CHINTENCLR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHINTENSET2

Channel n Interrupt Enable Set
address_offset : 0x35 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET2 CHINTENSET2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


USER[36]

User Multiplexer n
address_offset : 0x3528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[36] USER[36] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHINTFLAG2

Channel n Interrupt Flag Status and Clear
address_offset : 0x36 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG2 CHINTFLAG2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


USER[1]

User Multiplexer n
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[1] USER[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER[37]

User Multiplexer n
address_offset : 0x36DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[37] USER[37] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHSTATUS2

Channel n Status
address_offset : 0x37 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS2 CHSTATUS2 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


CHANNEL3

Channel n Control
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL3 CHANNEL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


USER[38]

User Multiplexer n
address_offset : 0x3894 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[38] USER[38] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x394 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x395 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x396 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x397 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


USER[39]

User Multiplexer n
address_offset : 0x3A50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[39] USER[39] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHINTENCLR3

Channel n Interrupt Enable Clear
address_offset : 0x3C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR3 CHINTENCLR3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


USER[40]

User Multiplexer n
address_offset : 0x3C10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[40] USER[40] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHINTENSET3

Channel n Interrupt Enable Set
address_offset : 0x3D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET3 CHINTENSET3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


USER[41]

User Multiplexer n
address_offset : 0x3DD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[41] USER[41] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHINTFLAG3

Channel n Interrupt Flag Status and Clear
address_offset : 0x3E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG3 CHINTFLAG3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHSTATUS3

Channel n Status
address_offset : 0x3F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS3 CHSTATUS3 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


USER[42]

User Multiplexer n
address_offset : 0x3F9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[42] USER[42] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


SWEVT

Software Event
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SWEVT SWEVT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 CHANNEL4 CHANNEL5 CHANNEL6 CHANNEL7 CHANNEL8 CHANNEL9 CHANNEL10 CHANNEL11 CHANNEL12 CHANNEL13 CHANNEL14 CHANNEL15 CHANNEL16 CHANNEL17 CHANNEL18 CHANNEL19 CHANNEL20 CHANNEL21 CHANNEL22 CHANNEL23 CHANNEL24 CHANNEL25 CHANNEL26 CHANNEL27 CHANNEL28 CHANNEL29 CHANNEL30 CHANNEL31

CHANNEL0 : Channel 0 Software Selection
bits : 0 - 0 (1 bit)

CHANNEL1 : Channel 1 Software Selection
bits : 1 - 1 (1 bit)

CHANNEL2 : Channel 2 Software Selection
bits : 2 - 2 (1 bit)

CHANNEL3 : Channel 3 Software Selection
bits : 3 - 3 (1 bit)

CHANNEL4 : Channel 4 Software Selection
bits : 4 - 4 (1 bit)

CHANNEL5 : Channel 5 Software Selection
bits : 5 - 5 (1 bit)

CHANNEL6 : Channel 6 Software Selection
bits : 6 - 6 (1 bit)

CHANNEL7 : Channel 7 Software Selection
bits : 7 - 7 (1 bit)

CHANNEL8 : Channel 8 Software Selection
bits : 8 - 8 (1 bit)

CHANNEL9 : Channel 9 Software Selection
bits : 9 - 9 (1 bit)

CHANNEL10 : Channel 10 Software Selection
bits : 10 - 10 (1 bit)

CHANNEL11 : Channel 11 Software Selection
bits : 11 - 11 (1 bit)

CHANNEL12 : Channel 12 Software Selection
bits : 12 - 12 (1 bit)

CHANNEL13 : Channel 13 Software Selection
bits : 13 - 13 (1 bit)

CHANNEL14 : Channel 14 Software Selection
bits : 14 - 14 (1 bit)

CHANNEL15 : Channel 15 Software Selection
bits : 15 - 15 (1 bit)

CHANNEL16 : Channel 16 Software Selection
bits : 16 - 16 (1 bit)

CHANNEL17 : Channel 17 Software Selection
bits : 17 - 17 (1 bit)

CHANNEL18 : Channel 18 Software Selection
bits : 18 - 18 (1 bit)

CHANNEL19 : Channel 19 Software Selection
bits : 19 - 19 (1 bit)

CHANNEL20 : Channel 20 Software Selection
bits : 20 - 20 (1 bit)

CHANNEL21 : Channel 21 Software Selection
bits : 21 - 21 (1 bit)

CHANNEL22 : Channel 22 Software Selection
bits : 22 - 22 (1 bit)

CHANNEL23 : Channel 23 Software Selection
bits : 23 - 23 (1 bit)

CHANNEL24 : Channel 24 Software Selection
bits : 24 - 24 (1 bit)

CHANNEL25 : Channel 25 Software Selection
bits : 25 - 25 (1 bit)

CHANNEL26 : Channel 26 Software Selection
bits : 26 - 26 (1 bit)

CHANNEL27 : Channel 27 Software Selection
bits : 27 - 27 (1 bit)

CHANNEL28 : Channel 28 Software Selection
bits : 28 - 28 (1 bit)

CHANNEL29 : Channel 29 Software Selection
bits : 29 - 29 (1 bit)

CHANNEL30 : Channel 30 Software Selection
bits : 30 - 30 (1 bit)

CHANNEL31 : Channel 31 Software Selection
bits : 31 - 31 (1 bit)


CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL4

Channel n Control
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL4 CHANNEL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x414 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x415 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x416 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


USER[43]

User Multiplexer n
address_offset : 0x4168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[43] USER[43] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x417 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


USER[44]

User Multiplexer n
address_offset : 0x4338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[44] USER[44] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHINTENCLR4

Channel n Interrupt Enable Clear
address_offset : 0x44 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR4 CHINTENCLR4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHINTENSET4

Channel n Interrupt Enable Set
address_offset : 0x45 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET4 CHINTENSET4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


USER[45]

User Multiplexer n
address_offset : 0x450C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[45] USER[45] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHINTFLAG4

Channel n Interrupt Flag Status and Clear
address_offset : 0x46 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG4 CHINTFLAG4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


USER[46]

User Multiplexer n
address_offset : 0x46E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[46] USER[46] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHSTATUS4

Channel n Status
address_offset : 0x47 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS4 CHSTATUS4 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL5

Channel n Control
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL5 CHANNEL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


USER[2]

User Multiplexer n
address_offset : 0x48C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[2] USER[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER[47]

User Multiplexer n
address_offset : 0x48C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[47] USER[47] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x49C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x49D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x49E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x49F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


USER[48]

User Multiplexer n
address_offset : 0x4AA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[48] USER[48] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x4C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHINTENCLR5

Channel n Interrupt Enable Clear
address_offset : 0x4C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR5 CHINTENCLR5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


USER[49]

User Multiplexer n
address_offset : 0x4C84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[49] USER[49] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x4D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHINTENSET5

Channel n Interrupt Enable Set
address_offset : 0x4D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET5 CHINTENSET5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x4E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHINTFLAG5

Channel n Interrupt Flag Status and Clear
address_offset : 0x4E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG5 CHINTFLAG5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


USER[50]

User Multiplexer n
address_offset : 0x4E6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[50] USER[50] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x4F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


CHSTATUS5

Channel n Status
address_offset : 0x4F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS5 CHSTATUS5 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL6

Channel n Control
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL6 CHANNEL6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


USER[51]

User Multiplexer n
address_offset : 0x5058 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[51] USER[51] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER[52]

User Multiplexer n
address_offset : 0x5248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[52] USER[52] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x52C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x52D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x52E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x52F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


CHINTENCLR6

Channel n Interrupt Enable Clear
address_offset : 0x54 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR6 CHINTENCLR6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


USER[53]

User Multiplexer n
address_offset : 0x543C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[53] USER[53] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHINTENSET6

Channel n Interrupt Enable Set
address_offset : 0x55 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET6 CHINTENSET6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHINTFLAG6

Channel n Interrupt Flag Status and Clear
address_offset : 0x56 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG6 CHINTFLAG6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


USER[54]

User Multiplexer n
address_offset : 0x5634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[54] USER[54] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHSTATUS6

Channel n Status
address_offset : 0x57 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS6 CHSTATUS6 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


CHANNEL7

Channel n Control
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL7 CHANNEL7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


USER[55]

User Multiplexer n
address_offset : 0x5830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[55] USER[55] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER[56]

User Multiplexer n
address_offset : 0x5A30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[56] USER[56] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER[3]

User Multiplexer n
address_offset : 0x5B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[3] USER[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHINTENCLR7

Channel n Interrupt Enable Clear
address_offset : 0x5C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR7 CHINTENCLR7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


USER[57]

User Multiplexer n
address_offset : 0x5C34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[57] USER[57] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x5C4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x5C5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x5C6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x5C7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


CHINTENSET7

Channel n Interrupt Enable Set
address_offset : 0x5D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET7 CHINTENSET7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHINTFLAG7

Channel n Interrupt Flag Status and Clear
address_offset : 0x5E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG7 CHINTFLAG7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


USER[58]

User Multiplexer n
address_offset : 0x5E3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[58] USER[58] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHSTATUS7

Channel n Status
address_offset : 0x5F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS7 CHSTATUS7 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL8

Channel n Control
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL8 CHANNEL8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


USER[59]

User Multiplexer n
address_offset : 0x6048 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[59] USER[59] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER[60]

User Multiplexer n
address_offset : 0x6258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[60] USER[60] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHINTENCLR8

Channel n Interrupt Enable Clear
address_offset : 0x64 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR8 CHINTENCLR8 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


USER[61]

User Multiplexer n
address_offset : 0x646C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[61] USER[61] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHINTENSET8

Channel n Interrupt Enable Set
address_offset : 0x65 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET8 CHINTENSET8 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHINTFLAG8

Channel n Interrupt Flag Status and Clear
address_offset : 0x66 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG8 CHINTFLAG8 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x664 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x665 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x666 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x667 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


USER[62]

User Multiplexer n
address_offset : 0x6684 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[62] USER[62] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHSTATUS8

Channel n Status
address_offset : 0x67 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS8 CHSTATUS8 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


CHANNEL9

Channel n Control
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL9 CHANNEL9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


USER[63]

User Multiplexer n
address_offset : 0x68A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[63] USER[63] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


USER[64]

User Multiplexer n
address_offset : 0x6AC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[64] USER[64] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHINTENCLR9

Channel n Interrupt Enable Clear
address_offset : 0x6C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR9 CHINTENCLR9 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


USER[65]

User Multiplexer n
address_offset : 0x6CE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[65] USER[65] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHINTENSET9

Channel n Interrupt Enable Set
address_offset : 0x6D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET9 CHINTENSET9 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHINTFLAG9

Channel n Interrupt Flag Status and Clear
address_offset : 0x6E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG9 CHINTFLAG9 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


USER[4]

User Multiplexer n
address_offset : 0x6E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[4] USER[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHSTATUS9

Channel n Status
address_offset : 0x6F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS9 CHSTATUS9 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


USER[66]

User Multiplexer n
address_offset : 0x6F0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[66] USER[66] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHSTATUS

Channel n Status
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


CHANNEL10

Channel n Control
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL10 CHANNEL10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x708 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x70C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x70D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x70E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x70F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


CHINTENCLR10

Channel n Interrupt Enable Clear
address_offset : 0x74 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR10 CHINTENCLR10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHINTENSET10

Channel n Interrupt Enable Set
address_offset : 0x75 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET10 CHINTENSET10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHINTFLAG10

Channel n Interrupt Flag Status and Clear
address_offset : 0x76 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG10 CHINTFLAG10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHSTATUS10

Channel n Status
address_offset : 0x77 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS10 CHSTATUS10 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL11

Channel n Control
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL11 CHANNEL11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x7B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x7BC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x7BD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x7BE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x7BF Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x7C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHINTENCLR11

Channel n Interrupt Enable Clear
address_offset : 0x7C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR11 CHINTENCLR11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x7D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHINTENSET11

Channel n Interrupt Enable Set
address_offset : 0x7D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET11 CHINTENSET11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x7E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHINTFLAG11

Channel n Interrupt Flag Status and Clear
address_offset : 0x7E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG11 CHINTFLAG11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x7F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


CHSTATUS11

Channel n Status
address_offset : 0x7F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS11 CHSTATUS11 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


PRICTRL

Priority Control
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRICTRL PRICTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI RREN

PRI : Channel Priority Number
bits : 0 - 3 (4 bit)

RREN : Round-Robin Scheduling Enable
bits : 7 - 7 (1 bit)


CHANNEL12

Channel n Control
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL12 CHANNEL12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


USER[5]

User Multiplexer n
address_offset : 0x81C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[5] USER[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHINTENCLR12

Channel n Interrupt Enable Clear
address_offset : 0x84 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR12 CHINTENCLR12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHINTENSET12

Channel n Interrupt Enable Set
address_offset : 0x85 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET12 CHINTENSET12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHINTFLAG12

Channel n Interrupt Flag Status and Clear
address_offset : 0x86 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG12 CHINTFLAG12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHSTATUS12

Channel n Status
address_offset : 0x87 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS12 CHSTATUS12 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x874 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x875 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x876 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x877 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


CHANNEL13

Channel n Control
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL13 CHANNEL13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHINTENCLR13

Channel n Interrupt Enable Clear
address_offset : 0x8C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR13 CHINTENCLR13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHINTENSET13

Channel n Interrupt Enable Set
address_offset : 0x8D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET13 CHINTENSET13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHINTFLAG13

Channel n Interrupt Flag Status and Clear
address_offset : 0x8E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG13 CHINTFLAG13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHSTATUS13

Channel n Status
address_offset : 0x8F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS13 CHSTATUS13 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


CHANNEL14

Channel n Control
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL14 CHANNEL14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x934 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x935 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x936 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x937 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


CHINTENCLR14

Channel n Interrupt Enable Clear
address_offset : 0x94 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR14 CHINTENCLR14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHINTENSET14

Channel n Interrupt Enable Set
address_offset : 0x95 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET14 CHINTENSET14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


USER[6]

User Multiplexer n
address_offset : 0x954 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[6] USER[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHINTFLAG14

Channel n Interrupt Flag Status and Clear
address_offset : 0x96 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG14 CHINTFLAG14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHSTATUS14

Channel n Status
address_offset : 0x97 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS14 CHSTATUS14 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


CHANNEL15

Channel n Control
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL15 CHANNEL15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHINTENCLR15

Channel n Interrupt Enable Clear
address_offset : 0x9C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR15 CHINTENCLR15 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHINTENSET15

Channel n Interrupt Enable Set
address_offset : 0x9D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET15 CHINTENSET15 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHINTFLAG15

Channel n Interrupt Flag Status and Clear
address_offset : 0x9E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG15 CHINTFLAG15 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHSTATUS15

Channel n Status
address_offset : 0x9F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS15 CHSTATUS15 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x9F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x9FC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x9FD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x9FE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x9FF Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


CHANNEL16

Channel n Control
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL16 CHANNEL16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHINTENCLR16

Channel n Interrupt Enable Clear
address_offset : 0xA4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR16 CHINTENCLR16 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHINTENSET16

Channel n Interrupt Enable Set
address_offset : 0xA5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET16 CHINTENSET16 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHINTFLAG16

Channel n Interrupt Flag Status and Clear
address_offset : 0xA6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG16 CHINTFLAG16 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHSTATUS16

Channel n Status
address_offset : 0xA7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS16 CHSTATUS16 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


CHANNEL17

Channel n Control
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL17 CHANNEL17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


USER[7]

User Multiplexer n
address_offset : 0xA90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[7] USER[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHINTENCLR17

Channel n Interrupt Enable Clear
address_offset : 0xAC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR17 CHINTENCLR17 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0xAC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0xACC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0xACD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0xACE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0xACF Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


CHINTENSET17

Channel n Interrupt Enable Set
address_offset : 0xAD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET17 CHINTENSET17 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHINTFLAG17

Channel n Interrupt Flag Status and Clear
address_offset : 0xAE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG17 CHINTFLAG17 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHSTATUS17

Channel n Status
address_offset : 0xAF Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS17 CHSTATUS17 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL18

Channel n Control
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL18 CHANNEL18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0xB4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHINTENCLR18

Channel n Interrupt Enable Clear
address_offset : 0xB4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR18 CHINTENCLR18 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0xB5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHINTENSET18

Channel n Interrupt Enable Set
address_offset : 0xB5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET18 CHINTENSET18 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0xB6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHINTFLAG18

Channel n Interrupt Flag Status and Clear
address_offset : 0xB6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG18 CHINTFLAG18 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0xB7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


CHSTATUS18

Channel n Status
address_offset : 0xB7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS18 CHSTATUS18 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


CHANNEL19

Channel n Control
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL19 CHANNEL19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0xBA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0xBA4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0xBA5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0xBA6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0xBA7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


CHINTENCLR19

Channel n Interrupt Enable Clear
address_offset : 0xBC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR19 CHINTENCLR19 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHINTENSET19

Channel n Interrupt Enable Set
address_offset : 0xBD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET19 CHINTENSET19 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


USER[8]

User Multiplexer n
address_offset : 0xBD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[8] USER[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHINTFLAG19

Channel n Interrupt Flag Status and Clear
address_offset : 0xBE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG19 CHINTFLAG19 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHSTATUS19

Channel n Status
address_offset : 0xBF Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS19 CHSTATUS19 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


CHANNEL20

Channel n Control
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL20 CHANNEL20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHINTENCLR20

Channel n Interrupt Enable Clear
address_offset : 0xC4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR20 CHINTENCLR20 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHINTENSET20

Channel n Interrupt Enable Set
address_offset : 0xC5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET20 CHINTENSET20 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHINTFLAG20

Channel n Interrupt Flag Status and Clear
address_offset : 0xC6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG20 CHINTFLAG20 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHSTATUS20

Channel n Status
address_offset : 0xC7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS20 CHSTATUS20 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


CHANNEL21

Channel n Control
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL21 CHANNEL21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0xC80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0xC84 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0xC85 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0xC86 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0xC87 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


CHINTENCLR21

Channel n Interrupt Enable Clear
address_offset : 0xCC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR21 CHINTENCLR21 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHINTENSET21

Channel n Interrupt Enable Set
address_offset : 0xCD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET21 CHINTENSET21 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHINTFLAG21

Channel n Interrupt Flag Status and Clear
address_offset : 0xCE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG21 CHINTFLAG21 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHSTATUS21

Channel n Status
address_offset : 0xCF Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS21 CHSTATUS21 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


CHANNEL22

Channel n Control
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL22 CHANNEL22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


USER[9]

User Multiplexer n
address_offset : 0xD14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[9] USER[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHINTENCLR22

Channel n Interrupt Enable Clear
address_offset : 0xD4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR22 CHINTENCLR22 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHINTENSET22

Channel n Interrupt Enable Set
address_offset : 0xD5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET22 CHINTENSET22 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHINTFLAG22

Channel n Interrupt Flag Status and Clear
address_offset : 0xD6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG22 CHINTFLAG22 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0xD68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0xD6C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0xD6D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0xD6E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0xD6F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


CHSTATUS22

Channel n Status
address_offset : 0xD7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS22 CHSTATUS22 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


CHANNEL23

Channel n Control
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL23 CHANNEL23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHINTENCLR23

Channel n Interrupt Enable Clear
address_offset : 0xDC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR23 CHINTENCLR23 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHINTENSET23

Channel n Interrupt Enable Set
address_offset : 0xDD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET23 CHINTENSET23 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHINTFLAG23

Channel n Interrupt Flag Status and Clear
address_offset : 0xDE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG23 CHINTFLAG23 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHSTATUS23

Channel n Status
address_offset : 0xDF Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS23 CHSTATUS23 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


CHANNEL24

Channel n Control
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL24 CHANNEL24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHINTENCLR24

Channel n Interrupt Enable Clear
address_offset : 0xE4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR24 CHINTENCLR24 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHINTENSET24

Channel n Interrupt Enable Set
address_offset : 0xE5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET24 CHINTENSET24 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0xE58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0xE5C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


USER[10]

User Multiplexer n
address_offset : 0xE5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[10] USER[10] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0xE5D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0xE5E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0xE5F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


CHINTFLAG24

Channel n Interrupt Flag Status and Clear
address_offset : 0xE6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG24 CHINTFLAG24 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHSTATUS24

Channel n Status
address_offset : 0xE7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS24 CHSTATUS24 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


CHANNEL25

Channel n Control
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL25 CHANNEL25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHINTENCLR25

Channel n Interrupt Enable Clear
address_offset : 0xEC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR25 CHINTENCLR25 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHINTENSET25

Channel n Interrupt Enable Set
address_offset : 0xED Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET25 CHINTENSET25 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHINTFLAG25

Channel n Interrupt Flag Status and Clear
address_offset : 0xEE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG25 CHINTFLAG25 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHSTATUS25

Channel n Status
address_offset : 0xEF Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS25 CHSTATUS25 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL26

Channel n Control
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL26 CHANNEL26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0xF4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHINTENCLR26

Channel n Interrupt Enable Clear
address_offset : 0xF4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR26 CHINTENCLR26 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0xF5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHINTENSET26

Channel n Interrupt Enable Set
address_offset : 0xF5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET26 CHINTENSET26 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0xF50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0xF54 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0xF55 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0xF56 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0xF57 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0xF6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHINTFLAG26

Channel n Interrupt Flag Status and Clear
address_offset : 0xF6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG26 CHINTFLAG26 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0xF7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


CHSTATUS26

Channel n Status
address_offset : 0xF7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS26 CHSTATUS26 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only


CHANNEL27

Channel n Control
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL27 CHANNEL27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0x0 : SYNCHRONOUS

Synchronous path

0x1 : RESYNCHRONIZED

Resynchronized path

0x2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0x0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

0x1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

0x2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

0x3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


USER[11]

User Multiplexer n
address_offset : 0xFA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[11] USER[11] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)


CHINTENCLR27

Channel n Interrupt Enable Clear
address_offset : 0xFC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR27 CHINTENCLR27 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHINTENSET27

Channel n Interrupt Enable Set
address_offset : 0xFD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET27 CHINTENSET27 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHINTFLAG27

Channel n Interrupt Flag Status and Clear
address_offset : 0xFE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG27 CHINTFLAG27 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHSTATUS27

Channel n Status
address_offset : 0xFF Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS27 CHSTATUS27 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
access : read-only



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