DMAC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection :

Registers

add a new register to this peripheral

CTRL

SWTRIGCTRL

PRICTRL0

CRCCTRL

INTPEND

INTSTATUS

BUSYCH

PENDCH

ACTIVE

BASEADDR

WRBADDR

CHID

CRCDATAIN

CHCTRLA

CHCTRLB

CHINTENCLR

CHINTENSET

CHINTFLAG

CHSTATUS

CRCCHKSUM

CRCSTATUS

DBGCTRL

QOSCTRL


CTRL

Control
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST DMAENABLE CRCENABLE LVLEN0 LVLEN1 LVLEN2 LVLEN3

SWRST : Software Reset
bits : 0 - 0 (1 bit)

DMAENABLE : DMA Enable
bits : 1 - 1 (1 bit)

CRCENABLE : CRC Enable
bits : 2 - 2 (1 bit)

LVLEN0 : Priority Level 0 Enable
bits : 8 - 8 (1 bit)

LVLEN1 : Priority Level 1 Enable
bits : 9 - 9 (1 bit)

LVLEN2 : Priority Level 2 Enable
bits : 10 - 10 (1 bit)

LVLEN3 : Priority Level 3 Enable
bits : 11 - 11 (1 bit)


SWTRIGCTRL

Software Trigger Control
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWTRIGCTRL SWTRIGCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWTRIG0 SWTRIG1 SWTRIG2 SWTRIG3 SWTRIG4 SWTRIG5 SWTRIG6 SWTRIG7 SWTRIG8 SWTRIG9 SWTRIG10 SWTRIG11

SWTRIG0 : Channel 0 Software Trigger
bits : 0 - 0 (1 bit)

SWTRIG1 : Channel 1 Software Trigger
bits : 1 - 1 (1 bit)

SWTRIG2 : Channel 2 Software Trigger
bits : 2 - 2 (1 bit)

SWTRIG3 : Channel 3 Software Trigger
bits : 3 - 3 (1 bit)

SWTRIG4 : Channel 4 Software Trigger
bits : 4 - 4 (1 bit)

SWTRIG5 : Channel 5 Software Trigger
bits : 5 - 5 (1 bit)

SWTRIG6 : Channel 6 Software Trigger
bits : 6 - 6 (1 bit)

SWTRIG7 : Channel 7 Software Trigger
bits : 7 - 7 (1 bit)

SWTRIG8 : Channel 8 Software Trigger
bits : 8 - 8 (1 bit)

SWTRIG9 : Channel 9 Software Trigger
bits : 9 - 9 (1 bit)

SWTRIG10 : Channel 10 Software Trigger
bits : 10 - 10 (1 bit)

SWTRIG11 : Channel 11 Software Trigger
bits : 11 - 11 (1 bit)


PRICTRL0

Priority Control 0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRICTRL0 PRICTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVLPRI0 RRLVLEN0 LVLPRI1 RRLVLEN1 LVLPRI2 RRLVLEN2 LVLPRI3 RRLVLEN3

LVLPRI0 : Level 0 Channel Priority Number
bits : 0 - 3 (4 bit)

RRLVLEN0 : Level 0 Round-Robin Scheduling Enable
bits : 7 - 7 (1 bit)

LVLPRI1 : Level 1 Channel Priority Number
bits : 8 - 11 (4 bit)

RRLVLEN1 : Level 1 Round-Robin Scheduling Enable
bits : 15 - 15 (1 bit)

LVLPRI2 : Level 2 Channel Priority Number
bits : 16 - 19 (4 bit)

RRLVLEN2 : Level 2 Round-Robin Scheduling Enable
bits : 23 - 23 (1 bit)

LVLPRI3 : Level 3 Channel Priority Number
bits : 24 - 27 (4 bit)

RRLVLEN3 : Level 3 Round-Robin Scheduling Enable
bits : 31 - 31 (1 bit)


CRCCTRL

CRC Control
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRCCTRL CRCCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRCBEATSIZE CRCPOLY CRCSRC

CRCBEATSIZE : CRC Beat Size
bits : 0 - 1 (2 bit)

Enumeration: CRCBEATSIZESelect

0x0 : BYTE

Byte bus access

0x1 : HWORD

Half-word bus access

0x2 : WORD

Word bus access

End of enumeration elements list.

CRCPOLY : CRC Polynomial Type
bits : 2 - 3 (2 bit)

Enumeration: CRCPOLYSelect

0x0 : CRC16

CRC-16 (CRC-CCITT)

0x1 : CRC32

CRC32 (IEEE 802.3)

End of enumeration elements list.

CRCSRC : CRC Input Source
bits : 8 - 13 (6 bit)

Enumeration: CRCSRCSelect

0x0 : NOACT

No action

0x1 : IO

I/O interface

End of enumeration elements list.


INTPEND

Interrupt Pending
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTPEND INTPEND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID TERR TCMPL SUSP FERR BUSY PEND

ID : Channel ID
bits : 0 - 3 (4 bit)

TERR : Transfer Error
bits : 8 - 8 (1 bit)

TCMPL : Transfer Complete
bits : 9 - 9 (1 bit)

SUSP : Channel Suspend
bits : 10 - 10 (1 bit)

FERR : Fetch Error
bits : 13 - 13 (1 bit)
access : read-only

BUSY : Busy
bits : 14 - 14 (1 bit)
access : read-only

PEND : Pending
bits : 15 - 15 (1 bit)
access : read-only


INTSTATUS

Interrupt Status
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS INTSTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHINT0 CHINT1 CHINT2 CHINT3 CHINT4 CHINT5 CHINT6 CHINT7 CHINT8 CHINT9 CHINT10 CHINT11

CHINT0 : Channel 0 Pending Interrupt
bits : 0 - 0 (1 bit)
access : read-only

CHINT1 : Channel 1 Pending Interrupt
bits : 1 - 1 (1 bit)
access : read-only

CHINT2 : Channel 2 Pending Interrupt
bits : 2 - 2 (1 bit)
access : read-only

CHINT3 : Channel 3 Pending Interrupt
bits : 3 - 3 (1 bit)
access : read-only

CHINT4 : Channel 4 Pending Interrupt
bits : 4 - 4 (1 bit)
access : read-only

CHINT5 : Channel 5 Pending Interrupt
bits : 5 - 5 (1 bit)
access : read-only

CHINT6 : Channel 6 Pending Interrupt
bits : 6 - 6 (1 bit)
access : read-only

CHINT7 : Channel 7 Pending Interrupt
bits : 7 - 7 (1 bit)
access : read-only

CHINT8 : Channel 8 Pending Interrupt
bits : 8 - 8 (1 bit)
access : read-only

CHINT9 : Channel 9 Pending Interrupt
bits : 9 - 9 (1 bit)
access : read-only

CHINT10 : Channel 10 Pending Interrupt
bits : 10 - 10 (1 bit)
access : read-only

CHINT11 : Channel 11 Pending Interrupt
bits : 11 - 11 (1 bit)
access : read-only


BUSYCH

Busy Channels
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUSYCH BUSYCH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSYCH0 BUSYCH1 BUSYCH2 BUSYCH3 BUSYCH4 BUSYCH5 BUSYCH6 BUSYCH7 BUSYCH8 BUSYCH9 BUSYCH10 BUSYCH11

BUSYCH0 : Busy Channel 0
bits : 0 - 0 (1 bit)
access : read-only

BUSYCH1 : Busy Channel 1
bits : 1 - 1 (1 bit)
access : read-only

BUSYCH2 : Busy Channel 2
bits : 2 - 2 (1 bit)
access : read-only

BUSYCH3 : Busy Channel 3
bits : 3 - 3 (1 bit)
access : read-only

BUSYCH4 : Busy Channel 4
bits : 4 - 4 (1 bit)
access : read-only

BUSYCH5 : Busy Channel 5
bits : 5 - 5 (1 bit)
access : read-only

BUSYCH6 : Busy Channel 6
bits : 6 - 6 (1 bit)
access : read-only

BUSYCH7 : Busy Channel 7
bits : 7 - 7 (1 bit)
access : read-only

BUSYCH8 : Busy Channel 8
bits : 8 - 8 (1 bit)
access : read-only

BUSYCH9 : Busy Channel 9
bits : 9 - 9 (1 bit)
access : read-only

BUSYCH10 : Busy Channel 10
bits : 10 - 10 (1 bit)
access : read-only

BUSYCH11 : Busy Channel 11
bits : 11 - 11 (1 bit)
access : read-only


PENDCH

Pending Channels
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PENDCH PENDCH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PENDCH0 PENDCH1 PENDCH2 PENDCH3 PENDCH4 PENDCH5 PENDCH6 PENDCH7 PENDCH8 PENDCH9 PENDCH10 PENDCH11

PENDCH0 : Pending Channel 0
bits : 0 - 0 (1 bit)
access : read-only

PENDCH1 : Pending Channel 1
bits : 1 - 1 (1 bit)
access : read-only

PENDCH2 : Pending Channel 2
bits : 2 - 2 (1 bit)
access : read-only

PENDCH3 : Pending Channel 3
bits : 3 - 3 (1 bit)
access : read-only

PENDCH4 : Pending Channel 4
bits : 4 - 4 (1 bit)
access : read-only

PENDCH5 : Pending Channel 5
bits : 5 - 5 (1 bit)
access : read-only

PENDCH6 : Pending Channel 6
bits : 6 - 6 (1 bit)
access : read-only

PENDCH7 : Pending Channel 7
bits : 7 - 7 (1 bit)
access : read-only

PENDCH8 : Pending Channel 8
bits : 8 - 8 (1 bit)
access : read-only

PENDCH9 : Pending Channel 9
bits : 9 - 9 (1 bit)
access : read-only

PENDCH10 : Pending Channel 10
bits : 10 - 10 (1 bit)
access : read-only

PENDCH11 : Pending Channel 11
bits : 11 - 11 (1 bit)
access : read-only


ACTIVE

Active Channel and Levels
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ACTIVE ACTIVE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVLEX0 LVLEX1 LVLEX2 LVLEX3 ID ABUSY BTCNT

LVLEX0 : Level 0 Channel Trigger Request Executing
bits : 0 - 0 (1 bit)
access : read-only

LVLEX1 : Level 1 Channel Trigger Request Executing
bits : 1 - 1 (1 bit)
access : read-only

LVLEX2 : Level 2 Channel Trigger Request Executing
bits : 2 - 2 (1 bit)
access : read-only

LVLEX3 : Level 3 Channel Trigger Request Executing
bits : 3 - 3 (1 bit)
access : read-only

ID : Active Channel ID
bits : 8 - 12 (5 bit)
access : read-only

ABUSY : Active Channel Busy
bits : 15 - 15 (1 bit)
access : read-only

BTCNT : Active Channel Block Transfer Count
bits : 16 - 31 (16 bit)
access : read-only


BASEADDR

Descriptor Memory Section Base Address
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BASEADDR BASEADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASEADDR

BASEADDR : Descriptor Memory Base Address
bits : 0 - 31 (32 bit)


WRBADDR

Write-Back Memory Section Base Address
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRBADDR WRBADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRBADDR

WRBADDR : Write-Back Memory Base Address
bits : 0 - 31 (32 bit)


CHID

Channel ID
address_offset : 0x3F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID CHID read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ID

ID : Channel ID
bits : 0 - 3 (4 bit)


CRCDATAIN

CRC Data Input
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRCDATAIN CRCDATAIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRCDATAIN

CRCDATAIN : CRC Data Input
bits : 0 - 31 (32 bit)


CHCTRLA

Channel Control A
address_offset : 0x40 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA CHCTRLA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SWRST ENABLE

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)


CHCTRLB

Channel Control B
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB CHCTRLB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVACT EVIE EVOE LVL TRIGSRC TRIGACT CMD

EVACT : Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 3 - 3 (1 bit)

EVOE : Channel Event Output Enable
bits : 4 - 4 (1 bit)

LVL : Channel Arbitration Level
bits : 5 - 6 (2 bit)

Enumeration: LVLSelect

0x0 : LVL0

Channel Priority Level 0

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

End of enumeration elements list.

TRIGSRC : Peripheral Trigger Source
bits : 8 - 13 (6 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 22 - 23 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BEAT

One trigger required for each beat transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

CMD : Software Command
bits : 24 - 25 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHINTENCLR

Channel Interrupt Enable Clear
address_offset : 0x4C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET

Channel Interrupt Enable Set
address_offset : 0x4D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG

Channel Interrupt Flag Status and Clear
address_offset : 0x4E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS

Channel Status
address_offset : 0x4F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Fetch Error
bits : 2 - 2 (1 bit)
access : read-only


CRCCHKSUM

CRC Checksum
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRCCHKSUM CRCCHKSUM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRCCHKSUM

CRCCHKSUM : CRC Checksum
bits : 0 - 31 (32 bit)


CRCSTATUS

CRC Status
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRCSTATUS CRCSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CRCBUSY CRCZERO

CRCBUSY : CRC Module Busy
bits : 0 - 0 (1 bit)

CRCZERO : CRC Zero
bits : 1 - 1 (1 bit)
access : read-only


DBGCTRL

Debug Control
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGCTRL DBGCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DBGRUN

DBGRUN : Debug Run
bits : 0 - 0 (1 bit)


QOSCTRL

QOS Control
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QOSCTRL QOSCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WRBQOS FQOS DQOS

WRBQOS : Write-Back Quality of Service
bits : 0 - 1 (2 bit)

Enumeration: WRBQOSSelect

0x0 : DISABLE

Background (no sensitive operation)

0x1 : LOW

Sensitive Bandwidth

0x2 : MEDIUM

Sensitive Latency

0x3 : HIGH

Critical Latency

End of enumeration elements list.

FQOS : Fetch Quality of Service
bits : 2 - 3 (2 bit)

Enumeration: FQOSSelect

0x0 : DISABLE

Background (no sensitive operation)

0x1 : LOW

Sensitive Bandwidth

0x2 : MEDIUM

Sensitive Latency

0x3 : HIGH

Critical Latency

End of enumeration elements list.

DQOS : Data Transfer Quality of Service
bits : 4 - 5 (2 bit)

Enumeration: DQOSSelect

0x0 : DISABLE

Background (no sensitive operation)

0x1 : LOW

Sensitive Bandwidth

0x2 : MEDIUM

Sensitive Latency

0x3 : HIGH

Critical Latency

End of enumeration elements list.



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