\n
address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
Control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
Status
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYNCBUSY : Synchronization Busy Status
bits : 7 - 7 (1 bit)
access : read-only
Generic Clock Control
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Generic Clock Selection ID
bits : 0 - 5 (6 bit)
Enumeration: IDSelect
0x0 : DFLL48
DFLL48
0x1 : FDPLL
FDPLL
0x2 : FDPLL32K
FDPLL32K
0x3 : WDT
WDT
0x4 : RTC
RTC
0x5 : EIC
EIC
0x7 : EVSYS_0
EVSYS_0
0x8 : EVSYS_1
EVSYS_1
0x9 : EVSYS_2
EVSYS_2
0xa : EVSYS_3
EVSYS_3
0xb : EVSYS_4
EVSYS_4
0xc : EVSYS_5
EVSYS_5
0xd : EVSYS_6
EVSYS_6
0xe : EVSYS_7
EVSYS_7
0xf : EVSYS_8
EVSYS_8
0x10 : EVSYS_9
EVSYS_9
0x11 : EVSYS_10
EVSYS_10
0x12 : EVSYS_11
EVSYS_11
0x13 : SERCOMX_SLOW
SERCOMX_SLOW
0x14 : SERCOM0_CORE
SERCOM0_CORE
0x15 : SERCOM1_CORE
SERCOM1_CORE
0x16 : SERCOM2_CORE
SERCOM2_CORE
0x17 : SERCOM3_CORE
SERCOM3_CORE
0x18 : SERCOM4_CORE
SERCOM4_CORE
0x19 : SERCOM5_CORE
SERCOM5_CORE
0x1a : TCC0_TCC1
TCC0_TCC1
0x1b : TCC2_TC3
TCC2_TC3
0x1c : TC4_TC5
TC4_TC5
0x1d : TC6_TC7
TC6_TC7
0x1e : ADC
ADC
0x1f : AC_DIG
AC_DIG
0x20 : AC_ANA
AC_ANA
0x21 : DAC
DAC
0x23 : I2S_0
I2S_0
0x24 : I2S_1
I2S_1
End of enumeration elements list.
GEN : Generic Clock Generator
bits : 8 - 11 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CLKEN : Clock Enable
bits : 14 - 14 (1 bit)
WRTLOCK : Write Lock
bits : 15 - 15 (1 bit)
Generic Clock Generator Control
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Generic Clock Generator Selection
bits : 0 - 3 (4 bit)
SRC : Source Select
bits : 8 - 12 (5 bit)
Enumeration: SRCSelect
0x0 : XOSC
XOSC oscillator output
0x1 : GCLKIN
Generator input pad
0x2 : GCLKGEN1
Generic clock generator 1 output
0x3 : OSCULP32K
OSCULP32K oscillator output
0x4 : OSC32K
OSC32K oscillator output
0x5 : XOSC32K
XOSC32K oscillator output
0x6 : OSC8M
OSC8M oscillator output
0x7 : DFLL48M
DFLL48M output
0x8 : FDPLL
FDPLL output
0x8 : DPLL96M
DPLL96M output
End of enumeration elements list.
GENEN : Generic Clock Generator Enable
bits : 16 - 16 (1 bit)
IDC : Improve Duty Cycle
bits : 17 - 17 (1 bit)
OOV : Output Off Value
bits : 18 - 18 (1 bit)
OE : Output Enable
bits : 19 - 19 (1 bit)
DIVSEL : Divide Selection
bits : 20 - 20 (1 bit)
RUNSTDBY : Run in Standby
bits : 21 - 21 (1 bit)
Generic Clock Generator Division
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Generic Clock Generator Selection
bits : 0 - 3 (4 bit)
DIV : Division Factor
bits : 8 - 23 (16 bit)
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