\n
address_offset : 0x0 Bytes (0x0)
size : 0x38 byte (0x0)
mem_usage : registers
protection :
MPU Type Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEPARATE : Separate instructions and data address regions
bits : 0 - 0 (1 bit)
DREGION : Number of MPU data regions
bits : 8 - 15 (8 bit)
MPU Region Limit Address Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Region enable
bits : 0 - 0 (1 bit)
AttrInd : Attribute Index
bits : 1 - 3 (3 bit)
LIMIT : Limit address
bits : 5 - 31 (27 bit)
MPU Memory Attribute Indirection Register 0
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Attr0 : Attribute of MPU region 0
bits : 0 - 7 (8 bit)
Attr1 : Attribute of MPU region 1
bits : 8 - 15 (8 bit)
Attr2 : Attribute of MPU region 2
bits : 16 - 23 (8 bit)
Attr3 : Attribute of MPU region 3
bits : 24 - 31 (8 bit)
MPU Memory Attribute Indirection Register 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Attr4 : Memory attribute encoding for MPU regions with AttrIndx 4
bits : 0 - 7 (8 bit)
Attr5 : Memory attribute encoding for MPU regions with AttrIndx 5
bits : 8 - 15 (8 bit)
Attr6 : Memory attribute encoding for MPU regions with AttrIndx 6
bits : 16 - 23 (8 bit)
Attr7 : Memory attribute encoding for MPU regions with AttrIndx 7
bits : 24 - 31 (8 bit)
MPU Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : MPU enable
bits : 0 - 0 (1 bit)
HFNMIENA : HardFault, NMI enable
bits : 1 - 1 (1 bit)
PRIVDEFENA : Privileged default enable
bits : 2 - 2 (1 bit)
MPU Region Number Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGION : Selected region number
bits : 0 - 7 (8 bit)
MPU Region Base Address Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XN : Execute Never
bits : 0 - 0 (1 bit)
Enumeration: XNSelect
0x0 : 0x0
Execution only permitted if read permitted
0x1 : 0x1
Execution not permitted
End of enumeration elements list.
AP : Access permissions
bits : 1 - 2 (2 bit)
Enumeration: APSelect
0x0 : 0x0
Read/write by privileged code only
0x1 : 0x1
Read/write by any privilege level
0x2 : 0x2
Read-only by privileged code only
0x3 : 0x3
Read-only by any privilege level
0 : RWPRIV
Read/write by privileged code only
1 : RWANY
Read/write by any privilege level
2 : RPRIV
Read-only by privileged code only
3 : RANY
Read-only by any privilege level
End of enumeration elements list.
SH : Shareability
bits : 3 - 4 (2 bit)
Enumeration: SHSelect
0x0 : NON
Non-shareable
2 : OUTER
Outer shareable
3 : INNER
Inner shareable
0 : NO
Non-shareable
End of enumeration elements list.
BASE : Base address
bits : 5 - 31 (27 bit)
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