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NVIC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xE04 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ISER[0]

ISER0

ISER4

ICER[0]

ISPR0

ISPR1

ISPR2

ISPR3

ISPR4

IP[4]

IP[5]

ISER[3]

ICPR0

IP[6]

ICER[1]

ICPR1

ICPR2

ICPR3

ICPR4

IP[7]

IP[8]

ISPR[0]

IABR0

IABR1

IABR2

ICER[2]

IABR3

IABR4

IP[9]

IP[10]

IP[11]

ISER[4]

ICER[3]

IP[12]

IP[13]

ICPR[0]

IP0

IP1

IP2

IP3

ISPR[1]

IP4

IP5

IP6

IP[14]

IP7

IP8

IP9

IP10

IP11

IP12

IP13

IP14

IP15

IP16

IP17

IP18

IP19

IP20

IP21

IP22

IP23

IP24

IP25

IP26

IP27

IP28

IP29

IP30

IP31

IP32

IP33

IP34

ICER[4]

IP[15]

IP[16]

IP[17]

IP[18]

IP[19]

ISER[1]

ISER1

IABR[0]

ISPR[2]

IP[20]

IP[21]

ICPR[1]

IP[22]

IP[23]

IP[24]

ISPR[3]

IP[25]

IP[26]

IP[27]

IP[28]

IP[29]

IP[0]

IABR[1]

ICPR[2]

IP[30]

ISPR[4]

IP[31]

IP[32]

IP[33]

IP[34]

ICPR[3]

ISER2

ICER0

IABR[2]

ICER1

ICER2

ICER3

ICER4

IP[1]

ICPR[4]

IABR[3]

ISER[2]

ISER3

IP[2]

IABR[4]

STIR

IP[3]


ISER[0]

Interrupt Set Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER[0] ISER[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt set enable bits
bits : 0 - 31 (32 bit)


ISER0

Interrupt Set Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER0 ISER0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt set enable bits
bits : 0 - 31 (32 bit)


ISER4

Interrupt Set Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER4 ISER4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt set enable bits
bits : 0 - 31 (32 bit)


ICER[0]

Interrupt Clear Enable Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER[0] ICER[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA

CLRENA : Interrupt clear-enable bits
bits : 0 - 31 (32 bit)


ISPR0

Interrupt Set Pending Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR0 ISPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Interrupt set-pending bits
bits : 0 - 31 (32 bit)


ISPR1

Interrupt Set Pending Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR1 ISPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Interrupt set-pending bits
bits : 0 - 31 (32 bit)


ISPR2

Interrupt Set Pending Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR2 ISPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Interrupt set-pending bits
bits : 0 - 31 (32 bit)


ISPR3

Interrupt Set Pending Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR3 ISPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Interrupt set-pending bits
bits : 0 - 31 (32 bit)


ISPR4

Interrupt Set Pending Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR4 ISPR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Interrupt set-pending bits
bits : 0 - 31 (32 bit)


IP[4]

Interrupt Priority Register n
address_offset : 0x120A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[4] IP[4] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP[5]

Interrupt Priority Register n
address_offset : 0x150F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[5] IP[5] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


ISER[3]

Interrupt Set Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER[3] ISER[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt set enable bits
bits : 0 - 31 (32 bit)


ICPR0

Interrupt Clear Pending Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR0 ICPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND

CLRPEND : Interrupt clear-pending bits
bits : 0 - 31 (32 bit)


IP[6]

Interrupt Priority Register n
address_offset : 0x1815 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[6] IP[6] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


ICER[1]

Interrupt Clear Enable Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER[1] ICER[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA

CLRENA : Interrupt clear-enable bits
bits : 0 - 31 (32 bit)


ICPR1

Interrupt Clear Pending Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR1 ICPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND

CLRPEND : Interrupt clear-pending bits
bits : 0 - 31 (32 bit)


ICPR2

Interrupt Clear Pending Register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR2 ICPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND

CLRPEND : Interrupt clear-pending bits
bits : 0 - 31 (32 bit)


ICPR3

Interrupt Clear Pending Register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR3 ICPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND

CLRPEND : Interrupt clear-pending bits
bits : 0 - 31 (32 bit)


ICPR4

Interrupt Clear Pending Register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR4 ICPR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND

CLRPEND : Interrupt clear-pending bits
bits : 0 - 31 (32 bit)


IP[7]

Interrupt Priority Register n
address_offset : 0x1B1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[7] IP[7] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP[8]

Interrupt Priority Register n
address_offset : 0x1E24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[8] IP[8] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


ISPR[0]

Interrupt Set Pending Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR[0] ISPR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Interrupt set-pending bits
bits : 0 - 31 (32 bit)


IABR0

Interrupt Active Bit Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IABR0 IABR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : Interrupt active bits
bits : 0 - 31 (32 bit)


IABR1

Interrupt Active Bit Register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IABR1 IABR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : Interrupt active bits
bits : 0 - 31 (32 bit)


IABR2

Interrupt Active Bit Register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IABR2 IABR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : Interrupt active bits
bits : 0 - 31 (32 bit)


ICER[2]

Interrupt Clear Enable Register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER[2] ICER[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA

CLRENA : Interrupt clear-enable bits
bits : 0 - 31 (32 bit)


IABR3

Interrupt Active Bit Register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IABR3 IABR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : Interrupt active bits
bits : 0 - 31 (32 bit)


IABR4

Interrupt Active Bit Register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IABR4 IABR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : Interrupt active bits
bits : 0 - 31 (32 bit)


IP[9]

Interrupt Priority Register n
address_offset : 0x212D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[9] IP[9] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP[10]

Interrupt Priority Register n
address_offset : 0x2437 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[10] IP[10] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP[11]

Interrupt Priority Register n
address_offset : 0x2742 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[11] IP[11] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


ISER[4]

Interrupt Set Enable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER[4] ISER[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt set enable bits
bits : 0 - 31 (32 bit)


ICER[3]

Interrupt Clear Enable Register
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER[3] ICER[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA

CLRENA : Interrupt clear-enable bits
bits : 0 - 31 (32 bit)


IP[12]

Interrupt Priority Register n
address_offset : 0x2A4E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[12] IP[12] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP[13]

Interrupt Priority Register n
address_offset : 0x2D5B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[13] IP[13] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


ICPR[0]

Interrupt Clear Pending Register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR[0] ICPR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND

CLRPEND : Interrupt clear-pending bits
bits : 0 - 31 (32 bit)


IP0

Interrupt Priority Register n
address_offset : 0x300 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP0 IP0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP1

Interrupt Priority Register n
address_offset : 0x301 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP1 IP1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP2

Interrupt Priority Register n
address_offset : 0x302 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP2 IP2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP3

Interrupt Priority Register n
address_offset : 0x303 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP3 IP3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


ISPR[1]

Interrupt Set Pending Register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR[1] ISPR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Interrupt set-pending bits
bits : 0 - 31 (32 bit)


IP4

Interrupt Priority Register n
address_offset : 0x304 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP4 IP4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP5

Interrupt Priority Register n
address_offset : 0x305 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP5 IP5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP6

Interrupt Priority Register n
address_offset : 0x306 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP6 IP6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP[14]

Interrupt Priority Register n
address_offset : 0x3069 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[14] IP[14] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP7

Interrupt Priority Register n
address_offset : 0x307 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP7 IP7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP8

Interrupt Priority Register n
address_offset : 0x308 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP8 IP8 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP9

Interrupt Priority Register n
address_offset : 0x309 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP9 IP9 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP10

Interrupt Priority Register n
address_offset : 0x30A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP10 IP10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP11

Interrupt Priority Register n
address_offset : 0x30B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP11 IP11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP12

Interrupt Priority Register n
address_offset : 0x30C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP12 IP12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP13

Interrupt Priority Register n
address_offset : 0x30D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP13 IP13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP14

Interrupt Priority Register n
address_offset : 0x30E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP14 IP14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP15

Interrupt Priority Register n
address_offset : 0x30F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP15 IP15 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP16

Interrupt Priority Register n
address_offset : 0x310 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP16 IP16 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP17

Interrupt Priority Register n
address_offset : 0x311 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP17 IP17 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP18

Interrupt Priority Register n
address_offset : 0x312 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP18 IP18 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP19

Interrupt Priority Register n
address_offset : 0x313 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP19 IP19 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP20

Interrupt Priority Register n
address_offset : 0x314 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP20 IP20 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP21

Interrupt Priority Register n
address_offset : 0x315 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP21 IP21 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP22

Interrupt Priority Register n
address_offset : 0x316 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP22 IP22 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP23

Interrupt Priority Register n
address_offset : 0x317 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP23 IP23 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP24

Interrupt Priority Register n
address_offset : 0x318 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP24 IP24 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP25

Interrupt Priority Register n
address_offset : 0x319 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP25 IP25 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP26

Interrupt Priority Register n
address_offset : 0x31A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP26 IP26 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP27

Interrupt Priority Register n
address_offset : 0x31B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP27 IP27 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP28

Interrupt Priority Register n
address_offset : 0x31C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP28 IP28 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP29

Interrupt Priority Register n
address_offset : 0x31D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP29 IP29 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP30

Interrupt Priority Register n
address_offset : 0x31E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP30 IP30 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP31

Interrupt Priority Register n
address_offset : 0x31F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP31 IP31 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP32

Interrupt Priority Register n
address_offset : 0x320 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP32 IP32 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP33

Interrupt Priority Register n
address_offset : 0x321 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP33 IP33 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP34

Interrupt Priority Register n
address_offset : 0x322 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP34 IP34 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


ICER[4]

Interrupt Clear Enable Register
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER[4] ICER[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA

CLRENA : Interrupt clear-enable bits
bits : 0 - 31 (32 bit)


IP[15]

Interrupt Priority Register n
address_offset : 0x3378 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[15] IP[15] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP[16]

Interrupt Priority Register n
address_offset : 0x3688 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[16] IP[16] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP[17]

Interrupt Priority Register n
address_offset : 0x3999 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[17] IP[17] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP[18]

Interrupt Priority Register n
address_offset : 0x3CAB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[18] IP[18] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP[19]

Interrupt Priority Register n
address_offset : 0x3FBE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[19] IP[19] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


ISER[1]

Interrupt Set Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER[1] ISER[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt set enable bits
bits : 0 - 31 (32 bit)


ISER1

Interrupt Set Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER1 ISER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt set enable bits
bits : 0 - 31 (32 bit)


IABR[0]

Interrupt Active Bit Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IABR[0] IABR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : Interrupt active bits
bits : 0 - 31 (32 bit)


ISPR[2]

Interrupt Set Pending Register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR[2] ISPR[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Interrupt set-pending bits
bits : 0 - 31 (32 bit)


IP[20]

Interrupt Priority Register n
address_offset : 0x42D2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[20] IP[20] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP[21]

Interrupt Priority Register n
address_offset : 0x45E7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[21] IP[21] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


ICPR[1]

Interrupt Clear Pending Register
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR[1] ICPR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND

CLRPEND : Interrupt clear-pending bits
bits : 0 - 31 (32 bit)


IP[22]

Interrupt Priority Register n
address_offset : 0x48FD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[22] IP[22] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP[23]

Interrupt Priority Register n
address_offset : 0x4C14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[23] IP[23] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP[24]

Interrupt Priority Register n
address_offset : 0x4F2C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[24] IP[24] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


ISPR[3]

Interrupt Set Pending Register
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR[3] ISPR[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Interrupt set-pending bits
bits : 0 - 31 (32 bit)


IP[25]

Interrupt Priority Register n
address_offset : 0x5245 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[25] IP[25] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP[26]

Interrupt Priority Register n
address_offset : 0x555F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[26] IP[26] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP[27]

Interrupt Priority Register n
address_offset : 0x587A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[27] IP[27] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP[28]

Interrupt Priority Register n
address_offset : 0x5B96 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[28] IP[28] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP[29]

Interrupt Priority Register n
address_offset : 0x5EB3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[29] IP[29] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP[0]

Interrupt Priority Register n
address_offset : 0x600 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[0] IP[0] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IABR[1]

Interrupt Active Bit Register
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IABR[1] IABR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : Interrupt active bits
bits : 0 - 31 (32 bit)


ICPR[2]

Interrupt Clear Pending Register
address_offset : 0x60C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR[2] ICPR[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND

CLRPEND : Interrupt clear-pending bits
bits : 0 - 31 (32 bit)


IP[30]

Interrupt Priority Register n
address_offset : 0x61D1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[30] IP[30] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


ISPR[4]

Interrupt Set Pending Register
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR[4] ISPR[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Interrupt set-pending bits
bits : 0 - 31 (32 bit)


IP[31]

Interrupt Priority Register n
address_offset : 0x64F0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[31] IP[31] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP[32]

Interrupt Priority Register n
address_offset : 0x6810 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[32] IP[32] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP[33]

Interrupt Priority Register n
address_offset : 0x6B31 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[33] IP[33] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IP[34]

Interrupt Priority Register n
address_offset : 0x6E53 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[34] IP[34] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


ICPR[3]

Interrupt Clear Pending Register
address_offset : 0x798 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR[3] ICPR[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND

CLRPEND : Interrupt clear-pending bits
bits : 0 - 31 (32 bit)


ISER2

Interrupt Set Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER2 ISER2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt set enable bits
bits : 0 - 31 (32 bit)


ICER0

Interrupt Clear Enable Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER0 ICER0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA

CLRENA : Interrupt clear-enable bits
bits : 0 - 31 (32 bit)


IABR[2]

Interrupt Active Bit Register
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IABR[2] IABR[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : Interrupt active bits
bits : 0 - 31 (32 bit)


ICER1

Interrupt Clear Enable Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER1 ICER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA

CLRENA : Interrupt clear-enable bits
bits : 0 - 31 (32 bit)


ICER2

Interrupt Clear Enable Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER2 ICER2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA

CLRENA : Interrupt clear-enable bits
bits : 0 - 31 (32 bit)


ICER3

Interrupt Clear Enable Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER3 ICER3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA

CLRENA : Interrupt clear-enable bits
bits : 0 - 31 (32 bit)


ICER4

Interrupt Clear Enable Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER4 ICER4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA

CLRENA : Interrupt clear-enable bits
bits : 0 - 31 (32 bit)


IP[1]

Interrupt Priority Register n
address_offset : 0x901 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[1] IP[1] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


ICPR[4]

Interrupt Clear Pending Register
address_offset : 0x928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR[4] ICPR[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND

CLRPEND : Interrupt clear-pending bits
bits : 0 - 31 (32 bit)


IABR[3]

Interrupt Active Bit Register
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IABR[3] IABR[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : Interrupt active bits
bits : 0 - 31 (32 bit)


ISER[2]

Interrupt Set Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER[2] ISER[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt set enable bits
bits : 0 - 31 (32 bit)


ISER3

Interrupt Set Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER3 ISER3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt set enable bits
bits : 0 - 31 (32 bit)


IP[2]

Interrupt Priority Register n
address_offset : 0xC03 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[2] IP[2] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)


IABR[4]

Interrupt Active Bit Register
address_offset : 0xC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IABR[4] IABR[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : Interrupt active bits
bits : 0 - 31 (32 bit)


STIR

Software Trigger Interrupt Register
address_offset : 0xE00 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

STIR STIR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTID

INTID : Interrupt ID to trigger
bits : 0 - 8 (9 bit)


IP[3]

Interrupt Priority Register n
address_offset : 0xF06 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP[3] IP[3] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of interrupt n
bits : 0 - 2 (3 bit)



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