Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x48 byte (0x0)
mem_usage : registers
protection : not protected
Control A
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Enable
bits : 1 - 1 (1 bit)
LASTXFER : Last Transfer
bits : 24 - 24 (1 bit)
Transmit Data
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Transmit Data
bits : 0 - 15 (16 bit)
Interrupt Enable Clear
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXC : Receive Data Register Full Interrupt Disable
bits : 0 - 0 (1 bit)
DRE : Transmit Data Register Empty Interrupt Disable
bits : 1 - 1 (1 bit)
TXC : Transmission Complete Interrupt Disable
bits : 2 - 2 (1 bit)
ERROR : Overrun Error Interrupt Disable
bits : 3 - 3 (1 bit)
CSRISE : Chip Select Rise Interrupt Disable
bits : 8 - 8 (1 bit)
INSTREND : Instruction End Interrupt Disable
bits : 10 - 10 (1 bit)
Interrupt Enable Set
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXC : Receive Data Register Full Interrupt Enable
bits : 0 - 0 (1 bit)
DRE : Transmit Data Register Empty Interrupt Enable
bits : 1 - 1 (1 bit)
TXC : Transmission Complete Interrupt Enable
bits : 2 - 2 (1 bit)
ERROR : Overrun Error Interrupt Enable
bits : 3 - 3 (1 bit)
CSRISE : Chip Select Rise Interrupt Enable
bits : 8 - 8 (1 bit)
INSTREND : Instruction End Interrupt Enable
bits : 10 - 10 (1 bit)
Interrupt Flag Status and Clear
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXC : Receive Data Register Full
bits : 0 - 0 (1 bit)
DRE : Transmit Data Register Empty
bits : 1 - 1 (1 bit)
TXC : Transmission Complete
bits : 2 - 2 (1 bit)
ERROR : Overrun Error
bits : 3 - 3 (1 bit)
CSRISE : Chip Select Rise
bits : 8 - 8 (1 bit)
INSTREND : Instruction End
bits : 10 - 10 (1 bit)
Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enable
bits : 1 - 1 (1 bit)
CSSTATUS : Chip Select
bits : 9 - 9 (1 bit)
Instruction Address
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Instruction Address
bits : 0 - 31 (32 bit)
Instruction Code
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INSTR : Instruction Code
bits : 0 - 7 (8 bit)
OPTCODE : Option Code
bits : 16 - 23 (8 bit)
Instruction Frame
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Instruction Code, Address, Option Code and Data Width
bits : 0 - 2 (3 bit)
Enumeration: WIDTHSelect
0x0 : SINGLE_BIT_SPI
Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI
0x1 : DUAL_OUTPUT
Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI
0x2 : QUAD_OUTPUT
Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI
0x3 : DUAL_IO
Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI
0x4 : QUAD_IO
Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI
0x5 : DUAL_CMD
Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI
0x6 : QUAD_CMD
Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI
End of enumeration elements list.
INSTREN : Instruction Enable
bits : 4 - 4 (1 bit)
ADDREN : Address Enable
bits : 5 - 5 (1 bit)
OPTCODEEN : Option Enable
bits : 6 - 6 (1 bit)
DATAEN : Data Enable
bits : 7 - 7 (1 bit)
OPTCODELEN : Option Code Length
bits : 8 - 9 (2 bit)
Enumeration: OPTCODELENSelect
0x0 : 1BIT
1-bit length option code
0x1 : 2BITS
2-bits length option code
0x2 : 4BITS
4-bits length option code
0x3 : 8BITS
8-bits length option code
End of enumeration elements list.
ADDRLEN : Address Length
bits : 10 - 10 (1 bit)
Enumeration: ADDRLENSelect
0 : 24BITS
24-bits address length
1 : 32BITS
32-bits address length
End of enumeration elements list.
TFRTYPE : Data Transfer Type
bits : 12 - 13 (2 bit)
Enumeration: TFRTYPESelect
0x0 : READ
Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible.
0x1 : READMEMORY
Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible.
0x2 : WRITE
Write transfer into the serial memory.Scrambling is not performed.
0x3 : WRITEMEMORY
Write data transfer into the serial memory.If enabled, scrambling is performed.
End of enumeration elements list.
CRMODE : Continuous Read Mode
bits : 14 - 14 (1 bit)
DDREN : Double Data Rate Enable
bits : 15 - 15 (1 bit)
DUMMYLEN : Dummy Cycles Length
bits : 16 - 20 (5 bit)
Control B
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Serial Memory Mode
bits : 0 - 0 (1 bit)
Enumeration: MODESelect
0 : SPI
SPI operating mode
1 : MEMORY
Serial Memory operating mode
End of enumeration elements list.
LOOPEN : Local Loopback Enable
bits : 1 - 1 (1 bit)
WDRBT : Wait Data Read Before Transfer
bits : 2 - 2 (1 bit)
SMEMREG : Serial Memory reg
bits : 3 - 3 (1 bit)
CSMODE : Chip Select Mode
bits : 4 - 5 (2 bit)
Enumeration: CSMODESelect
0x0 : NORELOAD
The chip select is deasserted if TD has not been reloaded before the end of the current transfer.
0x1 : LASTXFER
The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred.
0x2 : SYSTEMATICALLY
The chip select is deasserted systematically after each transfer.
End of enumeration elements list.
DATALEN : Data Length
bits : 8 - 11 (4 bit)
Enumeration: DATALENSelect
0x0 : 8BITS
8-bits transfer
0x1 : 9BITS
9 bits transfer
0x2 : 10BITS
10-bits transfer
0x3 : 11BITS
11-bits transfer
0x4 : 12BITS
12-bits transfer
0x5 : 13BITS
13-bits transfer
0x6 : 14BITS
14-bits transfer
0x7 : 15BITS
15-bits transfer
0x8 : 16BITS
16-bits transfer
End of enumeration elements list.
DLYBCT : Delay Between Consecutive Transfers
bits : 16 - 23 (8 bit)
DLYCS : Minimum Inactive CS Delay
bits : 24 - 31 (8 bit)
Scrambling Mode
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Scrambling/Unscrambling Enable
bits : 0 - 0 (1 bit)
RANDOMDIS : Scrambling/Unscrambling Random Value Disable
bits : 1 - 1 (1 bit)
Scrambling Key
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : Scrambling User Key
bits : 0 - 31 (32 bit)
Baud Rate
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPOL : Clock Polarity
bits : 0 - 0 (1 bit)
CPHA : Clock Phase
bits : 1 - 1 (1 bit)
BAUD : Serial Clock Baud Rate
bits : 8 - 15 (8 bit)
DLYBS : Delay Before SCK
bits : 16 - 23 (8 bit)
Receive Data
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Receive Data
bits : 0 - 15 (16 bit)
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