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USB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DEVICE - CTRLA

HOST - CTRLA

CTRLA

EPCFG

PCFG

DEVICE - FNUM

HOST - FNUM

FNUM

DEVICE_ENDPOINT[0]-EPCFG

HOST_PIPE[0]-PCFG

EPCFG0

PCFG0

HOST_PIPE[0]-BINTERVAL

BINTERVAL0

DEVICE_ENDPOINT[0]-EPSTATUSCLR

HOST_PIPE[0]-PSTATUSCLR

EPSTATUSCLR0

PSTATUSCLR0

DEVICE_ENDPOINT[0]-EPSTATUSSET

HOST_PIPE[0]-PSTATUSSET

EPSTATUSSET0

PSTATUSSET0

DEVICE_ENDPOINT[0]-EPSTATUS

HOST_PIPE[0]-PSTATUS

EPSTATUS0

PSTATUS0

DEVICE_ENDPOINT[0]-EPINTFLAG

HOST_PIPE[0]-PINTFLAG

EPINTFLAG0

PINTFLAG0

DEVICE_ENDPOINT[0]-EPINTENCLR

HOST_PIPE[0]-PINTENCLR

EPINTENCLR0

PINTENCLR0

DEVICE_ENDPOINT[0]-EPINTENSET

HOST_PIPE[0]-PINTENSET

EPINTENSET0

PINTENSET0

HOST - FLENHIGH

FLENHIGH

EPCFG1

PCFG1

BINTERVAL1

EPSTATUSCLR1

PSTATUSCLR1

EPSTATUSSET1

PSTATUSSET1

EPSTATUS1

PSTATUS1

EPINTFLAG1

PINTFLAG1

EPINTENCLR1

PINTENCLR1

EPINTENSET1

PINTENSET1

DEVICE - INTENCLR

HOST - INTENCLR

INTENCLR

EPCFG2

PCFG2

BINTERVAL2

EPSTATUSCLR2

PSTATUSCLR2

EPSTATUSSET2

PSTATUSSET2

EPSTATUS2

PSTATUS2

EPINTFLAG2

PINTFLAG2

EPINTENCLR2

PINTENCLR2

EPINTENSET2

PINTENSET2

EPCFG3

PCFG3

BINTERVAL3

EPSTATUSCLR3

PSTATUSCLR3

EPSTATUSSET3

PSTATUSSET3

EPSTATUS3

PSTATUS3

EPINTFLAG3

PINTFLAG3

EPINTENCLR3

PINTENCLR3

EPINTENSET3

PINTENSET3

DEVICE - INTENSET

HOST - INTENSET

INTENSET

EPCFG4

PCFG4

BINTERVAL4

EPSTATUSCLR4

PSTATUSCLR4

EPSTATUSSET4

PSTATUSSET4

EPSTATUS4

PSTATUS4

EPINTFLAG4

PINTFLAG4

EPINTENCLR4

PINTENCLR4

EPINTENSET4

PINTENSET4

EPCFG5

PCFG5

BINTERVAL5

EPSTATUSCLR5

PSTATUSCLR5

EPSTATUSSET5

PSTATUSSET5

EPSTATUS5

PSTATUS5

EPINTFLAG5

PINTFLAG5

EPINTENCLR5

PINTENCLR5

EPINTENSET5

PINTENSET5

DEVICE - INTFLAG

HOST - INTFLAG

INTFLAG

EPCFG6

PCFG6

BINTERVAL6

EPSTATUSCLR6

PSTATUSCLR6

EPSTATUSSET6

PSTATUSSET6

EPSTATUS6

PSTATUS6

EPINTFLAG6

PINTFLAG6

EPINTENCLR6

PINTENCLR6

EPINTENSET6

PINTENSET6

EPCFG7

PCFG7

BINTERVAL7

EPSTATUSCLR7

PSTATUSCLR7

EPSTATUSSET7

PSTATUSSET7

EPSTATUS7

PSTATUS7

EPINTFLAG7

PINTFLAG7

EPINTENCLR7

PINTENCLR7

EPINTENSET7

PINTENSET7

DEVICE - SYNCBUSY

HOST - SYNCBUSY

SYNCBUSY

DEVICE - EPINTSMRY

HOST - PINTSMRY

EPINTSMRY

PINTSMRY

DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG

HOST_PIPE[1]-HOST_PIPE[0]-PCFG

HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL

DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR

HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR

DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET

HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET

DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS

HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS

DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG

HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG

DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR

HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR

DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET

HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET

DEVICE - DESCADD

HOST - DESCADD

DESCADD

DEVICE - PADCAL

HOST - PADCAL

PADCAL

DEVICE - QOSCTRL

HOST - QOSCTRL

QOSCTRL

BINTERVAL

DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG

HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG

HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL

DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR

HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR

DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET

HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET

DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS

HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS

DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG

HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG

DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR

HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR

DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET

HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET

EPSTATUSCLR

PSTATUSCLR

DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG

HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG

HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL

DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR

HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR

DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET

HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET

DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS

HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS

DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG

HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG

DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR

HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR

DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET

HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET

EPSTATUSSET

PSTATUSSET

EPSTATUS

PSTATUS

DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG

HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG

HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL

DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR

HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR

DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET

HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET

DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS

HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS

DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG

HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG

DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR

HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR

DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET

HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET

EPINTFLAG

PINTFLAG

DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG

HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG

HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL

DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR

HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR

DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET

HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET

DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS

HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS

DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG

HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG

DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR

HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR

DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET

HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET

DEVICE - CTRLB

HOST - CTRLB

CTRLB

EPINTENCLR

PINTENCLR

EPINTENSET

PINTENSET

DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG

HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG

HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL

DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR

HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR

DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET

HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET

DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS

HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS

DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG

HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG

DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR

HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR

DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET

HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET

DEVICE - DADD

HOST - HSOFC

DADD

HSOFC

DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG

HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG

HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL

DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR

HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR

DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET

HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET

DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS

HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS

DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG

HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG

DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR

HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR

DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET

HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET

DEVICE - STATUS

HOST - STATUS

STATUS

DEVICE - FSMSTATUS

HOST - FSMSTATUS

FSMSTATUS


DEVICE - CTRLA

USB is Device - - Control A
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE - CTRLA DEVICE - CTRLA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY MODE

SWRST : Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Run in Standby Mode
bits : 2 - 2 (1 bit)

MODE : Operating Mode
bits : 7 - 7 (1 bit)

Enumeration: MODESelect

0 : DEVICE

Device Mode

1 : HOST

Host Mode

End of enumeration elements list.


HOST - CTRLA

USB is Host - - Control A
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST - CTRLA HOST - CTRLA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY MODE

SWRST : Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Run in Standby Mode
bits : 2 - 2 (1 bit)

MODE : Operating Mode
bits : 7 - 7 (1 bit)

Enumeration: MODESelect

0 : DEVICE

Device Mode

1 : HOST

Host Mode

End of enumeration elements list.


CTRLA

Control A
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLA CTRLA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY MODE

SWRST : Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Run in Standby Mode
bits : 2 - 2 (1 bit)

MODE : Operating Mode
bits : 7 - 7 (1 bit)

Enumeration: MODESelect

0 : DEVICE

Device Mode

1 : HOST

Host Mode

End of enumeration elements list.


EPCFG

DEVICE_ENDPOINT End Point Configuration
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPCFG EPCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPTYPE0 EPTYPE1 NYETDIS

EPTYPE0 : End Point Type0
bits : 0 - 2 (3 bit)

EPTYPE1 : End Point Type1
bits : 4 - 6 (3 bit)

NYETDIS : NYET Token Disable
bits : 7 - 7 (1 bit)


PCFG

HOST_PIPE End Point Configuration
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFG PCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PTOKEN BK PTYPE

PTOKEN : Pipe Token
bits : 0 - 1 (2 bit)

BK : Pipe Bank
bits : 2 - 2 (1 bit)

PTYPE : Pipe Type
bits : 3 - 5 (3 bit)


DEVICE - FNUM

USB is Device - - DEVICE Device Frame Number
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE - FNUM DEVICE - FNUM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFNUM FNUM FNCERR

MFNUM : Micro Frame Number
bits : 0 - 2 (3 bit)

FNUM : Frame Number
bits : 3 - 13 (11 bit)

FNCERR : Frame Number CRC Error
bits : 15 - 15 (1 bit)


HOST - FNUM

USB is Host - - HOST Host Frame Number
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST - FNUM HOST - FNUM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFNUM FNUM

MFNUM : Micro Frame Number
bits : 0 - 2 (3 bit)

FNUM : Frame Number
bits : 3 - 13 (11 bit)


FNUM

DEVICE Device Frame Number
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FNUM FNUM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFNUM FNUM FNCERR

MFNUM : Micro Frame Number
bits : 0 - 2 (3 bit)
access : read-only

FNUM : Frame Number
bits : 3 - 13 (11 bit)
access : read-only

FNCERR : Frame Number CRC Error
bits : 15 - 15 (1 bit)
access : read-only


DEVICE_ENDPOINT[0]-EPCFG

DEVICE_ENDPOINT End Point Configuration
address_offset : 0x100 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[0]-EPCFG DEVICE_ENDPOINT[0]-EPCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPTYPE0 EPTYPE1 NYETDIS

EPTYPE0 : End Point Type0
bits : 0 - 2 (3 bit)

EPTYPE1 : End Point Type1
bits : 4 - 6 (3 bit)

NYETDIS : NYET Token Disable
bits : 7 - 7 (1 bit)


HOST_PIPE[0]-PCFG

HOST_PIPE End Point Configuration
address_offset : 0x100 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[0]-PCFG HOST_PIPE[0]-PCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PTOKEN BK PTYPE

PTOKEN : Pipe Token
bits : 0 - 1 (2 bit)

BK : Pipe Bank
bits : 2 - 2 (1 bit)

PTYPE : Pipe Type
bits : 3 - 5 (3 bit)


EPCFG0

DEVICE End Point Configuration
address_offset : 0x100 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPCFG0 EPCFG0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPTYPE0 EPTYPE1 NYETDIS

EPTYPE0 : End Point Type0
bits : 0 - 2 (3 bit)

EPTYPE1 : End Point Type1
bits : 4 - 6 (3 bit)

NYETDIS : NYET Token Disable
bits : 7 - 7 (1 bit)


PCFG0

HOST End Point Configuration
address_offset : 0x100 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFG0 PCFG0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PTOKEN BK PTYPE

PTOKEN : Pipe Token
bits : 0 - 1 (2 bit)

BK : Pipe Bank
bits : 2 - 2 (1 bit)

PTYPE : Pipe Type
bits : 3 - 5 (3 bit)


HOST_PIPE[0]-BINTERVAL

HOST_PIPE Bus Access Period of Pipe
address_offset : 0x103 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[0]-BINTERVAL HOST_PIPE[0]-BINTERVAL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BITINTERVAL

BITINTERVAL : Bit Interval
bits : 0 - 7 (8 bit)


BINTERVAL0

HOST Bus Access Period of Pipe
address_offset : 0x103 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BINTERVAL0 BINTERVAL0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BITINTERVAL

BITINTERVAL : Bit Interval
bits : 0 - 7 (8 bit)


DEVICE_ENDPOINT[0]-EPSTATUSCLR

DEVICE_ENDPOINT End Point Pipe Status Clear
address_offset : 0x104 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[0]-EPSTATUSCLR DEVICE_ENDPOINT[0]-EPSTATUSCLR write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Clear
bits : 0 - 0 (1 bit)

DTGLIN : Data Toggle IN Clear
bits : 1 - 1 (1 bit)

CURBK : Current Bank Clear
bits : 2 - 2 (1 bit)

STALLRQ0 : Stall 0 Request Clear
bits : 4 - 4 (1 bit)

STALLRQ1 : Stall 1 Request Clear
bits : 5 - 5 (1 bit)

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)


HOST_PIPE[0]-PSTATUSCLR

HOST_PIPE End Point Pipe Status Clear
address_offset : 0x104 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[0]-PSTATUSCLR HOST_PIPE[0]-PSTATUSCLR write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle clear
bits : 0 - 0 (1 bit)

CURBK : Curren Bank clear
bits : 2 - 2 (1 bit)

PFREEZE : Pipe Freeze Clear
bits : 4 - 4 (1 bit)

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)


EPSTATUSCLR0

DEVICE End Point Pipe Status Clear
address_offset : 0x104 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPSTATUSCLR0 EPSTATUSCLR0 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Clear
bits : 0 - 0 (1 bit)
access : write-only

DTGLIN : Data Toggle IN Clear
bits : 1 - 1 (1 bit)
access : write-only

CURBK : Current Bank Clear
bits : 2 - 2 (1 bit)
access : write-only

STALLRQ0 : Stall 0 Request Clear
bits : 4 - 4 (1 bit)
access : write-only

STALLRQ1 : Stall 1 Request Clear
bits : 5 - 5 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
access : write-only


PSTATUSCLR0

HOST End Point Pipe Status Clear
address_offset : 0x104 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PSTATUSCLR0 PSTATUSCLR0 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle clear
bits : 0 - 0 (1 bit)
access : read-only

CURBK : Curren Bank clear
bits : 2 - 2 (1 bit)
access : write-only

PFREEZE : Pipe Freeze Clear
bits : 4 - 4 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
access : write-only


DEVICE_ENDPOINT[0]-EPSTATUSSET

DEVICE_ENDPOINT End Point Pipe Status Set
address_offset : 0x105 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[0]-EPSTATUSSET DEVICE_ENDPOINT[0]-EPSTATUSSET write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Set
bits : 0 - 0 (1 bit)

DTGLIN : Data Toggle IN Set
bits : 1 - 1 (1 bit)

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)

STALLRQ0 : Stall 0 Request Set
bits : 4 - 4 (1 bit)

STALLRQ1 : Stall 1 Request Set
bits : 5 - 5 (1 bit)

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)


HOST_PIPE[0]-PSTATUSSET

HOST_PIPE End Point Pipe Status Set
address_offset : 0x105 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[0]-PSTATUSSET HOST_PIPE[0]-PSTATUSSET write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle Set
bits : 0 - 0 (1 bit)

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)

PFREEZE : Pipe Freeze Set
bits : 4 - 4 (1 bit)

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)


EPSTATUSSET0

DEVICE End Point Pipe Status Set
address_offset : 0x105 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPSTATUSSET0 EPSTATUSSET0 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Set
bits : 0 - 0 (1 bit)
access : write-only

DTGLIN : Data Toggle IN Set
bits : 1 - 1 (1 bit)
access : write-only

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
access : write-only

STALLRQ0 : Stall 0 Request Set
bits : 4 - 4 (1 bit)
access : write-only

STALLRQ1 : Stall 1 Request Set
bits : 5 - 5 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
access : write-only


PSTATUSSET0

HOST End Point Pipe Status Set
address_offset : 0x105 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PSTATUSSET0 PSTATUSSET0 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle Set
bits : 0 - 0 (1 bit)
access : write-only

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
access : write-only

PFREEZE : Pipe Freeze Set
bits : 4 - 4 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
access : write-only


DEVICE_ENDPOINT[0]-EPSTATUS

DEVICE_ENDPOINT End Point Pipe Status
address_offset : 0x106 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[0]-EPSTATUS DEVICE_ENDPOINT[0]-EPSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle Out
bits : 0 - 0 (1 bit)

DTGLIN : Data Toggle In
bits : 1 - 1 (1 bit)

CURBK : Current Bank
bits : 2 - 2 (1 bit)

STALLRQ0 : Stall 0 Request
bits : 4 - 4 (1 bit)

STALLRQ1 : Stall 1 Request
bits : 5 - 5 (1 bit)

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)


HOST_PIPE[0]-PSTATUS

HOST_PIPE End Point Pipe Status
address_offset : 0x106 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[0]-PSTATUS HOST_PIPE[0]-PSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle
bits : 0 - 0 (1 bit)

CURBK : Current Bank
bits : 2 - 2 (1 bit)

PFREEZE : Pipe Freeze
bits : 4 - 4 (1 bit)

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)


EPSTATUS0

DEVICE End Point Pipe Status
address_offset : 0x106 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EPSTATUS0 EPSTATUS0 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle Out
bits : 0 - 0 (1 bit)
access : read-only

DTGLIN : Data Toggle In
bits : 1 - 1 (1 bit)
access : read-only

CURBK : Current Bank
bits : 2 - 2 (1 bit)
access : read-only

STALLRQ0 : Stall 0 Request
bits : 4 - 4 (1 bit)
access : read-only

STALLRQ1 : Stall 1 Request
bits : 5 - 5 (1 bit)
access : read-only

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
access : read-only

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
access : read-only


PSTATUS0

HOST End Point Pipe Status
address_offset : 0x106 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PSTATUS0 PSTATUS0 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle
bits : 0 - 0 (1 bit)
access : read-only

CURBK : Current Bank
bits : 2 - 2 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 4 - 4 (1 bit)
access : read-only

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
access : read-only

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
access : read-only


DEVICE_ENDPOINT[0]-EPINTFLAG

DEVICE_ENDPOINT End Point Interrupt Flag
address_offset : 0x107 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[0]-EPINTFLAG DEVICE_ENDPOINT[0]-EPINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1
bits : 3 - 3 (1 bit)

RXSTP : Received Setup
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out
bits : 6 - 6 (1 bit)


HOST_PIPE[0]-PINTFLAG

HOST_PIPE Pipe Interrupt Flag
address_offset : 0x107 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[0]-PINTFLAG HOST_PIPE[0]-PINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Flag
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Flag
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Flag
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Flag
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Flag
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Flag
bits : 5 - 5 (1 bit)


EPINTFLAG0

DEVICE End Point Interrupt Flag
address_offset : 0x107 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPINTFLAG0 EPINTFLAG0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1
bits : 3 - 3 (1 bit)

RXSTP : Received Setup
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out
bits : 6 - 6 (1 bit)


PINTFLAG0

HOST Pipe Interrupt Flag
address_offset : 0x107 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTFLAG0 PINTFLAG0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Flag
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Flag
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Flag
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Flag
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Flag
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Flag
bits : 5 - 5 (1 bit)


DEVICE_ENDPOINT[0]-EPINTENCLR

DEVICE_ENDPOINT End Point Interrupt Clear Flag
address_offset : 0x108 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[0]-EPINTENCLR DEVICE_ENDPOINT[0]-EPINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Disable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Disable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Disable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/Out Interrupt Disable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/Out Interrupt Disable
bits : 6 - 6 (1 bit)


HOST_PIPE[0]-PINTENCLR

HOST_PIPE Pipe Interrupt Flag Clear
address_offset : 0x108 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[0]-PINTENCLR HOST_PIPE[0]-PINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Disable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Disable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL : Stall Inetrrupt Disable
bits : 5 - 5 (1 bit)


EPINTENCLR0

DEVICE End Point Interrupt Clear Flag
address_offset : 0x108 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPINTENCLR0 EPINTENCLR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Disable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Disable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Disable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/Out Interrupt Disable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/Out Interrupt Disable
bits : 6 - 6 (1 bit)


PINTENCLR0

HOST Pipe Interrupt Flag Clear
address_offset : 0x108 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTENCLR0 PINTENCLR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Disable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Disable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL : Stall Inetrrupt Disable
bits : 5 - 5 (1 bit)


DEVICE_ENDPOINT[0]-EPINTENSET

DEVICE_ENDPOINT End Point Interrupt Set Flag
address_offset : 0x109 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[0]-EPINTENSET DEVICE_ENDPOINT[0]-EPINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Enable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Enable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out Interrupt enable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out Interrupt enable
bits : 6 - 6 (1 bit)


HOST_PIPE[0]-PINTENSET

HOST_PIPE Pipe Interrupt Flag Set
address_offset : 0x109 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[0]-PINTENSET HOST_PIPE[0]-PINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Enable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Enable
bits : 5 - 5 (1 bit)


EPINTENSET0

DEVICE End Point Interrupt Set Flag
address_offset : 0x109 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPINTENSET0 EPINTENSET0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Enable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Enable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out Interrupt enable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out Interrupt enable
bits : 6 - 6 (1 bit)


PINTENSET0

HOST Pipe Interrupt Flag Set
address_offset : 0x109 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTENSET0 PINTENSET0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Enable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Enable
bits : 5 - 5 (1 bit)


HOST - FLENHIGH

USB is Host - - HOST Host Frame Length
address_offset : 0x12 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HOST - FLENHIGH HOST - FLENHIGH read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FLENHIGH

FLENHIGH : Frame Length
bits : 0 - 7 (8 bit)


FLENHIGH

HOST Host Frame Length
address_offset : 0x12 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FLENHIGH FLENHIGH read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FLENHIGH

FLENHIGH : Frame Length
bits : 0 - 7 (8 bit)
access : read-only


EPCFG1

DEVICE End Point Configuration
address_offset : 0x120 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPCFG1 EPCFG1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPTYPE0 EPTYPE1 NYETDIS

EPTYPE0 : End Point Type0
bits : 0 - 2 (3 bit)

EPTYPE1 : End Point Type1
bits : 4 - 6 (3 bit)

NYETDIS : NYET Token Disable
bits : 7 - 7 (1 bit)


PCFG1

HOST End Point Configuration
address_offset : 0x120 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFG1 PCFG1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PTOKEN BK PTYPE

PTOKEN : Pipe Token
bits : 0 - 1 (2 bit)

BK : Pipe Bank
bits : 2 - 2 (1 bit)

PTYPE : Pipe Type
bits : 3 - 5 (3 bit)


BINTERVAL1

HOST Bus Access Period of Pipe
address_offset : 0x123 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BINTERVAL1 BINTERVAL1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BITINTERVAL

BITINTERVAL : Bit Interval
bits : 0 - 7 (8 bit)


EPSTATUSCLR1

DEVICE End Point Pipe Status Clear
address_offset : 0x124 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPSTATUSCLR1 EPSTATUSCLR1 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Clear
bits : 0 - 0 (1 bit)
access : write-only

DTGLIN : Data Toggle IN Clear
bits : 1 - 1 (1 bit)
access : write-only

CURBK : Current Bank Clear
bits : 2 - 2 (1 bit)
access : write-only

STALLRQ0 : Stall 0 Request Clear
bits : 4 - 4 (1 bit)
access : write-only

STALLRQ1 : Stall 1 Request Clear
bits : 5 - 5 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
access : write-only


PSTATUSCLR1

HOST End Point Pipe Status Clear
address_offset : 0x124 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PSTATUSCLR1 PSTATUSCLR1 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle clear
bits : 0 - 0 (1 bit)
access : read-only

CURBK : Curren Bank clear
bits : 2 - 2 (1 bit)
access : write-only

PFREEZE : Pipe Freeze Clear
bits : 4 - 4 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
access : write-only


EPSTATUSSET1

DEVICE End Point Pipe Status Set
address_offset : 0x125 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPSTATUSSET1 EPSTATUSSET1 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Set
bits : 0 - 0 (1 bit)
access : write-only

DTGLIN : Data Toggle IN Set
bits : 1 - 1 (1 bit)
access : write-only

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
access : write-only

STALLRQ0 : Stall 0 Request Set
bits : 4 - 4 (1 bit)
access : write-only

STALLRQ1 : Stall 1 Request Set
bits : 5 - 5 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
access : write-only


PSTATUSSET1

HOST End Point Pipe Status Set
address_offset : 0x125 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PSTATUSSET1 PSTATUSSET1 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle Set
bits : 0 - 0 (1 bit)
access : write-only

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
access : write-only

PFREEZE : Pipe Freeze Set
bits : 4 - 4 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
access : write-only


EPSTATUS1

DEVICE End Point Pipe Status
address_offset : 0x126 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EPSTATUS1 EPSTATUS1 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle Out
bits : 0 - 0 (1 bit)
access : read-only

DTGLIN : Data Toggle In
bits : 1 - 1 (1 bit)
access : read-only

CURBK : Current Bank
bits : 2 - 2 (1 bit)
access : read-only

STALLRQ0 : Stall 0 Request
bits : 4 - 4 (1 bit)
access : read-only

STALLRQ1 : Stall 1 Request
bits : 5 - 5 (1 bit)
access : read-only

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
access : read-only

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
access : read-only


PSTATUS1

HOST End Point Pipe Status
address_offset : 0x126 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PSTATUS1 PSTATUS1 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle
bits : 0 - 0 (1 bit)
access : read-only

CURBK : Current Bank
bits : 2 - 2 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 4 - 4 (1 bit)
access : read-only

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
access : read-only

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
access : read-only


EPINTFLAG1

DEVICE End Point Interrupt Flag
address_offset : 0x127 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPINTFLAG1 EPINTFLAG1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1
bits : 3 - 3 (1 bit)

RXSTP : Received Setup
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out
bits : 6 - 6 (1 bit)


PINTFLAG1

HOST Pipe Interrupt Flag
address_offset : 0x127 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTFLAG1 PINTFLAG1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Flag
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Flag
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Flag
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Flag
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Flag
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Flag
bits : 5 - 5 (1 bit)


EPINTENCLR1

DEVICE End Point Interrupt Clear Flag
address_offset : 0x128 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPINTENCLR1 EPINTENCLR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Disable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Disable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Disable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/Out Interrupt Disable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/Out Interrupt Disable
bits : 6 - 6 (1 bit)


PINTENCLR1

HOST Pipe Interrupt Flag Clear
address_offset : 0x128 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTENCLR1 PINTENCLR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Disable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Disable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL : Stall Inetrrupt Disable
bits : 5 - 5 (1 bit)


EPINTENSET1

DEVICE End Point Interrupt Set Flag
address_offset : 0x129 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPINTENSET1 EPINTENSET1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Enable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Enable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out Interrupt enable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out Interrupt enable
bits : 6 - 6 (1 bit)


PINTENSET1

HOST Pipe Interrupt Flag Set
address_offset : 0x129 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTENSET1 PINTENSET1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Enable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Enable
bits : 5 - 5 (1 bit)


DEVICE - INTENCLR

USB is Device - - DEVICE Device Interrupt Enable Clear
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE - INTENCLR DEVICE - INTENCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSPEND MSOF SOF EORST WAKEUP EORSM UPRSM RAMACER LPMNYET LPMSUSP

SUSPEND : Suspend Interrupt Enable
bits : 0 - 0 (1 bit)

MSOF : Micro Start of Frame Interrupt Enable in High Speed Mode
bits : 1 - 1 (1 bit)

SOF : Start Of Frame Interrupt Enable
bits : 2 - 2 (1 bit)

EORST : End of Reset Interrupt Enable
bits : 3 - 3 (1 bit)

WAKEUP : Wake Up Interrupt Enable
bits : 4 - 4 (1 bit)

EORSM : End Of Resume Interrupt Enable
bits : 5 - 5 (1 bit)

UPRSM : Upstream Resume Interrupt Enable
bits : 6 - 6 (1 bit)

RAMACER : Ram Access Interrupt Enable
bits : 7 - 7 (1 bit)

LPMNYET : Link Power Management Not Yet Interrupt Enable
bits : 8 - 8 (1 bit)

LPMSUSP : Link Power Management Suspend Interrupt Enable
bits : 9 - 9 (1 bit)


HOST - INTENCLR

USB is Host - - HOST Host Interrupt Enable Clear
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST - INTENCLR HOST - INTENCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSOF RST WAKEUP DNRSM UPRSM RAMACER DCONN DDISC

HSOF : Host Start Of Frame Interrupt Disable
bits : 2 - 2 (1 bit)

RST : BUS Reset Interrupt Disable
bits : 3 - 3 (1 bit)

WAKEUP : Wake Up Interrupt Disable
bits : 4 - 4 (1 bit)

DNRSM : DownStream to Device Interrupt Disable
bits : 5 - 5 (1 bit)

UPRSM : Upstream Resume from Device Interrupt Disable
bits : 6 - 6 (1 bit)

RAMACER : Ram Access Interrupt Disable
bits : 7 - 7 (1 bit)

DCONN : Device Connection Interrupt Disable
bits : 8 - 8 (1 bit)

DDISC : Device Disconnection Interrupt Disable
bits : 9 - 9 (1 bit)


INTENCLR

DEVICE Device Interrupt Enable Clear
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSPEND MSOF SOF HSOF EORST RST WAKEUP EORSM DNRSM UPRSM RAMACER LPMNYET DCONN LPMSUSP DDISC

SUSPEND : Suspend Interrupt Enable
bits : 0 - 0 (1 bit)

MSOF : Micro Start of Frame Interrupt Enable in High Speed Mode
bits : 1 - 1 (1 bit)

SOF : Start Of Frame Interrupt Enable
bits : 2 - 2 (1 bit)

HSOF : Host Start Of Frame Interrupt Disable
bits : 2 - 2 (1 bit)

EORST : End of Reset Interrupt Enable
bits : 3 - 3 (1 bit)

RST : BUS Reset Interrupt Disable
bits : 3 - 3 (1 bit)

WAKEUP : Wake Up Interrupt Disable
bits : 4 - 4 (1 bit)

EORSM : End Of Resume Interrupt Enable
bits : 5 - 5 (1 bit)

DNRSM : DownStream to Device Interrupt Disable
bits : 5 - 5 (1 bit)

UPRSM : Upstream Resume from Device Interrupt Disable
bits : 6 - 6 (1 bit)

RAMACER : Ram Access Interrupt Disable
bits : 7 - 7 (1 bit)

LPMNYET : Link Power Management Not Yet Interrupt Enable
bits : 8 - 8 (1 bit)

DCONN : Device Connection Interrupt Disable
bits : 8 - 8 (1 bit)

LPMSUSP : Link Power Management Suspend Interrupt Enable
bits : 9 - 9 (1 bit)

DDISC : Device Disconnection Interrupt Disable
bits : 9 - 9 (1 bit)


EPCFG2

DEVICE End Point Configuration
address_offset : 0x140 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPCFG2 EPCFG2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPTYPE0 EPTYPE1 NYETDIS

EPTYPE0 : End Point Type0
bits : 0 - 2 (3 bit)

EPTYPE1 : End Point Type1
bits : 4 - 6 (3 bit)

NYETDIS : NYET Token Disable
bits : 7 - 7 (1 bit)


PCFG2

HOST End Point Configuration
address_offset : 0x140 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFG2 PCFG2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PTOKEN BK PTYPE

PTOKEN : Pipe Token
bits : 0 - 1 (2 bit)

BK : Pipe Bank
bits : 2 - 2 (1 bit)

PTYPE : Pipe Type
bits : 3 - 5 (3 bit)


BINTERVAL2

HOST Bus Access Period of Pipe
address_offset : 0x143 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BINTERVAL2 BINTERVAL2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BITINTERVAL

BITINTERVAL : Bit Interval
bits : 0 - 7 (8 bit)


EPSTATUSCLR2

DEVICE End Point Pipe Status Clear
address_offset : 0x144 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPSTATUSCLR2 EPSTATUSCLR2 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Clear
bits : 0 - 0 (1 bit)
access : write-only

DTGLIN : Data Toggle IN Clear
bits : 1 - 1 (1 bit)
access : write-only

CURBK : Current Bank Clear
bits : 2 - 2 (1 bit)
access : write-only

STALLRQ0 : Stall 0 Request Clear
bits : 4 - 4 (1 bit)
access : write-only

STALLRQ1 : Stall 1 Request Clear
bits : 5 - 5 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
access : write-only


PSTATUSCLR2

HOST End Point Pipe Status Clear
address_offset : 0x144 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PSTATUSCLR2 PSTATUSCLR2 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle clear
bits : 0 - 0 (1 bit)
access : read-only

CURBK : Curren Bank clear
bits : 2 - 2 (1 bit)
access : write-only

PFREEZE : Pipe Freeze Clear
bits : 4 - 4 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
access : write-only


EPSTATUSSET2

DEVICE End Point Pipe Status Set
address_offset : 0x145 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPSTATUSSET2 EPSTATUSSET2 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Set
bits : 0 - 0 (1 bit)
access : write-only

DTGLIN : Data Toggle IN Set
bits : 1 - 1 (1 bit)
access : write-only

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
access : write-only

STALLRQ0 : Stall 0 Request Set
bits : 4 - 4 (1 bit)
access : write-only

STALLRQ1 : Stall 1 Request Set
bits : 5 - 5 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
access : write-only


PSTATUSSET2

HOST End Point Pipe Status Set
address_offset : 0x145 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PSTATUSSET2 PSTATUSSET2 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle Set
bits : 0 - 0 (1 bit)
access : write-only

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
access : write-only

PFREEZE : Pipe Freeze Set
bits : 4 - 4 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
access : write-only


EPSTATUS2

DEVICE End Point Pipe Status
address_offset : 0x146 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EPSTATUS2 EPSTATUS2 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle Out
bits : 0 - 0 (1 bit)
access : read-only

DTGLIN : Data Toggle In
bits : 1 - 1 (1 bit)
access : read-only

CURBK : Current Bank
bits : 2 - 2 (1 bit)
access : read-only

STALLRQ0 : Stall 0 Request
bits : 4 - 4 (1 bit)
access : read-only

STALLRQ1 : Stall 1 Request
bits : 5 - 5 (1 bit)
access : read-only

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
access : read-only

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
access : read-only


PSTATUS2

HOST End Point Pipe Status
address_offset : 0x146 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PSTATUS2 PSTATUS2 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle
bits : 0 - 0 (1 bit)
access : read-only

CURBK : Current Bank
bits : 2 - 2 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 4 - 4 (1 bit)
access : read-only

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
access : read-only

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
access : read-only


EPINTFLAG2

DEVICE End Point Interrupt Flag
address_offset : 0x147 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPINTFLAG2 EPINTFLAG2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1
bits : 3 - 3 (1 bit)

RXSTP : Received Setup
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out
bits : 6 - 6 (1 bit)


PINTFLAG2

HOST Pipe Interrupt Flag
address_offset : 0x147 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTFLAG2 PINTFLAG2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Flag
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Flag
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Flag
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Flag
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Flag
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Flag
bits : 5 - 5 (1 bit)


EPINTENCLR2

DEVICE End Point Interrupt Clear Flag
address_offset : 0x148 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPINTENCLR2 EPINTENCLR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Disable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Disable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Disable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/Out Interrupt Disable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/Out Interrupt Disable
bits : 6 - 6 (1 bit)


PINTENCLR2

HOST Pipe Interrupt Flag Clear
address_offset : 0x148 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTENCLR2 PINTENCLR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Disable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Disable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL : Stall Inetrrupt Disable
bits : 5 - 5 (1 bit)


EPINTENSET2

DEVICE End Point Interrupt Set Flag
address_offset : 0x149 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPINTENSET2 EPINTENSET2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Enable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Enable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out Interrupt enable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out Interrupt enable
bits : 6 - 6 (1 bit)


PINTENSET2

HOST Pipe Interrupt Flag Set
address_offset : 0x149 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTENSET2 PINTENSET2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Enable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Enable
bits : 5 - 5 (1 bit)


EPCFG3

DEVICE End Point Configuration
address_offset : 0x160 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPCFG3 EPCFG3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPTYPE0 EPTYPE1 NYETDIS

EPTYPE0 : End Point Type0
bits : 0 - 2 (3 bit)

EPTYPE1 : End Point Type1
bits : 4 - 6 (3 bit)

NYETDIS : NYET Token Disable
bits : 7 - 7 (1 bit)


PCFG3

HOST End Point Configuration
address_offset : 0x160 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFG3 PCFG3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PTOKEN BK PTYPE

PTOKEN : Pipe Token
bits : 0 - 1 (2 bit)

BK : Pipe Bank
bits : 2 - 2 (1 bit)

PTYPE : Pipe Type
bits : 3 - 5 (3 bit)


BINTERVAL3

HOST Bus Access Period of Pipe
address_offset : 0x163 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BINTERVAL3 BINTERVAL3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BITINTERVAL

BITINTERVAL : Bit Interval
bits : 0 - 7 (8 bit)


EPSTATUSCLR3

DEVICE End Point Pipe Status Clear
address_offset : 0x164 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPSTATUSCLR3 EPSTATUSCLR3 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Clear
bits : 0 - 0 (1 bit)
access : write-only

DTGLIN : Data Toggle IN Clear
bits : 1 - 1 (1 bit)
access : write-only

CURBK : Current Bank Clear
bits : 2 - 2 (1 bit)
access : write-only

STALLRQ0 : Stall 0 Request Clear
bits : 4 - 4 (1 bit)
access : write-only

STALLRQ1 : Stall 1 Request Clear
bits : 5 - 5 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
access : write-only


PSTATUSCLR3

HOST End Point Pipe Status Clear
address_offset : 0x164 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PSTATUSCLR3 PSTATUSCLR3 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle clear
bits : 0 - 0 (1 bit)
access : read-only

CURBK : Curren Bank clear
bits : 2 - 2 (1 bit)
access : write-only

PFREEZE : Pipe Freeze Clear
bits : 4 - 4 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
access : write-only


EPSTATUSSET3

DEVICE End Point Pipe Status Set
address_offset : 0x165 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPSTATUSSET3 EPSTATUSSET3 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Set
bits : 0 - 0 (1 bit)
access : write-only

DTGLIN : Data Toggle IN Set
bits : 1 - 1 (1 bit)
access : write-only

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
access : write-only

STALLRQ0 : Stall 0 Request Set
bits : 4 - 4 (1 bit)
access : write-only

STALLRQ1 : Stall 1 Request Set
bits : 5 - 5 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
access : write-only


PSTATUSSET3

HOST End Point Pipe Status Set
address_offset : 0x165 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PSTATUSSET3 PSTATUSSET3 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle Set
bits : 0 - 0 (1 bit)
access : write-only

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
access : write-only

PFREEZE : Pipe Freeze Set
bits : 4 - 4 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
access : write-only


EPSTATUS3

DEVICE End Point Pipe Status
address_offset : 0x166 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EPSTATUS3 EPSTATUS3 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle Out
bits : 0 - 0 (1 bit)
access : read-only

DTGLIN : Data Toggle In
bits : 1 - 1 (1 bit)
access : read-only

CURBK : Current Bank
bits : 2 - 2 (1 bit)
access : read-only

STALLRQ0 : Stall 0 Request
bits : 4 - 4 (1 bit)
access : read-only

STALLRQ1 : Stall 1 Request
bits : 5 - 5 (1 bit)
access : read-only

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
access : read-only

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
access : read-only


PSTATUS3

HOST End Point Pipe Status
address_offset : 0x166 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PSTATUS3 PSTATUS3 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle
bits : 0 - 0 (1 bit)
access : read-only

CURBK : Current Bank
bits : 2 - 2 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 4 - 4 (1 bit)
access : read-only

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
access : read-only

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
access : read-only


EPINTFLAG3

DEVICE End Point Interrupt Flag
address_offset : 0x167 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPINTFLAG3 EPINTFLAG3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1
bits : 3 - 3 (1 bit)

RXSTP : Received Setup
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out
bits : 6 - 6 (1 bit)


PINTFLAG3

HOST Pipe Interrupt Flag
address_offset : 0x167 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTFLAG3 PINTFLAG3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Flag
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Flag
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Flag
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Flag
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Flag
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Flag
bits : 5 - 5 (1 bit)


EPINTENCLR3

DEVICE End Point Interrupt Clear Flag
address_offset : 0x168 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPINTENCLR3 EPINTENCLR3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Disable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Disable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Disable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/Out Interrupt Disable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/Out Interrupt Disable
bits : 6 - 6 (1 bit)


PINTENCLR3

HOST Pipe Interrupt Flag Clear
address_offset : 0x168 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTENCLR3 PINTENCLR3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Disable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Disable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL : Stall Inetrrupt Disable
bits : 5 - 5 (1 bit)


EPINTENSET3

DEVICE End Point Interrupt Set Flag
address_offset : 0x169 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPINTENSET3 EPINTENSET3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Enable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Enable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out Interrupt enable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out Interrupt enable
bits : 6 - 6 (1 bit)


PINTENSET3

HOST Pipe Interrupt Flag Set
address_offset : 0x169 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTENSET3 PINTENSET3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Enable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Enable
bits : 5 - 5 (1 bit)


DEVICE - INTENSET

USB is Device - - DEVICE Device Interrupt Enable Set
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE - INTENSET DEVICE - INTENSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSPEND MSOF SOF EORST WAKEUP EORSM UPRSM RAMACER LPMNYET LPMSUSP

SUSPEND : Suspend Interrupt Enable
bits : 0 - 0 (1 bit)

MSOF : Micro Start of Frame Interrupt Enable in High Speed Mode
bits : 1 - 1 (1 bit)

SOF : Start Of Frame Interrupt Enable
bits : 2 - 2 (1 bit)

EORST : End of Reset Interrupt Enable
bits : 3 - 3 (1 bit)

WAKEUP : Wake Up Interrupt Enable
bits : 4 - 4 (1 bit)

EORSM : End Of Resume Interrupt Enable
bits : 5 - 5 (1 bit)

UPRSM : Upstream Resume Interrupt Enable
bits : 6 - 6 (1 bit)

RAMACER : Ram Access Interrupt Enable
bits : 7 - 7 (1 bit)

LPMNYET : Link Power Management Not Yet Interrupt Enable
bits : 8 - 8 (1 bit)

LPMSUSP : Link Power Management Suspend Interrupt Enable
bits : 9 - 9 (1 bit)


HOST - INTENSET

USB is Host - - HOST Host Interrupt Enable Set
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST - INTENSET HOST - INTENSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSOF RST WAKEUP DNRSM UPRSM RAMACER DCONN DDISC

HSOF : Host Start Of Frame Interrupt Enable
bits : 2 - 2 (1 bit)

RST : Bus Reset Interrupt Enable
bits : 3 - 3 (1 bit)

WAKEUP : Wake Up Interrupt Enable
bits : 4 - 4 (1 bit)

DNRSM : DownStream to the Device Interrupt Enable
bits : 5 - 5 (1 bit)

UPRSM : Upstream Resume fromthe device Interrupt Enable
bits : 6 - 6 (1 bit)

RAMACER : Ram Access Interrupt Enable
bits : 7 - 7 (1 bit)

DCONN : Link Power Management Interrupt Enable
bits : 8 - 8 (1 bit)

DDISC : Device Disconnection Interrupt Enable
bits : 9 - 9 (1 bit)


INTENSET

DEVICE Device Interrupt Enable Set
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSPEND MSOF SOF HSOF EORST RST WAKEUP EORSM DNRSM UPRSM RAMACER LPMNYET DCONN LPMSUSP DDISC

SUSPEND : Suspend Interrupt Enable
bits : 0 - 0 (1 bit)

MSOF : Micro Start of Frame Interrupt Enable in High Speed Mode
bits : 1 - 1 (1 bit)

SOF : Start Of Frame Interrupt Enable
bits : 2 - 2 (1 bit)

HSOF : Host Start Of Frame Interrupt Enable
bits : 2 - 2 (1 bit)

EORST : End of Reset Interrupt Enable
bits : 3 - 3 (1 bit)

RST : Bus Reset Interrupt Enable
bits : 3 - 3 (1 bit)

WAKEUP : Wake Up Interrupt Enable
bits : 4 - 4 (1 bit)

EORSM : End Of Resume Interrupt Enable
bits : 5 - 5 (1 bit)

DNRSM : DownStream to the Device Interrupt Enable
bits : 5 - 5 (1 bit)

UPRSM : Upstream Resume fromthe device Interrupt Enable
bits : 6 - 6 (1 bit)

RAMACER : Ram Access Interrupt Enable
bits : 7 - 7 (1 bit)

LPMNYET : Link Power Management Not Yet Interrupt Enable
bits : 8 - 8 (1 bit)

DCONN : Link Power Management Interrupt Enable
bits : 8 - 8 (1 bit)

LPMSUSP : Link Power Management Suspend Interrupt Enable
bits : 9 - 9 (1 bit)

DDISC : Device Disconnection Interrupt Enable
bits : 9 - 9 (1 bit)


EPCFG4

DEVICE End Point Configuration
address_offset : 0x180 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPCFG4 EPCFG4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPTYPE0 EPTYPE1 NYETDIS

EPTYPE0 : End Point Type0
bits : 0 - 2 (3 bit)

EPTYPE1 : End Point Type1
bits : 4 - 6 (3 bit)

NYETDIS : NYET Token Disable
bits : 7 - 7 (1 bit)


PCFG4

HOST End Point Configuration
address_offset : 0x180 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFG4 PCFG4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PTOKEN BK PTYPE

PTOKEN : Pipe Token
bits : 0 - 1 (2 bit)

BK : Pipe Bank
bits : 2 - 2 (1 bit)

PTYPE : Pipe Type
bits : 3 - 5 (3 bit)


BINTERVAL4

HOST Bus Access Period of Pipe
address_offset : 0x183 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BINTERVAL4 BINTERVAL4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BITINTERVAL

BITINTERVAL : Bit Interval
bits : 0 - 7 (8 bit)


EPSTATUSCLR4

DEVICE End Point Pipe Status Clear
address_offset : 0x184 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPSTATUSCLR4 EPSTATUSCLR4 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Clear
bits : 0 - 0 (1 bit)
access : write-only

DTGLIN : Data Toggle IN Clear
bits : 1 - 1 (1 bit)
access : write-only

CURBK : Current Bank Clear
bits : 2 - 2 (1 bit)
access : write-only

STALLRQ0 : Stall 0 Request Clear
bits : 4 - 4 (1 bit)
access : write-only

STALLRQ1 : Stall 1 Request Clear
bits : 5 - 5 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
access : write-only


PSTATUSCLR4

HOST End Point Pipe Status Clear
address_offset : 0x184 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PSTATUSCLR4 PSTATUSCLR4 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle clear
bits : 0 - 0 (1 bit)
access : read-only

CURBK : Curren Bank clear
bits : 2 - 2 (1 bit)
access : write-only

PFREEZE : Pipe Freeze Clear
bits : 4 - 4 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
access : write-only


EPSTATUSSET4

DEVICE End Point Pipe Status Set
address_offset : 0x185 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPSTATUSSET4 EPSTATUSSET4 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Set
bits : 0 - 0 (1 bit)
access : write-only

DTGLIN : Data Toggle IN Set
bits : 1 - 1 (1 bit)
access : write-only

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
access : write-only

STALLRQ0 : Stall 0 Request Set
bits : 4 - 4 (1 bit)
access : write-only

STALLRQ1 : Stall 1 Request Set
bits : 5 - 5 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
access : write-only


PSTATUSSET4

HOST End Point Pipe Status Set
address_offset : 0x185 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PSTATUSSET4 PSTATUSSET4 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle Set
bits : 0 - 0 (1 bit)
access : write-only

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
access : write-only

PFREEZE : Pipe Freeze Set
bits : 4 - 4 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
access : write-only


EPSTATUS4

DEVICE End Point Pipe Status
address_offset : 0x186 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EPSTATUS4 EPSTATUS4 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle Out
bits : 0 - 0 (1 bit)
access : read-only

DTGLIN : Data Toggle In
bits : 1 - 1 (1 bit)
access : read-only

CURBK : Current Bank
bits : 2 - 2 (1 bit)
access : read-only

STALLRQ0 : Stall 0 Request
bits : 4 - 4 (1 bit)
access : read-only

STALLRQ1 : Stall 1 Request
bits : 5 - 5 (1 bit)
access : read-only

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
access : read-only

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
access : read-only


PSTATUS4

HOST End Point Pipe Status
address_offset : 0x186 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PSTATUS4 PSTATUS4 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle
bits : 0 - 0 (1 bit)
access : read-only

CURBK : Current Bank
bits : 2 - 2 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 4 - 4 (1 bit)
access : read-only

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
access : read-only

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
access : read-only


EPINTFLAG4

DEVICE End Point Interrupt Flag
address_offset : 0x187 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPINTFLAG4 EPINTFLAG4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1
bits : 3 - 3 (1 bit)

RXSTP : Received Setup
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out
bits : 6 - 6 (1 bit)


PINTFLAG4

HOST Pipe Interrupt Flag
address_offset : 0x187 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTFLAG4 PINTFLAG4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Flag
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Flag
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Flag
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Flag
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Flag
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Flag
bits : 5 - 5 (1 bit)


EPINTENCLR4

DEVICE End Point Interrupt Clear Flag
address_offset : 0x188 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPINTENCLR4 EPINTENCLR4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Disable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Disable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Disable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/Out Interrupt Disable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/Out Interrupt Disable
bits : 6 - 6 (1 bit)


PINTENCLR4

HOST Pipe Interrupt Flag Clear
address_offset : 0x188 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTENCLR4 PINTENCLR4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Disable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Disable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL : Stall Inetrrupt Disable
bits : 5 - 5 (1 bit)


EPINTENSET4

DEVICE End Point Interrupt Set Flag
address_offset : 0x189 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPINTENSET4 EPINTENSET4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Enable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Enable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out Interrupt enable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out Interrupt enable
bits : 6 - 6 (1 bit)


PINTENSET4

HOST Pipe Interrupt Flag Set
address_offset : 0x189 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTENSET4 PINTENSET4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Enable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Enable
bits : 5 - 5 (1 bit)


EPCFG5

DEVICE End Point Configuration
address_offset : 0x1A0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPCFG5 EPCFG5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPTYPE0 EPTYPE1 NYETDIS

EPTYPE0 : End Point Type0
bits : 0 - 2 (3 bit)

EPTYPE1 : End Point Type1
bits : 4 - 6 (3 bit)

NYETDIS : NYET Token Disable
bits : 7 - 7 (1 bit)


PCFG5

HOST End Point Configuration
address_offset : 0x1A0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFG5 PCFG5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PTOKEN BK PTYPE

PTOKEN : Pipe Token
bits : 0 - 1 (2 bit)

BK : Pipe Bank
bits : 2 - 2 (1 bit)

PTYPE : Pipe Type
bits : 3 - 5 (3 bit)


BINTERVAL5

HOST Bus Access Period of Pipe
address_offset : 0x1A3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BINTERVAL5 BINTERVAL5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BITINTERVAL

BITINTERVAL : Bit Interval
bits : 0 - 7 (8 bit)


EPSTATUSCLR5

DEVICE End Point Pipe Status Clear
address_offset : 0x1A4 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPSTATUSCLR5 EPSTATUSCLR5 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Clear
bits : 0 - 0 (1 bit)
access : write-only

DTGLIN : Data Toggle IN Clear
bits : 1 - 1 (1 bit)
access : write-only

CURBK : Current Bank Clear
bits : 2 - 2 (1 bit)
access : write-only

STALLRQ0 : Stall 0 Request Clear
bits : 4 - 4 (1 bit)
access : write-only

STALLRQ1 : Stall 1 Request Clear
bits : 5 - 5 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
access : write-only


PSTATUSCLR5

HOST End Point Pipe Status Clear
address_offset : 0x1A4 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PSTATUSCLR5 PSTATUSCLR5 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle clear
bits : 0 - 0 (1 bit)
access : read-only

CURBK : Curren Bank clear
bits : 2 - 2 (1 bit)
access : write-only

PFREEZE : Pipe Freeze Clear
bits : 4 - 4 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
access : write-only


EPSTATUSSET5

DEVICE End Point Pipe Status Set
address_offset : 0x1A5 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPSTATUSSET5 EPSTATUSSET5 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Set
bits : 0 - 0 (1 bit)
access : write-only

DTGLIN : Data Toggle IN Set
bits : 1 - 1 (1 bit)
access : write-only

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
access : write-only

STALLRQ0 : Stall 0 Request Set
bits : 4 - 4 (1 bit)
access : write-only

STALLRQ1 : Stall 1 Request Set
bits : 5 - 5 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
access : write-only


PSTATUSSET5

HOST End Point Pipe Status Set
address_offset : 0x1A5 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PSTATUSSET5 PSTATUSSET5 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle Set
bits : 0 - 0 (1 bit)
access : write-only

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
access : write-only

PFREEZE : Pipe Freeze Set
bits : 4 - 4 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
access : write-only


EPSTATUS5

DEVICE End Point Pipe Status
address_offset : 0x1A6 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EPSTATUS5 EPSTATUS5 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle Out
bits : 0 - 0 (1 bit)
access : read-only

DTGLIN : Data Toggle In
bits : 1 - 1 (1 bit)
access : read-only

CURBK : Current Bank
bits : 2 - 2 (1 bit)
access : read-only

STALLRQ0 : Stall 0 Request
bits : 4 - 4 (1 bit)
access : read-only

STALLRQ1 : Stall 1 Request
bits : 5 - 5 (1 bit)
access : read-only

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
access : read-only

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
access : read-only


PSTATUS5

HOST End Point Pipe Status
address_offset : 0x1A6 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PSTATUS5 PSTATUS5 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle
bits : 0 - 0 (1 bit)
access : read-only

CURBK : Current Bank
bits : 2 - 2 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 4 - 4 (1 bit)
access : read-only

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
access : read-only

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
access : read-only


EPINTFLAG5

DEVICE End Point Interrupt Flag
address_offset : 0x1A7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPINTFLAG5 EPINTFLAG5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1
bits : 3 - 3 (1 bit)

RXSTP : Received Setup
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out
bits : 6 - 6 (1 bit)


PINTFLAG5

HOST Pipe Interrupt Flag
address_offset : 0x1A7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTFLAG5 PINTFLAG5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Flag
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Flag
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Flag
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Flag
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Flag
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Flag
bits : 5 - 5 (1 bit)


EPINTENCLR5

DEVICE End Point Interrupt Clear Flag
address_offset : 0x1A8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPINTENCLR5 EPINTENCLR5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Disable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Disable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Disable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/Out Interrupt Disable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/Out Interrupt Disable
bits : 6 - 6 (1 bit)


PINTENCLR5

HOST Pipe Interrupt Flag Clear
address_offset : 0x1A8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTENCLR5 PINTENCLR5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Disable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Disable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL : Stall Inetrrupt Disable
bits : 5 - 5 (1 bit)


EPINTENSET5

DEVICE End Point Interrupt Set Flag
address_offset : 0x1A9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPINTENSET5 EPINTENSET5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Enable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Enable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out Interrupt enable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out Interrupt enable
bits : 6 - 6 (1 bit)


PINTENSET5

HOST Pipe Interrupt Flag Set
address_offset : 0x1A9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTENSET5 PINTENSET5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Enable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Enable
bits : 5 - 5 (1 bit)


DEVICE - INTFLAG

USB is Device - - DEVICE Device Interrupt Flag
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE - INTFLAG DEVICE - INTFLAG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSPEND MSOF SOF EORST WAKEUP EORSM UPRSM RAMACER LPMNYET LPMSUSP

SUSPEND : Suspend
bits : 0 - 0 (1 bit)

MSOF : Micro Start of Frame in High Speed Mode
bits : 1 - 1 (1 bit)

SOF : Start Of Frame
bits : 2 - 2 (1 bit)

EORST : End of Reset
bits : 3 - 3 (1 bit)

WAKEUP : Wake Up
bits : 4 - 4 (1 bit)

EORSM : End Of Resume
bits : 5 - 5 (1 bit)

UPRSM : Upstream Resume
bits : 6 - 6 (1 bit)

RAMACER : Ram Access
bits : 7 - 7 (1 bit)

LPMNYET : Link Power Management Not Yet
bits : 8 - 8 (1 bit)

LPMSUSP : Link Power Management Suspend
bits : 9 - 9 (1 bit)


HOST - INTFLAG

USB is Host - - HOST Host Interrupt Flag
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST - INTFLAG HOST - INTFLAG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSOF RST WAKEUP DNRSM UPRSM RAMACER DCONN DDISC

HSOF : Host Start Of Frame
bits : 2 - 2 (1 bit)

RST : Bus Reset
bits : 3 - 3 (1 bit)

WAKEUP : Wake Up
bits : 4 - 4 (1 bit)

DNRSM : Downstream
bits : 5 - 5 (1 bit)

UPRSM : Upstream Resume from the Device
bits : 6 - 6 (1 bit)

RAMACER : Ram Access
bits : 7 - 7 (1 bit)

DCONN : Device Connection
bits : 8 - 8 (1 bit)

DDISC : Device Disconnection
bits : 9 - 9 (1 bit)


INTFLAG

DEVICE Device Interrupt Flag
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAG INTFLAG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSPEND MSOF SOF HSOF EORST RST WAKEUP EORSM DNRSM UPRSM RAMACER LPMNYET DCONN LPMSUSP DDISC

SUSPEND : Suspend
bits : 0 - 0 (1 bit)

MSOF : Micro Start of Frame in High Speed Mode
bits : 1 - 1 (1 bit)

SOF : Start Of Frame
bits : 2 - 2 (1 bit)

HSOF : Host Start Of Frame
bits : 2 - 2 (1 bit)

EORST : End of Reset
bits : 3 - 3 (1 bit)

RST : Bus Reset
bits : 3 - 3 (1 bit)

WAKEUP : Wake Up
bits : 4 - 4 (1 bit)

EORSM : End Of Resume
bits : 5 - 5 (1 bit)

DNRSM : Downstream
bits : 5 - 5 (1 bit)

UPRSM : Upstream Resume from the Device
bits : 6 - 6 (1 bit)

RAMACER : Ram Access
bits : 7 - 7 (1 bit)

LPMNYET : Link Power Management Not Yet
bits : 8 - 8 (1 bit)

DCONN : Device Connection
bits : 8 - 8 (1 bit)

LPMSUSP : Link Power Management Suspend
bits : 9 - 9 (1 bit)

DDISC : Device Disconnection
bits : 9 - 9 (1 bit)


EPCFG6

DEVICE End Point Configuration
address_offset : 0x1C0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPCFG6 EPCFG6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPTYPE0 EPTYPE1 NYETDIS

EPTYPE0 : End Point Type0
bits : 0 - 2 (3 bit)

EPTYPE1 : End Point Type1
bits : 4 - 6 (3 bit)

NYETDIS : NYET Token Disable
bits : 7 - 7 (1 bit)


PCFG6

HOST End Point Configuration
address_offset : 0x1C0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFG6 PCFG6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PTOKEN BK PTYPE

PTOKEN : Pipe Token
bits : 0 - 1 (2 bit)

BK : Pipe Bank
bits : 2 - 2 (1 bit)

PTYPE : Pipe Type
bits : 3 - 5 (3 bit)


BINTERVAL6

HOST Bus Access Period of Pipe
address_offset : 0x1C3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BINTERVAL6 BINTERVAL6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BITINTERVAL

BITINTERVAL : Bit Interval
bits : 0 - 7 (8 bit)


EPSTATUSCLR6

DEVICE End Point Pipe Status Clear
address_offset : 0x1C4 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPSTATUSCLR6 EPSTATUSCLR6 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Clear
bits : 0 - 0 (1 bit)
access : write-only

DTGLIN : Data Toggle IN Clear
bits : 1 - 1 (1 bit)
access : write-only

CURBK : Current Bank Clear
bits : 2 - 2 (1 bit)
access : write-only

STALLRQ0 : Stall 0 Request Clear
bits : 4 - 4 (1 bit)
access : write-only

STALLRQ1 : Stall 1 Request Clear
bits : 5 - 5 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
access : write-only


PSTATUSCLR6

HOST End Point Pipe Status Clear
address_offset : 0x1C4 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PSTATUSCLR6 PSTATUSCLR6 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle clear
bits : 0 - 0 (1 bit)
access : read-only

CURBK : Curren Bank clear
bits : 2 - 2 (1 bit)
access : write-only

PFREEZE : Pipe Freeze Clear
bits : 4 - 4 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
access : write-only


EPSTATUSSET6

DEVICE End Point Pipe Status Set
address_offset : 0x1C5 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPSTATUSSET6 EPSTATUSSET6 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Set
bits : 0 - 0 (1 bit)
access : write-only

DTGLIN : Data Toggle IN Set
bits : 1 - 1 (1 bit)
access : write-only

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
access : write-only

STALLRQ0 : Stall 0 Request Set
bits : 4 - 4 (1 bit)
access : write-only

STALLRQ1 : Stall 1 Request Set
bits : 5 - 5 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
access : write-only


PSTATUSSET6

HOST End Point Pipe Status Set
address_offset : 0x1C5 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PSTATUSSET6 PSTATUSSET6 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle Set
bits : 0 - 0 (1 bit)
access : write-only

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
access : write-only

PFREEZE : Pipe Freeze Set
bits : 4 - 4 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
access : write-only


EPSTATUS6

DEVICE End Point Pipe Status
address_offset : 0x1C6 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EPSTATUS6 EPSTATUS6 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle Out
bits : 0 - 0 (1 bit)
access : read-only

DTGLIN : Data Toggle In
bits : 1 - 1 (1 bit)
access : read-only

CURBK : Current Bank
bits : 2 - 2 (1 bit)
access : read-only

STALLRQ0 : Stall 0 Request
bits : 4 - 4 (1 bit)
access : read-only

STALLRQ1 : Stall 1 Request
bits : 5 - 5 (1 bit)
access : read-only

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
access : read-only

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
access : read-only


PSTATUS6

HOST End Point Pipe Status
address_offset : 0x1C6 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PSTATUS6 PSTATUS6 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle
bits : 0 - 0 (1 bit)
access : read-only

CURBK : Current Bank
bits : 2 - 2 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 4 - 4 (1 bit)
access : read-only

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
access : read-only

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
access : read-only


EPINTFLAG6

DEVICE End Point Interrupt Flag
address_offset : 0x1C7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPINTFLAG6 EPINTFLAG6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1
bits : 3 - 3 (1 bit)

RXSTP : Received Setup
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out
bits : 6 - 6 (1 bit)


PINTFLAG6

HOST Pipe Interrupt Flag
address_offset : 0x1C7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTFLAG6 PINTFLAG6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Flag
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Flag
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Flag
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Flag
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Flag
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Flag
bits : 5 - 5 (1 bit)


EPINTENCLR6

DEVICE End Point Interrupt Clear Flag
address_offset : 0x1C8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPINTENCLR6 EPINTENCLR6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Disable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Disable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Disable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/Out Interrupt Disable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/Out Interrupt Disable
bits : 6 - 6 (1 bit)


PINTENCLR6

HOST Pipe Interrupt Flag Clear
address_offset : 0x1C8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTENCLR6 PINTENCLR6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Disable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Disable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL : Stall Inetrrupt Disable
bits : 5 - 5 (1 bit)


EPINTENSET6

DEVICE End Point Interrupt Set Flag
address_offset : 0x1C9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPINTENSET6 EPINTENSET6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Enable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Enable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out Interrupt enable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out Interrupt enable
bits : 6 - 6 (1 bit)


PINTENSET6

HOST Pipe Interrupt Flag Set
address_offset : 0x1C9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTENSET6 PINTENSET6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Enable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Enable
bits : 5 - 5 (1 bit)


EPCFG7

DEVICE End Point Configuration
address_offset : 0x1E0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPCFG7 EPCFG7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPTYPE0 EPTYPE1 NYETDIS

EPTYPE0 : End Point Type0
bits : 0 - 2 (3 bit)

EPTYPE1 : End Point Type1
bits : 4 - 6 (3 bit)

NYETDIS : NYET Token Disable
bits : 7 - 7 (1 bit)


PCFG7

HOST End Point Configuration
address_offset : 0x1E0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFG7 PCFG7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PTOKEN BK PTYPE

PTOKEN : Pipe Token
bits : 0 - 1 (2 bit)

BK : Pipe Bank
bits : 2 - 2 (1 bit)

PTYPE : Pipe Type
bits : 3 - 5 (3 bit)


BINTERVAL7

HOST Bus Access Period of Pipe
address_offset : 0x1E3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BINTERVAL7 BINTERVAL7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BITINTERVAL

BITINTERVAL : Bit Interval
bits : 0 - 7 (8 bit)


EPSTATUSCLR7

DEVICE End Point Pipe Status Clear
address_offset : 0x1E4 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPSTATUSCLR7 EPSTATUSCLR7 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Clear
bits : 0 - 0 (1 bit)
access : write-only

DTGLIN : Data Toggle IN Clear
bits : 1 - 1 (1 bit)
access : write-only

CURBK : Current Bank Clear
bits : 2 - 2 (1 bit)
access : write-only

STALLRQ0 : Stall 0 Request Clear
bits : 4 - 4 (1 bit)
access : write-only

STALLRQ1 : Stall 1 Request Clear
bits : 5 - 5 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
access : write-only


PSTATUSCLR7

HOST End Point Pipe Status Clear
address_offset : 0x1E4 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PSTATUSCLR7 PSTATUSCLR7 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle clear
bits : 0 - 0 (1 bit)
access : read-only

CURBK : Curren Bank clear
bits : 2 - 2 (1 bit)
access : write-only

PFREEZE : Pipe Freeze Clear
bits : 4 - 4 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
access : write-only


EPSTATUSSET7

DEVICE End Point Pipe Status Set
address_offset : 0x1E5 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPSTATUSSET7 EPSTATUSSET7 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Set
bits : 0 - 0 (1 bit)
access : write-only

DTGLIN : Data Toggle IN Set
bits : 1 - 1 (1 bit)
access : write-only

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
access : write-only

STALLRQ0 : Stall 0 Request Set
bits : 4 - 4 (1 bit)
access : write-only

STALLRQ1 : Stall 1 Request Set
bits : 5 - 5 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
access : write-only


PSTATUSSET7

HOST End Point Pipe Status Set
address_offset : 0x1E5 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PSTATUSSET7 PSTATUSSET7 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle Set
bits : 0 - 0 (1 bit)
access : write-only

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
access : write-only

PFREEZE : Pipe Freeze Set
bits : 4 - 4 (1 bit)
access : write-only

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
access : write-only

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
access : write-only


EPSTATUS7

DEVICE End Point Pipe Status
address_offset : 0x1E6 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EPSTATUS7 EPSTATUS7 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle Out
bits : 0 - 0 (1 bit)
access : read-only

DTGLIN : Data Toggle In
bits : 1 - 1 (1 bit)
access : read-only

CURBK : Current Bank
bits : 2 - 2 (1 bit)
access : read-only

STALLRQ0 : Stall 0 Request
bits : 4 - 4 (1 bit)
access : read-only

STALLRQ1 : Stall 1 Request
bits : 5 - 5 (1 bit)
access : read-only

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
access : read-only

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
access : read-only


PSTATUS7

HOST End Point Pipe Status
address_offset : 0x1E6 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PSTATUS7 PSTATUS7 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle
bits : 0 - 0 (1 bit)
access : read-only

CURBK : Current Bank
bits : 2 - 2 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 4 - 4 (1 bit)
access : read-only

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
access : read-only

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
access : read-only


EPINTFLAG7

DEVICE End Point Interrupt Flag
address_offset : 0x1E7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPINTFLAG7 EPINTFLAG7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1
bits : 3 - 3 (1 bit)

RXSTP : Received Setup
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out
bits : 6 - 6 (1 bit)


PINTFLAG7

HOST Pipe Interrupt Flag
address_offset : 0x1E7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTFLAG7 PINTFLAG7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Flag
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Flag
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Flag
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Flag
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Flag
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Flag
bits : 5 - 5 (1 bit)


EPINTENCLR7

DEVICE End Point Interrupt Clear Flag
address_offset : 0x1E8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPINTENCLR7 EPINTENCLR7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Disable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Disable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Disable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/Out Interrupt Disable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/Out Interrupt Disable
bits : 6 - 6 (1 bit)


PINTENCLR7

HOST Pipe Interrupt Flag Clear
address_offset : 0x1E8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTENCLR7 PINTENCLR7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Disable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Disable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL : Stall Inetrrupt Disable
bits : 5 - 5 (1 bit)


EPINTENSET7

DEVICE End Point Interrupt Set Flag
address_offset : 0x1E9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPINTENSET7 EPINTENSET7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Enable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Enable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out Interrupt enable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out Interrupt enable
bits : 6 - 6 (1 bit)


PINTENSET7

HOST Pipe Interrupt Flag Set
address_offset : 0x1E9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTENSET7 PINTENSET7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Enable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Enable
bits : 5 - 5 (1 bit)


DEVICE - SYNCBUSY

USB is Device - - Synchronization Busy
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE - SYNCBUSY DEVICE - SYNCBUSY read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SWRST ENABLE

SWRST : Software Reset Synchronization Busy
bits : 0 - 0 (1 bit)

ENABLE : Enable Synchronization Busy
bits : 1 - 1 (1 bit)


HOST - SYNCBUSY

USB is Host - - Synchronization Busy
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HOST - SYNCBUSY HOST - SYNCBUSY read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SWRST ENABLE

SWRST : Software Reset Synchronization Busy
bits : 0 - 0 (1 bit)

ENABLE : Enable Synchronization Busy
bits : 1 - 1 (1 bit)


SYNCBUSY

Synchronization Busy
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYNCBUSY SYNCBUSY read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SWRST ENABLE

SWRST : Software Reset Synchronization Busy
bits : 0 - 0 (1 bit)
access : read-only

ENABLE : Enable Synchronization Busy
bits : 1 - 1 (1 bit)
access : read-only


DEVICE - EPINTSMRY

USB is Device - - DEVICE End Point Interrupt Summary
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE - EPINTSMRY DEVICE - EPINTSMRY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPINT0 EPINT1 EPINT2 EPINT3 EPINT4 EPINT5 EPINT6 EPINT7

EPINT0 : End Point 0 Interrupt
bits : 0 - 0 (1 bit)

EPINT1 : End Point 1 Interrupt
bits : 1 - 1 (1 bit)

EPINT2 : End Point 2 Interrupt
bits : 2 - 2 (1 bit)

EPINT3 : End Point 3 Interrupt
bits : 3 - 3 (1 bit)

EPINT4 : End Point 4 Interrupt
bits : 4 - 4 (1 bit)

EPINT5 : End Point 5 Interrupt
bits : 5 - 5 (1 bit)

EPINT6 : End Point 6 Interrupt
bits : 6 - 6 (1 bit)

EPINT7 : End Point 7 Interrupt
bits : 7 - 7 (1 bit)


HOST - PINTSMRY

USB is Host - - HOST Pipe Interrupt Summary
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HOST - PINTSMRY HOST - PINTSMRY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPINT0 EPINT1 EPINT2 EPINT3 EPINT4 EPINT5 EPINT6 EPINT7

EPINT0 : Pipe 0 Interrupt
bits : 0 - 0 (1 bit)

EPINT1 : Pipe 1 Interrupt
bits : 1 - 1 (1 bit)

EPINT2 : Pipe 2 Interrupt
bits : 2 - 2 (1 bit)

EPINT3 : Pipe 3 Interrupt
bits : 3 - 3 (1 bit)

EPINT4 : Pipe 4 Interrupt
bits : 4 - 4 (1 bit)

EPINT5 : Pipe 5 Interrupt
bits : 5 - 5 (1 bit)

EPINT6 : Pipe 6 Interrupt
bits : 6 - 6 (1 bit)

EPINT7 : Pipe 7 Interrupt
bits : 7 - 7 (1 bit)


EPINTSMRY

DEVICE End Point Interrupt Summary
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EPINTSMRY EPINTSMRY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPINT0 EPINT1 EPINT2 EPINT3 EPINT4 EPINT5 EPINT6 EPINT7

EPINT0 : End Point 0 Interrupt
bits : 0 - 0 (1 bit)
access : read-only

EPINT1 : End Point 1 Interrupt
bits : 1 - 1 (1 bit)
access : read-only

EPINT2 : End Point 2 Interrupt
bits : 2 - 2 (1 bit)
access : read-only

EPINT3 : End Point 3 Interrupt
bits : 3 - 3 (1 bit)
access : read-only

EPINT4 : End Point 4 Interrupt
bits : 4 - 4 (1 bit)
access : read-only

EPINT5 : End Point 5 Interrupt
bits : 5 - 5 (1 bit)
access : read-only

EPINT6 : End Point 6 Interrupt
bits : 6 - 6 (1 bit)
access : read-only

EPINT7 : End Point 7 Interrupt
bits : 7 - 7 (1 bit)
access : read-only


PINTSMRY

HOST Pipe Interrupt Summary
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PINTSMRY PINTSMRY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPINT0 EPINT1 EPINT2 EPINT3 EPINT4 EPINT5 EPINT6 EPINT7

EPINT0 : Pipe 0 Interrupt
bits : 0 - 0 (1 bit)
access : read-only

EPINT1 : Pipe 1 Interrupt
bits : 1 - 1 (1 bit)
access : read-only

EPINT2 : Pipe 2 Interrupt
bits : 2 - 2 (1 bit)
access : read-only

EPINT3 : Pipe 3 Interrupt
bits : 3 - 3 (1 bit)
access : read-only

EPINT4 : Pipe 4 Interrupt
bits : 4 - 4 (1 bit)
access : read-only

EPINT5 : Pipe 5 Interrupt
bits : 5 - 5 (1 bit)
access : read-only

EPINT6 : Pipe 6 Interrupt
bits : 6 - 6 (1 bit)
access : read-only

EPINT7 : Pipe 7 Interrupt
bits : 7 - 7 (1 bit)
access : read-only


DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG

DEVICE_ENDPOINT End Point Configuration
address_offset : 0x220 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPTYPE0 EPTYPE1 NYETDIS

EPTYPE0 : End Point Type0
bits : 0 - 2 (3 bit)

EPTYPE1 : End Point Type1
bits : 4 - 6 (3 bit)

NYETDIS : NYET Token Disable
bits : 7 - 7 (1 bit)


HOST_PIPE[1]-HOST_PIPE[0]-PCFG

HOST_PIPE End Point Configuration
address_offset : 0x220 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[1]-HOST_PIPE[0]-PCFG HOST_PIPE[1]-HOST_PIPE[0]-PCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PTOKEN BK PTYPE

PTOKEN : Pipe Token
bits : 0 - 1 (2 bit)

BK : Pipe Bank
bits : 2 - 2 (1 bit)

PTYPE : Pipe Type
bits : 3 - 5 (3 bit)


HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL

HOST_PIPE Bus Access Period of Pipe
address_offset : 0x223 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BITINTERVAL

BITINTERVAL : Bit Interval
bits : 0 - 7 (8 bit)


DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR

DEVICE_ENDPOINT End Point Pipe Status Clear
address_offset : 0x224 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Clear
bits : 0 - 0 (1 bit)

DTGLIN : Data Toggle IN Clear
bits : 1 - 1 (1 bit)

CURBK : Current Bank Clear
bits : 2 - 2 (1 bit)

STALLRQ0 : Stall 0 Request Clear
bits : 4 - 4 (1 bit)

STALLRQ1 : Stall 1 Request Clear
bits : 5 - 5 (1 bit)

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)


HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR

HOST_PIPE End Point Pipe Status Clear
address_offset : 0x224 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle clear
bits : 0 - 0 (1 bit)

CURBK : Curren Bank clear
bits : 2 - 2 (1 bit)

PFREEZE : Pipe Freeze Clear
bits : 4 - 4 (1 bit)

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)


DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET

DEVICE_ENDPOINT End Point Pipe Status Set
address_offset : 0x225 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Set
bits : 0 - 0 (1 bit)

DTGLIN : Data Toggle IN Set
bits : 1 - 1 (1 bit)

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)

STALLRQ0 : Stall 0 Request Set
bits : 4 - 4 (1 bit)

STALLRQ1 : Stall 1 Request Set
bits : 5 - 5 (1 bit)

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)


HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET

HOST_PIPE End Point Pipe Status Set
address_offset : 0x225 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle Set
bits : 0 - 0 (1 bit)

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)

PFREEZE : Pipe Freeze Set
bits : 4 - 4 (1 bit)

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)


DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS

DEVICE_ENDPOINT End Point Pipe Status
address_offset : 0x226 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle Out
bits : 0 - 0 (1 bit)

DTGLIN : Data Toggle In
bits : 1 - 1 (1 bit)

CURBK : Current Bank
bits : 2 - 2 (1 bit)

STALLRQ0 : Stall 0 Request
bits : 4 - 4 (1 bit)

STALLRQ1 : Stall 1 Request
bits : 5 - 5 (1 bit)

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)


HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS

HOST_PIPE End Point Pipe Status
address_offset : 0x226 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle
bits : 0 - 0 (1 bit)

CURBK : Current Bank
bits : 2 - 2 (1 bit)

PFREEZE : Pipe Freeze
bits : 4 - 4 (1 bit)

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)


DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG

DEVICE_ENDPOINT End Point Interrupt Flag
address_offset : 0x227 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1
bits : 3 - 3 (1 bit)

RXSTP : Received Setup
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out
bits : 6 - 6 (1 bit)


HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG

HOST_PIPE Pipe Interrupt Flag
address_offset : 0x227 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Flag
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Flag
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Flag
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Flag
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Flag
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Flag
bits : 5 - 5 (1 bit)


DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR

DEVICE_ENDPOINT End Point Interrupt Clear Flag
address_offset : 0x228 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Disable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Disable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Disable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/Out Interrupt Disable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/Out Interrupt Disable
bits : 6 - 6 (1 bit)


HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR

HOST_PIPE Pipe Interrupt Flag Clear
address_offset : 0x228 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Disable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Disable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL : Stall Inetrrupt Disable
bits : 5 - 5 (1 bit)


DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET

DEVICE_ENDPOINT End Point Interrupt Set Flag
address_offset : 0x229 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Enable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Enable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out Interrupt enable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out Interrupt enable
bits : 6 - 6 (1 bit)


HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET

HOST_PIPE Pipe Interrupt Flag Set
address_offset : 0x229 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Enable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Enable
bits : 5 - 5 (1 bit)


DEVICE - DESCADD

USB is Device - - Descriptor Address
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE - DESCADD DEVICE - DESCADD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DESCADD

DESCADD : Descriptor Address Value
bits : 0 - 31 (32 bit)


HOST - DESCADD

USB is Host - - Descriptor Address
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST - DESCADD HOST - DESCADD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DESCADD

DESCADD : Descriptor Address Value
bits : 0 - 31 (32 bit)


DESCADD

Descriptor Address
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DESCADD DESCADD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DESCADD

DESCADD : Descriptor Address Value
bits : 0 - 31 (32 bit)


DEVICE - PADCAL

USB is Device - - USB PAD Calibration
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE - PADCAL DEVICE - PADCAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRANSP TRANSN TRIM

TRANSP : USB Pad Transp calibration
bits : 0 - 4 (5 bit)

TRANSN : USB Pad Transn calibration
bits : 6 - 10 (5 bit)

TRIM : USB Pad Trim calibration
bits : 12 - 14 (3 bit)


HOST - PADCAL

USB is Host - - USB PAD Calibration
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST - PADCAL HOST - PADCAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRANSP TRANSN TRIM

TRANSP : USB Pad Transp calibration
bits : 0 - 4 (5 bit)

TRANSN : USB Pad Transn calibration
bits : 6 - 10 (5 bit)

TRIM : USB Pad Trim calibration
bits : 12 - 14 (3 bit)


PADCAL

USB PAD Calibration
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PADCAL PADCAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRANSP TRANSN TRIM

TRANSP : USB Pad Transp calibration
bits : 0 - 4 (5 bit)

TRANSN : USB Pad Transn calibration
bits : 6 - 10 (5 bit)

TRIM : USB Pad Trim calibration
bits : 12 - 14 (3 bit)


DEVICE - QOSCTRL

USB is Device - - USB Quality Of Service
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE - QOSCTRL DEVICE - QOSCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CQOS DQOS

CQOS : Configuration Quality of Service
bits : 0 - 1 (2 bit)

DQOS : Data Quality of Service
bits : 2 - 3 (2 bit)


HOST - QOSCTRL

USB is Host - - USB Quality Of Service
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST - QOSCTRL HOST - QOSCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CQOS DQOS

CQOS : Configuration Quality of Service
bits : 0 - 1 (2 bit)

DQOS : Data Quality of Service
bits : 2 - 3 (2 bit)


QOSCTRL

USB Quality Of Service
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QOSCTRL QOSCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CQOS DQOS

CQOS : Configuration Quality of Service
bits : 0 - 1 (2 bit)

DQOS : Data Quality of Service
bits : 2 - 3 (2 bit)


BINTERVAL

HOST_PIPE Bus Access Period of Pipe
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BINTERVAL BINTERVAL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BITINTERVAL

BITINTERVAL : Bit Interval
bits : 0 - 7 (8 bit)


DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG

DEVICE_ENDPOINT End Point Configuration
address_offset : 0x360 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPTYPE0 EPTYPE1 NYETDIS

EPTYPE0 : End Point Type0
bits : 0 - 2 (3 bit)

EPTYPE1 : End Point Type1
bits : 4 - 6 (3 bit)

NYETDIS : NYET Token Disable
bits : 7 - 7 (1 bit)


HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG

HOST_PIPE End Point Configuration
address_offset : 0x360 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PTOKEN BK PTYPE

PTOKEN : Pipe Token
bits : 0 - 1 (2 bit)

BK : Pipe Bank
bits : 2 - 2 (1 bit)

PTYPE : Pipe Type
bits : 3 - 5 (3 bit)


HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL

HOST_PIPE Bus Access Period of Pipe
address_offset : 0x363 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BITINTERVAL

BITINTERVAL : Bit Interval
bits : 0 - 7 (8 bit)


DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR

DEVICE_ENDPOINT End Point Pipe Status Clear
address_offset : 0x364 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Clear
bits : 0 - 0 (1 bit)

DTGLIN : Data Toggle IN Clear
bits : 1 - 1 (1 bit)

CURBK : Current Bank Clear
bits : 2 - 2 (1 bit)

STALLRQ0 : Stall 0 Request Clear
bits : 4 - 4 (1 bit)

STALLRQ1 : Stall 1 Request Clear
bits : 5 - 5 (1 bit)

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)


HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR

HOST_PIPE End Point Pipe Status Clear
address_offset : 0x364 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle clear
bits : 0 - 0 (1 bit)

CURBK : Curren Bank clear
bits : 2 - 2 (1 bit)

PFREEZE : Pipe Freeze Clear
bits : 4 - 4 (1 bit)

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)


DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET

DEVICE_ENDPOINT End Point Pipe Status Set
address_offset : 0x365 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Set
bits : 0 - 0 (1 bit)

DTGLIN : Data Toggle IN Set
bits : 1 - 1 (1 bit)

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)

STALLRQ0 : Stall 0 Request Set
bits : 4 - 4 (1 bit)

STALLRQ1 : Stall 1 Request Set
bits : 5 - 5 (1 bit)

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)


HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET

HOST_PIPE End Point Pipe Status Set
address_offset : 0x365 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle Set
bits : 0 - 0 (1 bit)

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)

PFREEZE : Pipe Freeze Set
bits : 4 - 4 (1 bit)

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)


DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS

DEVICE_ENDPOINT End Point Pipe Status
address_offset : 0x366 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle Out
bits : 0 - 0 (1 bit)

DTGLIN : Data Toggle In
bits : 1 - 1 (1 bit)

CURBK : Current Bank
bits : 2 - 2 (1 bit)

STALLRQ0 : Stall 0 Request
bits : 4 - 4 (1 bit)

STALLRQ1 : Stall 1 Request
bits : 5 - 5 (1 bit)

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)


HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS

HOST_PIPE End Point Pipe Status
address_offset : 0x366 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle
bits : 0 - 0 (1 bit)

CURBK : Current Bank
bits : 2 - 2 (1 bit)

PFREEZE : Pipe Freeze
bits : 4 - 4 (1 bit)

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)


DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG

DEVICE_ENDPOINT End Point Interrupt Flag
address_offset : 0x367 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1
bits : 3 - 3 (1 bit)

RXSTP : Received Setup
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out
bits : 6 - 6 (1 bit)


HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG

HOST_PIPE Pipe Interrupt Flag
address_offset : 0x367 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Flag
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Flag
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Flag
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Flag
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Flag
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Flag
bits : 5 - 5 (1 bit)


DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR

DEVICE_ENDPOINT End Point Interrupt Clear Flag
address_offset : 0x368 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Disable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Disable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Disable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/Out Interrupt Disable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/Out Interrupt Disable
bits : 6 - 6 (1 bit)


HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR

HOST_PIPE Pipe Interrupt Flag Clear
address_offset : 0x368 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Disable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Disable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL : Stall Inetrrupt Disable
bits : 5 - 5 (1 bit)


DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET

DEVICE_ENDPOINT End Point Interrupt Set Flag
address_offset : 0x369 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Enable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Enable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out Interrupt enable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out Interrupt enable
bits : 6 - 6 (1 bit)


HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET

HOST_PIPE Pipe Interrupt Flag Set
address_offset : 0x369 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Enable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Enable
bits : 5 - 5 (1 bit)


EPSTATUSCLR

DEVICE_ENDPOINT End Point Pipe Status Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPSTATUSCLR EPSTATUSCLR write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Clear
bits : 0 - 0 (1 bit)

DTGLIN : Data Toggle IN Clear
bits : 1 - 1 (1 bit)

CURBK : Current Bank Clear
bits : 2 - 2 (1 bit)

STALLRQ0 : Stall 0 Request Clear
bits : 4 - 4 (1 bit)

STALLRQ1 : Stall 1 Request Clear
bits : 5 - 5 (1 bit)

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)


PSTATUSCLR

HOST_PIPE End Point Pipe Status Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PSTATUSCLR PSTATUSCLR write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle clear
bits : 0 - 0 (1 bit)

CURBK : Curren Bank clear
bits : 2 - 2 (1 bit)

PFREEZE : Pipe Freeze Clear
bits : 4 - 4 (1 bit)

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)


DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG

DEVICE_ENDPOINT End Point Configuration
address_offset : 0x4C0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPTYPE0 EPTYPE1 NYETDIS

EPTYPE0 : End Point Type0
bits : 0 - 2 (3 bit)

EPTYPE1 : End Point Type1
bits : 4 - 6 (3 bit)

NYETDIS : NYET Token Disable
bits : 7 - 7 (1 bit)


HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG

HOST_PIPE End Point Configuration
address_offset : 0x4C0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PTOKEN BK PTYPE

PTOKEN : Pipe Token
bits : 0 - 1 (2 bit)

BK : Pipe Bank
bits : 2 - 2 (1 bit)

PTYPE : Pipe Type
bits : 3 - 5 (3 bit)


HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL

HOST_PIPE Bus Access Period of Pipe
address_offset : 0x4C3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BITINTERVAL

BITINTERVAL : Bit Interval
bits : 0 - 7 (8 bit)


DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR

DEVICE_ENDPOINT End Point Pipe Status Clear
address_offset : 0x4C4 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Clear
bits : 0 - 0 (1 bit)

DTGLIN : Data Toggle IN Clear
bits : 1 - 1 (1 bit)

CURBK : Current Bank Clear
bits : 2 - 2 (1 bit)

STALLRQ0 : Stall 0 Request Clear
bits : 4 - 4 (1 bit)

STALLRQ1 : Stall 1 Request Clear
bits : 5 - 5 (1 bit)

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)


HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR

HOST_PIPE End Point Pipe Status Clear
address_offset : 0x4C4 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle clear
bits : 0 - 0 (1 bit)

CURBK : Curren Bank clear
bits : 2 - 2 (1 bit)

PFREEZE : Pipe Freeze Clear
bits : 4 - 4 (1 bit)

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)


DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET

DEVICE_ENDPOINT End Point Pipe Status Set
address_offset : 0x4C5 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Set
bits : 0 - 0 (1 bit)

DTGLIN : Data Toggle IN Set
bits : 1 - 1 (1 bit)

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)

STALLRQ0 : Stall 0 Request Set
bits : 4 - 4 (1 bit)

STALLRQ1 : Stall 1 Request Set
bits : 5 - 5 (1 bit)

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)


HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET

HOST_PIPE End Point Pipe Status Set
address_offset : 0x4C5 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle Set
bits : 0 - 0 (1 bit)

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)

PFREEZE : Pipe Freeze Set
bits : 4 - 4 (1 bit)

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)


DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS

DEVICE_ENDPOINT End Point Pipe Status
address_offset : 0x4C6 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle Out
bits : 0 - 0 (1 bit)

DTGLIN : Data Toggle In
bits : 1 - 1 (1 bit)

CURBK : Current Bank
bits : 2 - 2 (1 bit)

STALLRQ0 : Stall 0 Request
bits : 4 - 4 (1 bit)

STALLRQ1 : Stall 1 Request
bits : 5 - 5 (1 bit)

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)


HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS

HOST_PIPE End Point Pipe Status
address_offset : 0x4C6 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle
bits : 0 - 0 (1 bit)

CURBK : Current Bank
bits : 2 - 2 (1 bit)

PFREEZE : Pipe Freeze
bits : 4 - 4 (1 bit)

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)


DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG

DEVICE_ENDPOINT End Point Interrupt Flag
address_offset : 0x4C7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1
bits : 3 - 3 (1 bit)

RXSTP : Received Setup
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out
bits : 6 - 6 (1 bit)


HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG

HOST_PIPE Pipe Interrupt Flag
address_offset : 0x4C7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Flag
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Flag
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Flag
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Flag
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Flag
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Flag
bits : 5 - 5 (1 bit)


DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR

DEVICE_ENDPOINT End Point Interrupt Clear Flag
address_offset : 0x4C8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Disable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Disable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Disable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/Out Interrupt Disable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/Out Interrupt Disable
bits : 6 - 6 (1 bit)


HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR

HOST_PIPE Pipe Interrupt Flag Clear
address_offset : 0x4C8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Disable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Disable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL : Stall Inetrrupt Disable
bits : 5 - 5 (1 bit)


DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET

DEVICE_ENDPOINT End Point Interrupt Set Flag
address_offset : 0x4C9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Enable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Enable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out Interrupt enable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out Interrupt enable
bits : 6 - 6 (1 bit)


HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET

HOST_PIPE Pipe Interrupt Flag Set
address_offset : 0x4C9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Enable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Enable
bits : 5 - 5 (1 bit)


EPSTATUSSET

DEVICE_ENDPOINT End Point Pipe Status Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EPSTATUSSET EPSTATUSSET write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Set
bits : 0 - 0 (1 bit)

DTGLIN : Data Toggle IN Set
bits : 1 - 1 (1 bit)

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)

STALLRQ0 : Stall 0 Request Set
bits : 4 - 4 (1 bit)

STALLRQ1 : Stall 1 Request Set
bits : 5 - 5 (1 bit)

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)


PSTATUSSET

HOST_PIPE End Point Pipe Status Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PSTATUSSET PSTATUSSET write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle Set
bits : 0 - 0 (1 bit)

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)

PFREEZE : Pipe Freeze Set
bits : 4 - 4 (1 bit)

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)


EPSTATUS

DEVICE_ENDPOINT End Point Pipe Status
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EPSTATUS EPSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle Out
bits : 0 - 0 (1 bit)

DTGLIN : Data Toggle In
bits : 1 - 1 (1 bit)

CURBK : Current Bank
bits : 2 - 2 (1 bit)

STALLRQ0 : Stall 0 Request
bits : 4 - 4 (1 bit)

STALLRQ1 : Stall 1 Request
bits : 5 - 5 (1 bit)

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)


PSTATUS

HOST_PIPE End Point Pipe Status
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PSTATUS PSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle
bits : 0 - 0 (1 bit)

CURBK : Current Bank
bits : 2 - 2 (1 bit)

PFREEZE : Pipe Freeze
bits : 4 - 4 (1 bit)

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)


DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG

DEVICE_ENDPOINT End Point Configuration
address_offset : 0x640 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPTYPE0 EPTYPE1 NYETDIS

EPTYPE0 : End Point Type0
bits : 0 - 2 (3 bit)

EPTYPE1 : End Point Type1
bits : 4 - 6 (3 bit)

NYETDIS : NYET Token Disable
bits : 7 - 7 (1 bit)


HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG

HOST_PIPE End Point Configuration
address_offset : 0x640 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PTOKEN BK PTYPE

PTOKEN : Pipe Token
bits : 0 - 1 (2 bit)

BK : Pipe Bank
bits : 2 - 2 (1 bit)

PTYPE : Pipe Type
bits : 3 - 5 (3 bit)


HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL

HOST_PIPE Bus Access Period of Pipe
address_offset : 0x643 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BITINTERVAL

BITINTERVAL : Bit Interval
bits : 0 - 7 (8 bit)


DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR

DEVICE_ENDPOINT End Point Pipe Status Clear
address_offset : 0x644 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Clear
bits : 0 - 0 (1 bit)

DTGLIN : Data Toggle IN Clear
bits : 1 - 1 (1 bit)

CURBK : Current Bank Clear
bits : 2 - 2 (1 bit)

STALLRQ0 : Stall 0 Request Clear
bits : 4 - 4 (1 bit)

STALLRQ1 : Stall 1 Request Clear
bits : 5 - 5 (1 bit)

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)


HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR

HOST_PIPE End Point Pipe Status Clear
address_offset : 0x644 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle clear
bits : 0 - 0 (1 bit)

CURBK : Curren Bank clear
bits : 2 - 2 (1 bit)

PFREEZE : Pipe Freeze Clear
bits : 4 - 4 (1 bit)

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)


DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET

DEVICE_ENDPOINT End Point Pipe Status Set
address_offset : 0x645 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Set
bits : 0 - 0 (1 bit)

DTGLIN : Data Toggle IN Set
bits : 1 - 1 (1 bit)

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)

STALLRQ0 : Stall 0 Request Set
bits : 4 - 4 (1 bit)

STALLRQ1 : Stall 1 Request Set
bits : 5 - 5 (1 bit)

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)


HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET

HOST_PIPE End Point Pipe Status Set
address_offset : 0x645 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle Set
bits : 0 - 0 (1 bit)

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)

PFREEZE : Pipe Freeze Set
bits : 4 - 4 (1 bit)

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)


DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS

DEVICE_ENDPOINT End Point Pipe Status
address_offset : 0x646 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle Out
bits : 0 - 0 (1 bit)

DTGLIN : Data Toggle In
bits : 1 - 1 (1 bit)

CURBK : Current Bank
bits : 2 - 2 (1 bit)

STALLRQ0 : Stall 0 Request
bits : 4 - 4 (1 bit)

STALLRQ1 : Stall 1 Request
bits : 5 - 5 (1 bit)

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)


HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS

HOST_PIPE End Point Pipe Status
address_offset : 0x646 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle
bits : 0 - 0 (1 bit)

CURBK : Current Bank
bits : 2 - 2 (1 bit)

PFREEZE : Pipe Freeze
bits : 4 - 4 (1 bit)

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)


DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG

DEVICE_ENDPOINT End Point Interrupt Flag
address_offset : 0x647 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1
bits : 3 - 3 (1 bit)

RXSTP : Received Setup
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out
bits : 6 - 6 (1 bit)


HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG

HOST_PIPE Pipe Interrupt Flag
address_offset : 0x647 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Flag
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Flag
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Flag
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Flag
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Flag
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Flag
bits : 5 - 5 (1 bit)


DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR

DEVICE_ENDPOINT End Point Interrupt Clear Flag
address_offset : 0x648 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Disable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Disable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Disable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/Out Interrupt Disable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/Out Interrupt Disable
bits : 6 - 6 (1 bit)


HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR

HOST_PIPE Pipe Interrupt Flag Clear
address_offset : 0x648 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Disable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Disable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL : Stall Inetrrupt Disable
bits : 5 - 5 (1 bit)


DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET

DEVICE_ENDPOINT End Point Interrupt Set Flag
address_offset : 0x649 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Enable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Enable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out Interrupt enable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out Interrupt enable
bits : 6 - 6 (1 bit)


HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET

HOST_PIPE Pipe Interrupt Flag Set
address_offset : 0x649 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Enable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Enable
bits : 5 - 5 (1 bit)


EPINTFLAG

DEVICE_ENDPOINT End Point Interrupt Flag
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPINTFLAG EPINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1
bits : 3 - 3 (1 bit)

RXSTP : Received Setup
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out
bits : 6 - 6 (1 bit)


PINTFLAG

HOST_PIPE Pipe Interrupt Flag
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTFLAG PINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Flag
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Flag
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Flag
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Flag
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Flag
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Flag
bits : 5 - 5 (1 bit)


DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG

DEVICE_ENDPOINT End Point Configuration
address_offset : 0x7E0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPTYPE0 EPTYPE1 NYETDIS

EPTYPE0 : End Point Type0
bits : 0 - 2 (3 bit)

EPTYPE1 : End Point Type1
bits : 4 - 6 (3 bit)

NYETDIS : NYET Token Disable
bits : 7 - 7 (1 bit)


HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG

HOST_PIPE End Point Configuration
address_offset : 0x7E0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PTOKEN BK PTYPE

PTOKEN : Pipe Token
bits : 0 - 1 (2 bit)

BK : Pipe Bank
bits : 2 - 2 (1 bit)

PTYPE : Pipe Type
bits : 3 - 5 (3 bit)


HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL

HOST_PIPE Bus Access Period of Pipe
address_offset : 0x7E3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BITINTERVAL

BITINTERVAL : Bit Interval
bits : 0 - 7 (8 bit)


DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR

DEVICE_ENDPOINT End Point Pipe Status Clear
address_offset : 0x7E4 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Clear
bits : 0 - 0 (1 bit)

DTGLIN : Data Toggle IN Clear
bits : 1 - 1 (1 bit)

CURBK : Current Bank Clear
bits : 2 - 2 (1 bit)

STALLRQ0 : Stall 0 Request Clear
bits : 4 - 4 (1 bit)

STALLRQ1 : Stall 1 Request Clear
bits : 5 - 5 (1 bit)

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)


HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR

HOST_PIPE End Point Pipe Status Clear
address_offset : 0x7E4 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle clear
bits : 0 - 0 (1 bit)

CURBK : Curren Bank clear
bits : 2 - 2 (1 bit)

PFREEZE : Pipe Freeze Clear
bits : 4 - 4 (1 bit)

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)


DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET

DEVICE_ENDPOINT End Point Pipe Status Set
address_offset : 0x7E5 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Set
bits : 0 - 0 (1 bit)

DTGLIN : Data Toggle IN Set
bits : 1 - 1 (1 bit)

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)

STALLRQ0 : Stall 0 Request Set
bits : 4 - 4 (1 bit)

STALLRQ1 : Stall 1 Request Set
bits : 5 - 5 (1 bit)

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)


HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET

HOST_PIPE End Point Pipe Status Set
address_offset : 0x7E5 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle Set
bits : 0 - 0 (1 bit)

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)

PFREEZE : Pipe Freeze Set
bits : 4 - 4 (1 bit)

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)


DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS

DEVICE_ENDPOINT End Point Pipe Status
address_offset : 0x7E6 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle Out
bits : 0 - 0 (1 bit)

DTGLIN : Data Toggle In
bits : 1 - 1 (1 bit)

CURBK : Current Bank
bits : 2 - 2 (1 bit)

STALLRQ0 : Stall 0 Request
bits : 4 - 4 (1 bit)

STALLRQ1 : Stall 1 Request
bits : 5 - 5 (1 bit)

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)


HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS

HOST_PIPE End Point Pipe Status
address_offset : 0x7E6 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle
bits : 0 - 0 (1 bit)

CURBK : Current Bank
bits : 2 - 2 (1 bit)

PFREEZE : Pipe Freeze
bits : 4 - 4 (1 bit)

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)


DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG

DEVICE_ENDPOINT End Point Interrupt Flag
address_offset : 0x7E7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1
bits : 3 - 3 (1 bit)

RXSTP : Received Setup
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out
bits : 6 - 6 (1 bit)


HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG

HOST_PIPE Pipe Interrupt Flag
address_offset : 0x7E7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Flag
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Flag
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Flag
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Flag
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Flag
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Flag
bits : 5 - 5 (1 bit)


DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR

DEVICE_ENDPOINT End Point Interrupt Clear Flag
address_offset : 0x7E8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Disable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Disable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Disable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/Out Interrupt Disable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/Out Interrupt Disable
bits : 6 - 6 (1 bit)


HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR

HOST_PIPE Pipe Interrupt Flag Clear
address_offset : 0x7E8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Disable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Disable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL : Stall Inetrrupt Disable
bits : 5 - 5 (1 bit)


DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET

DEVICE_ENDPOINT End Point Interrupt Set Flag
address_offset : 0x7E9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Enable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Enable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out Interrupt enable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out Interrupt enable
bits : 6 - 6 (1 bit)


HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET

HOST_PIPE Pipe Interrupt Flag Set
address_offset : 0x7E9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Enable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Enable
bits : 5 - 5 (1 bit)


DEVICE - CTRLB

USB is Device - - DEVICE Control B
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE - CTRLB DEVICE - CTRLB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DETACH UPRSM SPDCONF NREPLY TSTJ TSTK TSTPCKT OPMODE2 GNAK LPMHDSK

DETACH : Detach
bits : 0 - 0 (1 bit)

UPRSM : Upstream Resume
bits : 1 - 1 (1 bit)

SPDCONF : Speed Configuration
bits : 2 - 3 (2 bit)

Enumeration: SPDCONFSelect

0x0 : FS

FS : Full Speed

0x1 : LS

LS : Low Speed

0x2 : HS

HS : High Speed capable

0x3 : HSTM

HSTM: High Speed Test Mode (force high-speed mode for test mode)

End of enumeration elements list.

NREPLY : No Reply
bits : 4 - 4 (1 bit)

TSTJ : Test mode J
bits : 5 - 5 (1 bit)

TSTK : Test mode K
bits : 6 - 6 (1 bit)

TSTPCKT : Test packet mode
bits : 7 - 7 (1 bit)

OPMODE2 : Specific Operational Mode
bits : 8 - 8 (1 bit)

GNAK : Global NAK
bits : 9 - 9 (1 bit)

LPMHDSK : Link Power Management Handshake
bits : 10 - 11 (2 bit)

Enumeration: LPMHDSKSelect

0 : NO

No handshake. LPM is not supported

1 : ACK

ACK

2 : NYET

NYET

3 : STALL

STALL

End of enumeration elements list.


HOST - CTRLB

USB is Host - - HOST Control B
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST - CTRLB HOST - CTRLB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESUME SPDCONF AUTORESUME TSTJ TSTK SOFE BUSRESET VBUSOK L1RESUME

RESUME : Send USB Resume
bits : 1 - 1 (1 bit)

SPDCONF : Speed Configuration for Host
bits : 2 - 3 (2 bit)

Enumeration: SPDCONFSelect

0x0 : NORMAL

Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable.

0x3 : FS

Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only.

End of enumeration elements list.

AUTORESUME : Auto Resume Enable
bits : 4 - 4 (1 bit)

TSTJ : Test mode J
bits : 5 - 5 (1 bit)

TSTK : Test mode K
bits : 6 - 6 (1 bit)

SOFE : Start of Frame Generation Enable
bits : 8 - 8 (1 bit)

BUSRESET : Send USB Reset
bits : 9 - 9 (1 bit)

VBUSOK : VBUS is OK
bits : 10 - 10 (1 bit)

L1RESUME : Send L1 Resume
bits : 11 - 11 (1 bit)


CTRLB

DEVICE Control B
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLB CTRLB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DETACH UPRSM RESUME SPDCONF NREPLY AUTORESUME TSTJ TSTK TSTPCKT OPMODE2 SOFE GNAK BUSRESET LPMHDSK VBUSOK L1RESUME

DETACH : Detach
bits : 0 - 0 (1 bit)

UPRSM : Upstream Resume
bits : 1 - 1 (1 bit)

RESUME : Send USB Resume
bits : 1 - 1 (1 bit)

SPDCONF : Speed Configuration for Host
bits : 2 - 3 (2 bit)

Enumeration: SPDCONFSelect

0x3 : FS

Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only.

0x1 : LS

LS : Low Speed

0x2 : HS

HS : High Speed capable

0x3 : HSTM

HSTM: High Speed Test Mode (force high-speed mode for test mode)

0x0 : NORMAL

Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable.

End of enumeration elements list.

NREPLY : No Reply
bits : 4 - 4 (1 bit)

AUTORESUME : Auto Resume Enable
bits : 4 - 4 (1 bit)

TSTJ : Test mode J
bits : 5 - 5 (1 bit)

TSTK : Test mode K
bits : 6 - 6 (1 bit)

TSTPCKT : Test packet mode
bits : 7 - 7 (1 bit)

OPMODE2 : Specific Operational Mode
bits : 8 - 8 (1 bit)

SOFE : Start of Frame Generation Enable
bits : 8 - 8 (1 bit)

GNAK : Global NAK
bits : 9 - 9 (1 bit)

BUSRESET : Send USB Reset
bits : 9 - 9 (1 bit)

LPMHDSK : Link Power Management Handshake
bits : 10 - 11 (2 bit)

Enumeration: LPMHDSKSelect

0 : NO

No handshake. LPM is not supported

1 : ACK

ACK

2 : NYET

NYET

3 : STALL

STALL

End of enumeration elements list.

VBUSOK : VBUS is OK
bits : 10 - 10 (1 bit)

L1RESUME : Send L1 Resume
bits : 11 - 11 (1 bit)


EPINTENCLR

DEVICE_ENDPOINT End Point Interrupt Clear Flag
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPINTENCLR EPINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Disable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Disable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Disable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/Out Interrupt Disable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/Out Interrupt Disable
bits : 6 - 6 (1 bit)


PINTENCLR

HOST_PIPE Pipe Interrupt Flag Clear
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTENCLR PINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Disable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Disable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL : Stall Inetrrupt Disable
bits : 5 - 5 (1 bit)


EPINTENSET

DEVICE_ENDPOINT End Point Interrupt Set Flag
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPINTENSET EPINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Enable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Enable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out Interrupt enable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out Interrupt enable
bits : 6 - 6 (1 bit)


PINTENSET

HOST_PIPE Pipe Interrupt Flag Set
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTENSET PINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Enable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Enable
bits : 5 - 5 (1 bit)


DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG

DEVICE_ENDPOINT End Point Configuration
address_offset : 0x9A0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPTYPE0 EPTYPE1 NYETDIS

EPTYPE0 : End Point Type0
bits : 0 - 2 (3 bit)

EPTYPE1 : End Point Type1
bits : 4 - 6 (3 bit)

NYETDIS : NYET Token Disable
bits : 7 - 7 (1 bit)


HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG

HOST_PIPE End Point Configuration
address_offset : 0x9A0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PTOKEN BK PTYPE

PTOKEN : Pipe Token
bits : 0 - 1 (2 bit)

BK : Pipe Bank
bits : 2 - 2 (1 bit)

PTYPE : Pipe Type
bits : 3 - 5 (3 bit)


HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL

HOST_PIPE Bus Access Period of Pipe
address_offset : 0x9A3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BITINTERVAL

BITINTERVAL : Bit Interval
bits : 0 - 7 (8 bit)


DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR

DEVICE_ENDPOINT End Point Pipe Status Clear
address_offset : 0x9A4 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Clear
bits : 0 - 0 (1 bit)

DTGLIN : Data Toggle IN Clear
bits : 1 - 1 (1 bit)

CURBK : Current Bank Clear
bits : 2 - 2 (1 bit)

STALLRQ0 : Stall 0 Request Clear
bits : 4 - 4 (1 bit)

STALLRQ1 : Stall 1 Request Clear
bits : 5 - 5 (1 bit)

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)


HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR

HOST_PIPE End Point Pipe Status Clear
address_offset : 0x9A4 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle clear
bits : 0 - 0 (1 bit)

CURBK : Curren Bank clear
bits : 2 - 2 (1 bit)

PFREEZE : Pipe Freeze Clear
bits : 4 - 4 (1 bit)

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)


DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET

DEVICE_ENDPOINT End Point Pipe Status Set
address_offset : 0x9A5 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Set
bits : 0 - 0 (1 bit)

DTGLIN : Data Toggle IN Set
bits : 1 - 1 (1 bit)

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)

STALLRQ0 : Stall 0 Request Set
bits : 4 - 4 (1 bit)

STALLRQ1 : Stall 1 Request Set
bits : 5 - 5 (1 bit)

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)


HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET

HOST_PIPE End Point Pipe Status Set
address_offset : 0x9A5 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle Set
bits : 0 - 0 (1 bit)

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)

PFREEZE : Pipe Freeze Set
bits : 4 - 4 (1 bit)

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)


DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS

DEVICE_ENDPOINT End Point Pipe Status
address_offset : 0x9A6 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle Out
bits : 0 - 0 (1 bit)

DTGLIN : Data Toggle In
bits : 1 - 1 (1 bit)

CURBK : Current Bank
bits : 2 - 2 (1 bit)

STALLRQ0 : Stall 0 Request
bits : 4 - 4 (1 bit)

STALLRQ1 : Stall 1 Request
bits : 5 - 5 (1 bit)

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)


HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS

HOST_PIPE End Point Pipe Status
address_offset : 0x9A6 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle
bits : 0 - 0 (1 bit)

CURBK : Current Bank
bits : 2 - 2 (1 bit)

PFREEZE : Pipe Freeze
bits : 4 - 4 (1 bit)

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)


DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG

DEVICE_ENDPOINT End Point Interrupt Flag
address_offset : 0x9A7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1
bits : 3 - 3 (1 bit)

RXSTP : Received Setup
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out
bits : 6 - 6 (1 bit)


HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG

HOST_PIPE Pipe Interrupt Flag
address_offset : 0x9A7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Flag
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Flag
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Flag
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Flag
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Flag
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Flag
bits : 5 - 5 (1 bit)


DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR

DEVICE_ENDPOINT End Point Interrupt Clear Flag
address_offset : 0x9A8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Disable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Disable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Disable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/Out Interrupt Disable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/Out Interrupt Disable
bits : 6 - 6 (1 bit)


HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR

HOST_PIPE Pipe Interrupt Flag Clear
address_offset : 0x9A8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Disable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Disable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL : Stall Inetrrupt Disable
bits : 5 - 5 (1 bit)


DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET

DEVICE_ENDPOINT End Point Interrupt Set Flag
address_offset : 0x9A9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Enable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Enable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out Interrupt enable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out Interrupt enable
bits : 6 - 6 (1 bit)


HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET

HOST_PIPE Pipe Interrupt Flag Set
address_offset : 0x9A9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Enable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Enable
bits : 5 - 5 (1 bit)


DEVICE - DADD

USB is Device - - DEVICE Device Address
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE - DADD DEVICE - DADD read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DADD ADDEN

DADD : Device Address
bits : 0 - 6 (7 bit)

ADDEN : Device Address Enable
bits : 7 - 7 (1 bit)


HOST - HSOFC

USB is Host - - HOST Host Start Of Frame Control
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST - HSOFC HOST - HSOFC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FLENC FLENCE

FLENC : Frame Length Control
bits : 0 - 3 (4 bit)

FLENCE : Frame Length Control Enable
bits : 7 - 7 (1 bit)


DADD

DEVICE Device Address
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DADD DADD read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DADD ADDEN

DADD : Device Address
bits : 0 - 6 (7 bit)

ADDEN : Device Address Enable
bits : 7 - 7 (1 bit)


HSOFC

HOST Host Start Of Frame Control
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSOFC HSOFC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FLENC FLENCE

FLENC : Frame Length Control
bits : 0 - 3 (4 bit)

FLENCE : Frame Length Control Enable
bits : 7 - 7 (1 bit)


DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG

DEVICE_ENDPOINT End Point Configuration
address_offset : 0xB80 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPTYPE0 EPTYPE1 NYETDIS

EPTYPE0 : End Point Type0
bits : 0 - 2 (3 bit)

EPTYPE1 : End Point Type1
bits : 4 - 6 (3 bit)

NYETDIS : NYET Token Disable
bits : 7 - 7 (1 bit)


HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG

HOST_PIPE End Point Configuration
address_offset : 0xB80 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PTOKEN BK PTYPE

PTOKEN : Pipe Token
bits : 0 - 1 (2 bit)

BK : Pipe Bank
bits : 2 - 2 (1 bit)

PTYPE : Pipe Type
bits : 3 - 5 (3 bit)


HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL

HOST_PIPE Bus Access Period of Pipe
address_offset : 0xB83 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BITINTERVAL

BITINTERVAL : Bit Interval
bits : 0 - 7 (8 bit)


DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR

DEVICE_ENDPOINT End Point Pipe Status Clear
address_offset : 0xB84 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Clear
bits : 0 - 0 (1 bit)

DTGLIN : Data Toggle IN Clear
bits : 1 - 1 (1 bit)

CURBK : Current Bank Clear
bits : 2 - 2 (1 bit)

STALLRQ0 : Stall 0 Request Clear
bits : 4 - 4 (1 bit)

STALLRQ1 : Stall 1 Request Clear
bits : 5 - 5 (1 bit)

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)


HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR

HOST_PIPE End Point Pipe Status Clear
address_offset : 0xB84 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle clear
bits : 0 - 0 (1 bit)

CURBK : Curren Bank clear
bits : 2 - 2 (1 bit)

PFREEZE : Pipe Freeze Clear
bits : 4 - 4 (1 bit)

BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)


DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET

DEVICE_ENDPOINT End Point Pipe Status Set
address_offset : 0xB85 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle OUT Set
bits : 0 - 0 (1 bit)

DTGLIN : Data Toggle IN Set
bits : 1 - 1 (1 bit)

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)

STALLRQ0 : Stall 0 Request Set
bits : 4 - 4 (1 bit)

STALLRQ1 : Stall 1 Request Set
bits : 5 - 5 (1 bit)

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)


HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET

HOST_PIPE End Point Pipe Status Set
address_offset : 0xB85 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle Set
bits : 0 - 0 (1 bit)

CURBK : Current Bank Set
bits : 2 - 2 (1 bit)

PFREEZE : Pipe Freeze Set
bits : 4 - 4 (1 bit)

BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)


DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS

DEVICE_ENDPOINT End Point Pipe Status
address_offset : 0xB86 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGLOUT DTGLIN CURBK STALLRQ0 STALLRQ1 BK0RDY BK1RDY

DTGLOUT : Data Toggle Out
bits : 0 - 0 (1 bit)

DTGLIN : Data Toggle In
bits : 1 - 1 (1 bit)

CURBK : Current Bank
bits : 2 - 2 (1 bit)

STALLRQ0 : Stall 0 Request
bits : 4 - 4 (1 bit)

STALLRQ1 : Stall 1 Request
bits : 5 - 5 (1 bit)

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)


HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS

HOST_PIPE End Point Pipe Status
address_offset : 0xB86 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DTGL CURBK PFREEZE BK0RDY BK1RDY

DTGL : Data Toggle
bits : 0 - 0 (1 bit)

CURBK : Current Bank
bits : 2 - 2 (1 bit)

PFREEZE : Pipe Freeze
bits : 4 - 4 (1 bit)

BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)

BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)


DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG

DEVICE_ENDPOINT End Point Interrupt Flag
address_offset : 0xB87 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1
bits : 3 - 3 (1 bit)

RXSTP : Received Setup
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out
bits : 6 - 6 (1 bit)


HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG

HOST_PIPE Pipe Interrupt Flag
address_offset : 0xB87 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Flag
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Flag
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Flag
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Flag
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Flag
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Flag
bits : 5 - 5 (1 bit)


DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR

DEVICE_ENDPOINT End Point Interrupt Clear Flag
address_offset : 0xB88 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Disable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Disable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Disable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/Out Interrupt Disable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/Out Interrupt Disable
bits : 6 - 6 (1 bit)


HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR

HOST_PIPE Pipe Interrupt Flag Clear
address_offset : 0xB88 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Disable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Disable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Disable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Disable
bits : 4 - 4 (1 bit)

STALL : Stall Inetrrupt Disable
bits : 5 - 5 (1 bit)


DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET

DEVICE_ENDPOINT End Point Interrupt Set Flag
address_offset : 0xB89 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL0 TRFAIL1 RXSTP STALL0 STALL1

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL0 : Error Flow 0 Interrupt Enable
bits : 2 - 2 (1 bit)

TRFAIL1 : Error Flow 1 Interrupt Enable
bits : 3 - 3 (1 bit)

RXSTP : Received Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL0 : Stall 0 In/out Interrupt enable
bits : 5 - 5 (1 bit)

STALL1 : Stall 1 In/out Interrupt enable
bits : 6 - 6 (1 bit)


HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET

HOST_PIPE Pipe Interrupt Flag Set
address_offset : 0xB89 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRCPT0 TRCPT1 TRFAIL PERR TXSTP STALL

TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)

TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)

TRFAIL : Error Flow Interrupt Enable
bits : 2 - 2 (1 bit)

PERR : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)

TXSTP : Transmit Setup Interrupt Enable
bits : 4 - 4 (1 bit)

STALL : Stall Interrupt Enable
bits : 5 - 5 (1 bit)


DEVICE - STATUS

USB is Device - - DEVICE Status
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE - STATUS DEVICE - STATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SPEED LINESTATE

SPEED : Speed Status
bits : 2 - 3 (2 bit)

Enumeration: SPEEDSelect

0x0 : FS

Full-speed mode

0x1 : LS

Low-speed mode

0x2 : HS

High-speed mode

End of enumeration elements list.

LINESTATE : USB Line State Status
bits : 6 - 7 (2 bit)

Enumeration: LINESTATESelect

0x0 : 0

SE0/RESET

0x1 : 1

FS-J or LS-K State

0x2 : 2

FS-K or LS-J State

End of enumeration elements list.


HOST - STATUS

USB is Host - - HOST Status
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST - STATUS HOST - STATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SPEED LINESTATE

SPEED : Speed Status
bits : 2 - 3 (2 bit)

LINESTATE : USB Line State Status
bits : 6 - 7 (2 bit)


STATUS

DEVICE Status
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SPEED LINESTATE

SPEED : Speed Status
bits : 2 - 3 (2 bit)
access : read-only

Enumeration: SPEEDSelect

0x0 : FS

Full-speed mode

0x1 : LS

Low-speed mode

0x2 : HS

High-speed mode

End of enumeration elements list.

LINESTATE : USB Line State Status
bits : 6 - 7 (2 bit)
access : read-only

Enumeration: LINESTATESelect

0x0 : 0

SE0/RESET

0x1 : 1

FS-J or LS-K State

0x2 : 2

FS-K or LS-J State

End of enumeration elements list.


DEVICE - FSMSTATUS

USB is Device - - Finite State Machine Status
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE - FSMSTATUS DEVICE - FSMSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FSMSTATE

FSMSTATE : Fine State Machine Status
bits : 0 - 6 (7 bit)

Enumeration: FSMSTATESelect

0x1 : OFF

OFF (L3). It corresponds to the powered-off, disconnected, and disabled state

0x2 : ON

ON (L0). It corresponds to the Idle and Active states

0x4 : SUSPEND

SUSPEND (L2)

0x8 : SLEEP

SLEEP (L1)

0x10 : DNRESUME

DNRESUME. Down Stream Resume.

0x20 : UPRESUME

UPRESUME. Up Stream Resume.

0x40 : RESET

RESET. USB lines Reset.

End of enumeration elements list.


HOST - FSMSTATUS

USB is Host - - Finite State Machine Status
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HOST - FSMSTATUS HOST - FSMSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FSMSTATE

FSMSTATE : Fine State Machine Status
bits : 0 - 6 (7 bit)

Enumeration: FSMSTATESelect

0x1 : OFF

OFF (L3). It corresponds to the powered-off, disconnected, and disabled state

0x2 : ON

ON (L0). It corresponds to the Idle and Active states

0x4 : SUSPEND

SUSPEND (L2)

0x8 : SLEEP

SLEEP (L1)

0x10 : DNRESUME

DNRESUME. Down Stream Resume.

0x20 : UPRESUME

UPRESUME. Up Stream Resume.

0x40 : RESET

RESET. USB lines Reset.

End of enumeration elements list.


FSMSTATUS

Finite State Machine Status
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FSMSTATUS FSMSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FSMSTATE

FSMSTATE : Fine State Machine Status
bits : 0 - 6 (7 bit)
access : read-only

Enumeration: FSMSTATESelect

0x1 : OFF

OFF (L3). It corresponds to the powered-off, disconnected, and disabled state

0x2 : ON

ON (L0). It corresponds to the Idle and Active states

0x4 : SUSPEND

SUSPEND (L2)

0x8 : SLEEP

SLEEP (L1)

0x10 : DNRESUME

DNRESUME. Down Stream Resume.

0x20 : UPRESUME

UPRESUME. Up Stream Resume.

0x40 : RESET

RESET. USB lines Reset.

End of enumeration elements list.



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