\n

DAC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection :

Registers

CTRLA

CTRLB

DATA0

DATA1

DATABUF0

DATABUF1

DACCTRL[0]

DBGCTRL

RESULT0

RESULT1

EVCTRL

DATA[0]

DACCTRL[1]

DATABUF[0]

DATA[1]

RESULT[0]

DATABUF[1]

INTENCLR

INTENSET

RESULT[1]

INTFLAG

STATUS

SYNCBUSY

DACCTRL0

DACCTRL1


CTRLA

Control A
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLA CTRLA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SWRST ENABLE

SWRST : Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Enable DAC Controller
bits : 1 - 1 (1 bit)


CTRLB

Control B
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLB CTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DIFF REFSEL

DIFF : Differential mode enable
bits : 0 - 0 (1 bit)

REFSEL : Reference Selection for DAC0/1
bits : 1 - 2 (2 bit)

Enumeration: REFSELSelect

0 : VREFPU

External reference unbuffered

1 : VDDANA

Analog supply

2 : VREFPB

External reference buffered

3 : INTREF

Internal bandgap reference

End of enumeration elements list.


DATA0

DAC n Data
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DATA0 DATA0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DAC0 Data
bits : 0 - 15 (16 bit)
access : write-only


DATA1

DAC n Data
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DATA1 DATA1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DAC0 Data
bits : 0 - 15 (16 bit)
access : write-only


DATABUF0

DAC n Data Buffer
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DATABUF0 DATABUF0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATABUF

DATABUF : DAC0 Data Buffer
bits : 0 - 15 (16 bit)
access : write-only


DATABUF1

DAC n Data Buffer
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DATABUF1 DATABUF1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATABUF

DATABUF : DAC0 Data Buffer
bits : 0 - 15 (16 bit)
access : write-only


DACCTRL[0]

DAC n Control
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DACCTRL[0] DACCTRL[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEFTADJ ENABLE CCTRL FEXT RUNSTDBY DITHER REFRESH OSR

LEFTADJ : Left Adjusted Data
bits : 0 - 0 (1 bit)

ENABLE : Enable DAC0
bits : 1 - 1 (1 bit)

CCTRL : Current Control
bits : 2 - 3 (2 bit)

Enumeration: CCTRLSelect

0x0 : CC100K

100kSPS

0x1 : CC1M

500kSPS

0x2 : CC12M

1MSPS

End of enumeration elements list.

FEXT : Standalone Filter
bits : 5 - 5 (1 bit)

RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)

DITHER : Dithering Mode
bits : 7 - 7 (1 bit)

REFRESH : Refresh period
bits : 8 - 11 (4 bit)

Enumeration: REFRESHSelect

0 : REFRESH_0

Do not Refresh

1 : REFRESH_1

Refresh every 30 us

2 : REFRESH_2

Refresh every 60 us

3 : REFRESH_3

Refresh every 90 us

4 : REFRESH_4

Refresh every 120 us

5 : REFRESH_5

Refresh every 150 us

6 : REFRESH_6

Refresh every 180 us

7 : REFRESH_7

Refresh every 210 us

8 : REFRESH_8

Refresh every 240 us

9 : REFRESH_9

Refresh every 270 us

10 : REFRESH_10

Refresh every 300 us

11 : REFRESH_11

Refresh every 330 us

12 : REFRESH_12

Refresh every 360 us

13 : REFRESH_13

Refresh every 390 us

14 : REFRESH_14

Refresh every 420 us

15 : REFRESH_15

Refresh every 450 us

End of enumeration elements list.

OSR : Sampling Rate
bits : 13 - 15 (3 bit)

Enumeration: OSRSelect

0 : OSR_1

No Over Sampling

1 : OSR_2

2x Over Sampling Ratio

2 : OSR_4

4x Over Sampling Ratio

3 : OSR_8

8x Over Sampling Ratio

4 : OSR_16

16x Over Sampling Ratio

5 : OSR_32

32x Over Sampling Ratio

End of enumeration elements list.


DBGCTRL

Debug Control
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGCTRL DBGCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DBGRUN

DBGRUN : Debug Run
bits : 0 - 0 (1 bit)


RESULT0

Filter Result
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESULT0 RESULT0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT

RESULT : Filter Result
bits : 0 - 15 (16 bit)
access : read-only


RESULT1

Filter Result
address_offset : 0x1E Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESULT1 RESULT1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT

RESULT : Filter Result
bits : 0 - 15 (16 bit)
access : read-only


EVCTRL

Event Control
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVCTRL EVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 STARTEI0 STARTEI1 EMPTYEO0 EMPTYEO1 INVEI0 INVEI1 RESRDYEO0 RESRDYEO1

STARTEI0 : Start Conversion Event Input DAC 0
bits : 0 - 0 (1 bit)

STARTEI1 : Start Conversion Event Input DAC 1
bits : 1 - 1 (1 bit)

EMPTYEO0 : Data Buffer Empty Event Output DAC 0
bits : 2 - 2 (1 bit)

EMPTYEO1 : Data Buffer Empty Event Output DAC 1
bits : 3 - 3 (1 bit)

INVEI0 : Enable Invertion of DAC 0 input event
bits : 4 - 4 (1 bit)

INVEI1 : Enable Invertion of DAC 1 input event
bits : 5 - 5 (1 bit)

RESRDYEO0 : Result Ready Event Output 0
bits : 6 - 6 (1 bit)

RESRDYEO1 : Result Ready Event Output 1
bits : 7 - 7 (1 bit)


DATA[0]

DAC n Data
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DATA[0] DATA[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DAC0 Data
bits : 0 - 15 (16 bit)


DACCTRL[1]

DAC n Control
address_offset : 0x26 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DACCTRL[1] DACCTRL[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEFTADJ ENABLE CCTRL FEXT RUNSTDBY DITHER REFRESH OSR

LEFTADJ : Left Adjusted Data
bits : 0 - 0 (1 bit)

ENABLE : Enable DAC0
bits : 1 - 1 (1 bit)

CCTRL : Current Control
bits : 2 - 3 (2 bit)

Enumeration: CCTRLSelect

0x0 : CC100K

100kSPS

0x1 : CC1M

500kSPS

0x2 : CC12M

1MSPS

End of enumeration elements list.

FEXT : Standalone Filter
bits : 5 - 5 (1 bit)

RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)

DITHER : Dithering Mode
bits : 7 - 7 (1 bit)

REFRESH : Refresh period
bits : 8 - 11 (4 bit)

Enumeration: REFRESHSelect

0 : REFRESH_0

Do not Refresh

1 : REFRESH_1

Refresh every 30 us

2 : REFRESH_2

Refresh every 60 us

3 : REFRESH_3

Refresh every 90 us

4 : REFRESH_4

Refresh every 120 us

5 : REFRESH_5

Refresh every 150 us

6 : REFRESH_6

Refresh every 180 us

7 : REFRESH_7

Refresh every 210 us

8 : REFRESH_8

Refresh every 240 us

9 : REFRESH_9

Refresh every 270 us

10 : REFRESH_10

Refresh every 300 us

11 : REFRESH_11

Refresh every 330 us

12 : REFRESH_12

Refresh every 360 us

13 : REFRESH_13

Refresh every 390 us

14 : REFRESH_14

Refresh every 420 us

15 : REFRESH_15

Refresh every 450 us

End of enumeration elements list.

OSR : Sampling Rate
bits : 13 - 15 (3 bit)

Enumeration: OSRSelect

0 : OSR_1

No Over Sampling

1 : OSR_2

2x Over Sampling Ratio

2 : OSR_4

4x Over Sampling Ratio

3 : OSR_8

8x Over Sampling Ratio

4 : OSR_16

16x Over Sampling Ratio

5 : OSR_32

32x Over Sampling Ratio

End of enumeration elements list.


DATABUF[0]

DAC n Data Buffer
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DATABUF[0] DATABUF[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATABUF

DATABUF : DAC0 Data Buffer
bits : 0 - 15 (16 bit)


DATA[1]

DAC n Data
address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DATA[1] DATA[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DAC0 Data
bits : 0 - 15 (16 bit)


RESULT[0]

Filter Result
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESULT[0] RESULT[0] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT

RESULT : Filter Result
bits : 0 - 15 (16 bit)


DATABUF[1]

DAC n Data Buffer
address_offset : 0x3E Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DATABUF[1] DATABUF[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATABUF

DATABUF : DAC0 Data Buffer
bits : 0 - 15 (16 bit)


INTENCLR

Interrupt Enable Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 UNDERRUN0 UNDERRUN1 EMPTY0 EMPTY1 RESRDY0 RESRDY1 OVERRUN0 OVERRUN1

UNDERRUN0 : Underrun 0 Interrupt Enable
bits : 0 - 0 (1 bit)

UNDERRUN1 : Underrun 1 Interrupt Enable
bits : 1 - 1 (1 bit)

EMPTY0 : Data Buffer 0 Empty Interrupt Enable
bits : 2 - 2 (1 bit)

EMPTY1 : Data Buffer 1 Empty Interrupt Enable
bits : 3 - 3 (1 bit)

RESRDY0 : Result 0 Ready Interrupt Enable
bits : 4 - 4 (1 bit)

RESRDY1 : Result 1 Ready Interrupt Enable
bits : 5 - 5 (1 bit)

OVERRUN0 : Overrun 0 Interrupt Enable
bits : 6 - 6 (1 bit)

OVERRUN1 : Overrun 1 Interrupt Enable
bits : 7 - 7 (1 bit)


INTENSET

Interrupt Enable Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 UNDERRUN0 UNDERRUN1 EMPTY0 EMPTY1 RESRDY0 RESRDY1 OVERRUN0 OVERRUN1

UNDERRUN0 : Underrun 0 Interrupt Enable
bits : 0 - 0 (1 bit)

UNDERRUN1 : Underrun 1 Interrupt Enable
bits : 1 - 1 (1 bit)

EMPTY0 : Data Buffer 0 Empty Interrupt Enable
bits : 2 - 2 (1 bit)

EMPTY1 : Data Buffer 1 Empty Interrupt Enable
bits : 3 - 3 (1 bit)

RESRDY0 : Result 0 Ready Interrupt Enable
bits : 4 - 4 (1 bit)

RESRDY1 : Result 1 Ready Interrupt Enable
bits : 5 - 5 (1 bit)

OVERRUN0 : Overrun 0 Interrupt Enable
bits : 6 - 6 (1 bit)

OVERRUN1 : Overrun 1 Interrupt Enable
bits : 7 - 7 (1 bit)


RESULT[1]

Filter Result
address_offset : 0x56 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESULT[1] RESULT[1] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT

RESULT : Filter Result
bits : 0 - 15 (16 bit)


INTFLAG

Interrupt Flag Status and Clear
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAG INTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 UNDERRUN0 UNDERRUN1 EMPTY0 EMPTY1 RESRDY0 RESRDY1 OVERRUN0 OVERRUN1

UNDERRUN0 : Result 0 Underrun
bits : 0 - 0 (1 bit)

UNDERRUN1 : Result 1 Underrun
bits : 1 - 1 (1 bit)

EMPTY0 : Data Buffer 0 Empty
bits : 2 - 2 (1 bit)

EMPTY1 : Data Buffer 1 Empty
bits : 3 - 3 (1 bit)

RESRDY0 : Result 0 Ready
bits : 4 - 4 (1 bit)

RESRDY1 : Result 1 Ready
bits : 5 - 5 (1 bit)

OVERRUN0 : Result 0 Overrun
bits : 6 - 6 (1 bit)

OVERRUN1 : Result 1 Overrun
bits : 7 - 7 (1 bit)


STATUS

Status
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 READY0 READY1 EOC0 EOC1

READY0 : DAC 0 Startup Ready
bits : 0 - 0 (1 bit)

READY1 : DAC 1 Startup Ready
bits : 1 - 1 (1 bit)

EOC0 : DAC 0 End of Conversion
bits : 2 - 2 (1 bit)

EOC1 : DAC 1 End of Conversion
bits : 3 - 3 (1 bit)


SYNCBUSY

Synchronization Busy
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYNCBUSY SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE DATA0 DATA1 DATABUF0 DATABUF1

SWRST : Software Reset
bits : 0 - 0 (1 bit)

ENABLE : DAC Enable Status
bits : 1 - 1 (1 bit)

DATA0 : Data DAC 0
bits : 2 - 2 (1 bit)

DATA1 : Data DAC 1
bits : 3 - 3 (1 bit)

DATABUF0 : Data Buffer DAC 0
bits : 4 - 4 (1 bit)

DATABUF1 : Data Buffer DAC 1
bits : 5 - 5 (1 bit)


DACCTRL0

DAC n Control
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DACCTRL0 DACCTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEFTADJ ENABLE CCTRL FEXT RUNSTDBY DITHER REFRESH OSR

LEFTADJ : Left Adjusted Data
bits : 0 - 0 (1 bit)

ENABLE : Enable DAC0
bits : 1 - 1 (1 bit)

CCTRL : Current Control
bits : 2 - 3 (2 bit)

Enumeration: CCTRLSelect

0x0 : CC100K

100kSPS

0x1 : CC1M

500kSPS

0x2 : CC12M

1MSPS

End of enumeration elements list.

FEXT : Standalone Filter
bits : 5 - 5 (1 bit)

RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)

DITHER : Dithering Mode
bits : 7 - 7 (1 bit)

REFRESH : Refresh period
bits : 8 - 11 (4 bit)

Enumeration: REFRESHSelect

0 : REFRESH_0

Do not Refresh

1 : REFRESH_1

Refresh every 30 us

2 : REFRESH_2

Refresh every 60 us

3 : REFRESH_3

Refresh every 90 us

4 : REFRESH_4

Refresh every 120 us

5 : REFRESH_5

Refresh every 150 us

6 : REFRESH_6

Refresh every 180 us

7 : REFRESH_7

Refresh every 210 us

8 : REFRESH_8

Refresh every 240 us

9 : REFRESH_9

Refresh every 270 us

10 : REFRESH_10

Refresh every 300 us

11 : REFRESH_11

Refresh every 330 us

12 : REFRESH_12

Refresh every 360 us

13 : REFRESH_13

Refresh every 390 us

14 : REFRESH_14

Refresh every 420 us

15 : REFRESH_15

Refresh every 450 us

End of enumeration elements list.

OSR : Sampling Rate
bits : 13 - 15 (3 bit)

Enumeration: OSRSelect

0 : OSR_1

No Over Sampling

1 : OSR_2

2x Over Sampling Ratio

2 : OSR_4

4x Over Sampling Ratio

3 : OSR_8

8x Over Sampling Ratio

4 : OSR_16

16x Over Sampling Ratio

5 : OSR_32

32x Over Sampling Ratio

End of enumeration elements list.


DACCTRL1

DAC n Control
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DACCTRL1 DACCTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEFTADJ ENABLE CCTRL FEXT RUNSTDBY DITHER REFRESH OSR

LEFTADJ : Left Adjusted Data
bits : 0 - 0 (1 bit)

ENABLE : Enable DAC0
bits : 1 - 1 (1 bit)

CCTRL : Current Control
bits : 2 - 3 (2 bit)

Enumeration: CCTRLSelect

0x0 : CC100K

100kSPS

0x1 : CC1M

500kSPS

0x2 : CC12M

1MSPS

End of enumeration elements list.

FEXT : Standalone Filter
bits : 5 - 5 (1 bit)

RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)

DITHER : Dithering Mode
bits : 7 - 7 (1 bit)

REFRESH : Refresh period
bits : 8 - 11 (4 bit)

Enumeration: REFRESHSelect

0 : REFRESH_0

Do not Refresh

1 : REFRESH_1

Refresh every 30 us

2 : REFRESH_2

Refresh every 60 us

3 : REFRESH_3

Refresh every 90 us

4 : REFRESH_4

Refresh every 120 us

5 : REFRESH_5

Refresh every 150 us

6 : REFRESH_6

Refresh every 180 us

7 : REFRESH_7

Refresh every 210 us

8 : REFRESH_8

Refresh every 240 us

9 : REFRESH_9

Refresh every 270 us

10 : REFRESH_10

Refresh every 300 us

11 : REFRESH_11

Refresh every 330 us

12 : REFRESH_12

Refresh every 360 us

13 : REFRESH_13

Refresh every 390 us

14 : REFRESH_14

Refresh every 420 us

15 : REFRESH_15

Refresh every 450 us

End of enumeration elements list.

OSR : Sampling Rate
bits : 13 - 15 (3 bit)

Enumeration: OSRSelect

0 : OSR_1

No Over Sampling

1 : OSR_2

2x Over Sampling Ratio

2 : OSR_4

4x Over Sampling Ratio

3 : OSR_8

8x Over Sampling Ratio

4 : OSR_16

16x Over Sampling Ratio

5 : OSR_32

32x Over Sampling Ratio

End of enumeration elements list.



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