\n
address_offset : 0x0 Bytes (0x0)
size : 0x38 byte (0x0)
mem_usage : registers
protection :
Control A
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Enable
bits : 1 - 1 (1 bit)
MODE : Operation Mode
bits : 2 - 3 (2 bit)
Enumeration: MODESelect
0 : QDEC
QDEC operating mode
1 : HALL
HALL operating mode
2 : COUNTER
COUNTER operating mode
End of enumeration elements list.
RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)
CONF : PDEC Configuration
bits : 8 - 10 (3 bit)
Enumeration: CONFSelect
0 : X4
Quadrature decoder direction
1 : X4S
Secure Quadrature decoder direction
2 : X2
Decoder direction
3 : X2S
Secure decoder direction
4 : AUTOC
Auto correction mode
End of enumeration elements list.
ALOCK : Auto Lock
bits : 11 - 11 (1 bit)
SWAP : PDEC Phase A and B Swap
bits : 14 - 14 (1 bit)
PEREN : Period Enable
bits : 15 - 15 (1 bit)
PINEN0 : PDEC Input From Pin 0 Enable
bits : 16 - 16 (1 bit)
PINEN1 : PDEC Input From Pin 1 Enable
bits : 17 - 17 (1 bit)
PINEN2 : PDEC Input From Pin 2 Enable
bits : 18 - 18 (1 bit)
PINVEN0 : IO Pin 0 Invert Enable
bits : 20 - 20 (1 bit)
PINVEN1 : IO Pin 1 Invert Enable
bits : 21 - 21 (1 bit)
PINVEN2 : IO Pin 2 Invert Enable
bits : 22 - 22 (1 bit)
ANGULAR : Angular Counter Length
bits : 24 - 26 (3 bit)
MAXCMP : Maximum Consecutive Missing Pulses
bits : 28 - 31 (4 bit)
Synchronization Status
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset Synchronization Busy
bits : 0 - 0 (1 bit)
ENABLE : Enable Synchronization Busy
bits : 1 - 1 (1 bit)
CTRLB : Control B Synchronization Busy
bits : 2 - 2 (1 bit)
STATUS : Status Synchronization Busy
bits : 3 - 3 (1 bit)
PRESC : Prescaler Synchronization Busy
bits : 4 - 4 (1 bit)
FILTER : Filter Synchronization Busy
bits : 5 - 5 (1 bit)
COUNT : Count Synchronization Busy
bits : 6 - 6 (1 bit)
CC0 : Compare Channel 0 Synchronization Busy
bits : 7 - 7 (1 bit)
CC1 : Compare Channel 1 Synchronization Busy
bits : 8 - 8 (1 bit)
Prescaler Value
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESC : Prescaler Value
bits : 0 - 3 (4 bit)
Enumeration: PRESCSelect
0 : DIV1
No division
1 : DIV2
Divide by 2
2 : DIV4
Divide by 4
3 : DIV8
Divide by 8
4 : DIV16
Divide by 16
5 : DIV32
Divide by 32
6 : DIV64
Divide by 64
7 : DIV128
Divide by 128
8 : DIV256
Divide by 256
9 : DIV512
Divide by 512
10 : DIV1024
Divide by 1024
End of enumeration elements list.
Filter Value
address_offset : 0x15 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILTER : Filter Value
bits : 0 - 7 (8 bit)
Prescaler Buffer Value
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESCBUF : Prescaler Buffer Value
bits : 0 - 3 (4 bit)
Enumeration: PRESCBUFSelect
0 : DIV1
No division
1 : DIV2
Divide by 2
2 : DIV4
Divide by 4
3 : DIV8
Divide by 8
4 : DIV16
Divide by 16
5 : DIV32
Divide by 32
6 : DIV64
Divide by 64
7 : DIV128
Divide by 128
8 : DIV256
Divide by 256
9 : DIV512
Divide by 512
10 : DIV1024
Divide by 1024
End of enumeration elements list.
Filter Buffer Value
address_offset : 0x19 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILTERBUF : Filter Buffer Value
bits : 0 - 7 (8 bit)
Counter Value
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Counter Value
bits : 0 - 15 (16 bit)
Channel n Compare Value
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Channel Compare Value
bits : 0 - 15 (16 bit)
Channel n Compare Value
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Channel Compare Value
bits : 0 - 15 (16 bit)
Channel Compare Buffer Value
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCBUF : Channel Compare Buffer Value
bits : 0 - 15 (16 bit)
Channel Compare Buffer Value
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCBUF : Channel Compare Buffer Value
bits : 0 - 15 (16 bit)
Control B Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LUPD : Lock Update
bits : 1 - 1 (1 bit)
CMD : Command
bits : 5 - 7 (3 bit)
Enumeration: CMDSelect
0 : NONE
No action
1 : RETRIGGER
Force a counter restart or retrigger
2 : UPDATE
Force update of double buffered registers
3 : READSYNC
Force a read synchronization of COUNT
4 : START
Start QDEC/HALL
5 : STOP
Stop QDEC/HALL
End of enumeration elements list.
Control B Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LUPD : Lock Update
bits : 1 - 1 (1 bit)
CMD : Command
bits : 5 - 7 (3 bit)
Enumeration: CMDSelect
0 : NONE
No action
1 : RETRIGGER
Force a counter restart or retrigger
2 : UPDATE
Force update of double buffered registers
3 : READSYNC
Force a read synchronization of COUNT
4 : START
Start QDEC/HALL
5 : STOP
Stop QDEC/HALL
End of enumeration elements list.
Event Control
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Event Action
bits : 0 - 1 (2 bit)
Enumeration: EVACTSelect
0 : OFF
Event action disabled
1 : RETRIGGER
Start, restart or retrigger on event
2 : COUNT
Count on event
End of enumeration elements list.
EVINV : Inverted Event Input Enable
bits : 2 - 4 (3 bit)
EVEI : Event Input Enable
bits : 5 - 7 (3 bit)
OVFEO : Overflow/Underflow Output Event Enable
bits : 8 - 8 (1 bit)
ERREO : Error Output Event Enable
bits : 9 - 9 (1 bit)
DIREO : Direction Output Event Enable
bits : 10 - 10 (1 bit)
VLCEO : Velocity Output Event Enable
bits : 11 - 11 (1 bit)
MCEO0 : Match Channel 0 Event Output Enable
bits : 12 - 12 (1 bit)
MCEO1 : Match Channel 1 Event Output Enable
bits : 13 - 13 (1 bit)
Interrupt Enable Clear
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : Overflow/Underflow Interrupt Disable
bits : 0 - 0 (1 bit)
ERR : Error Interrupt Disable
bits : 1 - 1 (1 bit)
DIR : Direction Interrupt Disable
bits : 2 - 2 (1 bit)
VLC : Velocity Interrupt Disable
bits : 3 - 3 (1 bit)
MC0 : Channel 0 Compare Match Disable
bits : 4 - 4 (1 bit)
MC1 : Channel 1 Compare Match Disable
bits : 5 - 5 (1 bit)
Interrupt Enable Set
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : Overflow/Underflow Interrupt Enable
bits : 0 - 0 (1 bit)
ERR : Error Interrupt Enable
bits : 1 - 1 (1 bit)
DIR : Direction Interrupt Enable
bits : 2 - 2 (1 bit)
VLC : Velocity Interrupt Enable
bits : 3 - 3 (1 bit)
MC0 : Channel 0 Compare Match Enable
bits : 4 - 4 (1 bit)
MC1 : Channel 1 Compare Match Enable
bits : 5 - 5 (1 bit)
Interrupt Flag Status and Clear
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : Overflow/Underflow
bits : 0 - 0 (1 bit)
ERR : Error
bits : 1 - 1 (1 bit)
DIR : Direction Change
bits : 2 - 2 (1 bit)
VLC : Velocity
bits : 3 - 3 (1 bit)
MC0 : Channel 0 Compare Match
bits : 4 - 4 (1 bit)
MC1 : Channel 1 Compare Match
bits : 5 - 5 (1 bit)
Status
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QERR : Quadrature Error Flag
bits : 0 - 0 (1 bit)
IDXERR : Index Error Flag
bits : 1 - 1 (1 bit)
MPERR : Missing Pulse Error flag
bits : 2 - 2 (1 bit)
WINERR : Window Error Flag
bits : 4 - 4 (1 bit)
HERR : Hall Error Flag
bits : 5 - 5 (1 bit)
STOP : Stop
bits : 6 - 6 (1 bit)
DIR : Direction Status Flag
bits : 7 - 7 (1 bit)
PRESCBUFV : Prescaler Buffer Valid
bits : 8 - 8 (1 bit)
FILTERBUFV : Filter Buffer Valid
bits : 9 - 9 (1 bit)
CCBUFV0 : Compare Channel 0 Buffer Valid
bits : 12 - 12 (1 bit)
CCBUFV1 : Compare Channel 1 Buffer Valid
bits : 13 - 13 (1 bit)
Debug Control
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGRUN : Debug Run Mode
bits : 0 - 0 (1 bit)
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