\n
address_offset : 0x0 Bytes (0x0)
size : 0xD byte (0x0)
mem_usage : registers
protection : not protected
Control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enable
bits : 1 - 1 (1 bit)
WEN : Watchdog Timer Window Mode Enable
bits : 2 - 2 (1 bit)
ALWAYSON : Always-On
bits : 7 - 7 (1 bit)
Configuration
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PER : Time-Out Period
bits : 0 - 3 (4 bit)
Enumeration: PERSelect
0x0 : CYC8
8 clock cycles
0x1 : CYC16
16 clock cycles
0x2 : CYC32
32 clock cycles
0x3 : CYC64
64 clock cycles
0x4 : CYC128
128 clock cycles
0x5 : CYC256
256 clock cycles
0x6 : CYC512
512 clock cycles
0x7 : CYC1024
1024 clock cycles
0x8 : CYC2048
2048 clock cycles
0x9 : CYC4096
4096 clock cycles
0xA : CYC8192
8192 clock cycles
0xB : CYC16384
16384 clock cycles
End of enumeration elements list.
WINDOW : Window Mode Time-Out Period
bits : 4 - 7 (4 bit)
Enumeration: WINDOWSelect
0x0 : CYC8
8 clock cycles
0x1 : CYC16
16 clock cycles
0x2 : CYC32
32 clock cycles
0x3 : CYC64
64 clock cycles
0x4 : CYC128
128 clock cycles
0x5 : CYC256
256 clock cycles
0x6 : CYC512
512 clock cycles
0x7 : CYC1024
1024 clock cycles
0x8 : CYC2048
2048 clock cycles
0x9 : CYC4096
4096 clock cycles
0xA : CYC8192
8192 clock cycles
0xB : CYC16384
16384 clock cycles
End of enumeration elements list.
Early Warning Interrupt Control
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EWOFFSET : Early Warning Interrupt Time Offset
bits : 0 - 3 (4 bit)
Enumeration: EWOFFSETSelect
0x0 : CYC8
8 clock cycles
0x1 : CYC16
16 clock cycles
0x2 : CYC32
32 clock cycles
0x3 : CYC64
64 clock cycles
0x4 : CYC128
128 clock cycles
0x5 : CYC256
256 clock cycles
0x6 : CYC512
512 clock cycles
0x7 : CYC1024
1024 clock cycles
0x8 : CYC2048
2048 clock cycles
0x9 : CYC4096
4096 clock cycles
0xA : CYC8192
8192 clock cycles
0xB : CYC16384
16384 clock cycles
End of enumeration elements list.
Interrupt Enable Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EW : Early Warning Interrupt Enable
bits : 0 - 0 (1 bit)
Interrupt Enable Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EW : Early Warning Interrupt Enable
bits : 0 - 0 (1 bit)
Interrupt Flag Status and Clear
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EW : Early Warning
bits : 0 - 0 (1 bit)
Synchronization Busy
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enable Synchronization Busy
bits : 1 - 1 (1 bit)
WEN : Window Enable Synchronization Busy
bits : 2 - 2 (1 bit)
ALWAYSON : Always-On Synchronization Busy
bits : 3 - 3 (1 bit)
CLEAR : Clear Synchronization Busy
bits : 4 - 4 (1 bit)
Clear
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLEAR : Watchdog Clear
bits : 0 - 7 (8 bit)
Enumeration: CLEARSelect
0xA5 : KEY
Clear Key
End of enumeration elements list.
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