\n

DMAC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection :

Registers

CTRL

SWTRIGCTRL

PRICTRL

CRCCTRL

INTPEND

INTSTATUS

BUSYCH

PENDCH

ACTIVE

BASEADDR

WRBADDR

CHID

CRCDATAIN

CHCTRLA

CHCTRLB

CHINTENCLR

CHINTENSET

CHINTFLAG

CHSTATUS

CRCCHKSUM

CRCSTATUS

DBGCTRL

QOSCTRL


CTRL

Control
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST DMAENABLE CRCENABLE LVLEN0 LVLEN1 LVLEN2 LVLEN3

SWRST : Software Reset
bits : 0 - 0 (1 bit)

DMAENABLE : DMA Enable
bits : 1 - 1 (1 bit)

CRCENABLE : CRC Enable
bits : 2 - 2 (1 bit)

LVLEN0 : Priority Level 0 Enable
bits : 8 - 8 (1 bit)

LVLEN1 : Priority Level 1 Enable
bits : 9 - 9 (1 bit)

LVLEN2 : Priority Level 2 Enable
bits : 10 - 10 (1 bit)

LVLEN3 : Priority Level 3 Enable
bits : 11 - 11 (1 bit)


SWTRIGCTRL

Software Trigger Control
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWTRIGCTRL SWTRIGCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWTRIG0 SWTRIG1 SWTRIG2 SWTRIG3 SWTRIG4 SWTRIG5 SWTRIG6 SWTRIG7 SWTRIG8 SWTRIG9 SWTRIG10 SWTRIG11

SWTRIG0 : Channel 0 Software Trigger
bits : 0 - 0 (1 bit)

SWTRIG1 : Channel 1 Software Trigger
bits : 1 - 1 (1 bit)

SWTRIG2 : Channel 2 Software Trigger
bits : 2 - 2 (1 bit)

SWTRIG3 : Channel 3 Software Trigger
bits : 3 - 3 (1 bit)

SWTRIG4 : Channel 4 Software Trigger
bits : 4 - 4 (1 bit)

SWTRIG5 : Channel 5 Software Trigger
bits : 5 - 5 (1 bit)

SWTRIG6 : Channel 6 Software Trigger
bits : 6 - 6 (1 bit)

SWTRIG7 : Channel 7 Software Trigger
bits : 7 - 7 (1 bit)

SWTRIG8 : Channel 8 Software Trigger
bits : 8 - 8 (1 bit)

SWTRIG9 : Channel 9 Software Trigger
bits : 9 - 9 (1 bit)

SWTRIG10 : Channel 10 Software Trigger
bits : 10 - 10 (1 bit)

SWTRIG11 : Channel 11 Software Trigger
bits : 11 - 11 (1 bit)


PRICTRL

Priority Control
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRICTRL PRICTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVLPRI0 RRLVLEN0 LVLPRI1 RRLVLEN1 LVLPRI2 RRLVLEN2 LVLPRI3 RRLVLEN3

LVLPRI0 : Level 0 Channel Priority Number
bits : 0 - 3 (4 bit)

RRLVLEN0 : Level 0 Round-Robin Scheduling Enable
bits : 7 - 7 (1 bit)

Enumeration: RRLVLEN0Select

0x0 : STATIC_LVL

Static arbitration scheme for channels with level 0 priority

0x1 : ROUND_ROBIN_LVL

Round-robin arbitration scheme for channels with level 0 priority

End of enumeration elements list.

LVLPRI1 : Level 1 Channel Priority Number
bits : 8 - 11 (4 bit)

RRLVLEN1 : Level 1 Round-Robin Scheduling Enable
bits : 15 - 15 (1 bit)

Enumeration: RRLVLEN1Select

0x0 : STATIC_LVL

Static arbitration scheme for channels with level 1 priority

0x1 : ROUND_ROBIN_LVL

Round-robin arbitration scheme for channels with level 1 priority

End of enumeration elements list.

LVLPRI2 : Level 2 Channel Priority Number
bits : 16 - 19 (4 bit)

RRLVLEN2 : Level 2 Round-Robin Scheduling Enable
bits : 23 - 23 (1 bit)

Enumeration: RRLVLEN2Select

0x0 : STATIC_LVL

Static arbitration scheme for channels with level 2 priority

0x1 : ROUND_ROBIN_LVL

Round-robin arbitration scheme for channels with level 2 priority

End of enumeration elements list.

LVLPRI3 : Level 3 Channel Priority Number
bits : 24 - 27 (4 bit)

RRLVLEN3 : Level 3 Round-Robin Scheduling Enable
bits : 31 - 31 (1 bit)

Enumeration: RRLVLEN3Select

0x0 : STATIC_LVL

Static arbitration scheme for channels with level 3 priority

0x1 : ROUND_ROBIN_LVL

Round-robin arbitration scheme for channels with level 3 priority

End of enumeration elements list.


CRCCTRL

CRC Control
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRCCTRL CRCCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRCBEATSIZE CRCPOLY CRCSRC

CRCBEATSIZE : CRC Beat Size
bits : 0 - 1 (2 bit)

Enumeration: CRCBEATSIZESelect

0x0 : BYTE

8-bit bus transfer

0x1 : HWORD

16-bit bus transfer

0x2 : WORD

32-bit bus transfer

End of enumeration elements list.

CRCPOLY : CRC Polynomial Type
bits : 2 - 3 (2 bit)

Enumeration: CRCPOLYSelect

0x0 : CRC16

CRC-16 (CRC-CCITT)

0x1 : CRC32

CRC32 (IEEE 802.3)

End of enumeration elements list.

CRCSRC : CRC Input Source
bits : 8 - 13 (6 bit)

Enumeration: CRCSRCSelect

0x00 : NOACT

No action

0x01 : IO

I/O interface

0x20 : CHN0

DMA Channel 0

0x21 : CHN1

DMA Channel 1

0x22 : CHN2

DMA Channel 2

0x23 : CHN3

DMA Channel 3

0x24 : CHN4

DMA Channel 4

0x25 : CHN5

DMA Channel 5

0x26 : CHN6

DMA Channel 6

0x27 : CHN7

DMA Channel 7

0x28 : CHN8

DMA Channel 8

0x29 : CHN9

DMA Channel 9

0x2A : CHN10

DMA Channel 10

0x2B : CHN11

DMA Channel 11

End of enumeration elements list.


INTPEND

Interrupt Pending
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTPEND INTPEND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID TERR TCMPL SUSP FERR BUSY PEND

ID : Channel ID
bits : 0 - 3 (4 bit)

TERR : Transfer Error
bits : 8 - 8 (1 bit)

TCMPL : Transfer Complete
bits : 9 - 9 (1 bit)

SUSP : Channel Suspend
bits : 10 - 10 (1 bit)

FERR : Fetch Error
bits : 13 - 13 (1 bit)

BUSY : Busy
bits : 14 - 14 (1 bit)

PEND : Pending
bits : 15 - 15 (1 bit)


INTSTATUS

Interrupt Status
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS INTSTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHINT0 CHINT1 CHINT2 CHINT3 CHINT4 CHINT5 CHINT6 CHINT7 CHINT8 CHINT9 CHINT10 CHINT11

CHINT0 : Channel 0 Pending Interrupt
bits : 0 - 0 (1 bit)

CHINT1 : Channel 1 Pending Interrupt
bits : 1 - 1 (1 bit)

CHINT2 : Channel 2 Pending Interrupt
bits : 2 - 2 (1 bit)

CHINT3 : Channel 3 Pending Interrupt
bits : 3 - 3 (1 bit)

CHINT4 : Channel 4 Pending Interrupt
bits : 4 - 4 (1 bit)

CHINT5 : Channel 5 Pending Interrupt
bits : 5 - 5 (1 bit)

CHINT6 : Channel 6 Pending Interrupt
bits : 6 - 6 (1 bit)

CHINT7 : Channel 7 Pending Interrupt
bits : 7 - 7 (1 bit)

CHINT8 : Channel 8 Pending Interrupt
bits : 8 - 8 (1 bit)

CHINT9 : Channel 9 Pending Interrupt
bits : 9 - 9 (1 bit)

CHINT10 : Channel 10 Pending Interrupt
bits : 10 - 10 (1 bit)

CHINT11 : Channel 11 Pending Interrupt
bits : 11 - 11 (1 bit)


BUSYCH

Busy Channels
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUSYCH BUSYCH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSYCH0 BUSYCH1 BUSYCH2 BUSYCH3 BUSYCH4 BUSYCH5 BUSYCH6 BUSYCH7 BUSYCH8 BUSYCH9 BUSYCH10 BUSYCH11

BUSYCH0 : Busy Channel 0
bits : 0 - 0 (1 bit)

BUSYCH1 : Busy Channel 1
bits : 1 - 1 (1 bit)

BUSYCH2 : Busy Channel 2
bits : 2 - 2 (1 bit)

BUSYCH3 : Busy Channel 3
bits : 3 - 3 (1 bit)

BUSYCH4 : Busy Channel 4
bits : 4 - 4 (1 bit)

BUSYCH5 : Busy Channel 5
bits : 5 - 5 (1 bit)

BUSYCH6 : Busy Channel 6
bits : 6 - 6 (1 bit)

BUSYCH7 : Busy Channel 7
bits : 7 - 7 (1 bit)

BUSYCH8 : Busy Channel 8
bits : 8 - 8 (1 bit)

BUSYCH9 : Busy Channel 9
bits : 9 - 9 (1 bit)

BUSYCH10 : Busy Channel 10
bits : 10 - 10 (1 bit)

BUSYCH11 : Busy Channel 11
bits : 11 - 11 (1 bit)


PENDCH

Pending Channels
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PENDCH PENDCH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PENDCH0 PENDCH1 PENDCH2 PENDCH3 PENDCH4 PENDCH5 PENDCH6 PENDCH7 PENDCH8 PENDCH9 PENDCH10 PENDCH11

PENDCH0 : Pending Channel 0
bits : 0 - 0 (1 bit)

PENDCH1 : Pending Channel 1
bits : 1 - 1 (1 bit)

PENDCH2 : Pending Channel 2
bits : 2 - 2 (1 bit)

PENDCH3 : Pending Channel 3
bits : 3 - 3 (1 bit)

PENDCH4 : Pending Channel 4
bits : 4 - 4 (1 bit)

PENDCH5 : Pending Channel 5
bits : 5 - 5 (1 bit)

PENDCH6 : Pending Channel 6
bits : 6 - 6 (1 bit)

PENDCH7 : Pending Channel 7
bits : 7 - 7 (1 bit)

PENDCH8 : Pending Channel 8
bits : 8 - 8 (1 bit)

PENDCH9 : Pending Channel 9
bits : 9 - 9 (1 bit)

PENDCH10 : Pending Channel 10
bits : 10 - 10 (1 bit)

PENDCH11 : Pending Channel 11
bits : 11 - 11 (1 bit)


ACTIVE

Active Channel and Levels
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ACTIVE ACTIVE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVLEX0 LVLEX1 LVLEX2 LVLEX3 ID ABUSY BTCNT

LVLEX0 : Level 0 Channel Trigger Request Executing
bits : 0 - 0 (1 bit)

LVLEX1 : Level 1 Channel Trigger Request Executing
bits : 1 - 1 (1 bit)

LVLEX2 : Level 2 Channel Trigger Request Executing
bits : 2 - 2 (1 bit)

LVLEX3 : Level 3 Channel Trigger Request Executing
bits : 3 - 3 (1 bit)

ID : Active Channel ID
bits : 8 - 12 (5 bit)

ABUSY : Active Channel Busy
bits : 15 - 15 (1 bit)

BTCNT : Active Channel Block Transfer Count
bits : 16 - 31 (16 bit)


BASEADDR

Descriptor Memory Section Base Address
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BASEADDR BASEADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASEADDR

BASEADDR : Descriptor Memory Base Address
bits : 0 - 31 (32 bit)


WRBADDR

Write-Back Memory Section Base Address
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRBADDR WRBADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRBADDR

WRBADDR : Write-Back Memory Base Address
bits : 0 - 31 (32 bit)


CHID

Channel ID
address_offset : 0x3F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID CHID read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ID

ID : Channel ID
bits : 0 - 3 (4 bit)


CRCDATAIN

CRC Data Input
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRCDATAIN CRCDATAIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRCDATAIN

CRCDATAIN : CRC Data Input
bits : 0 - 31 (32 bit)


CHCTRLA

Channel Control A
address_offset : 0x40 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA CHCTRLA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel run in standby
bits : 6 - 6 (1 bit)


CHCTRLB

Channel Control B
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB CHCTRLB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVACT EVIE EVOE LVL TRIGSRC TRIGACT CMD

EVACT : Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 3 - 3 (1 bit)

EVOE : Channel Event Output Enable
bits : 4 - 4 (1 bit)

LVL : Channel Arbitration Level
bits : 5 - 6 (2 bit)

Enumeration: LVLSelect

0x0 : LVL0

Channel Priority Level 0

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

End of enumeration elements list.

TRIGSRC : Trigger Source
bits : 8 - 13 (6 bit)

Enumeration: TRIGSRCSelect

0x00 : DISABLE

Only software/event triggers

0x01 : TSENS

TSENS Result Ready Trigger

0x02 : SERCOM0_RX

SERCOM0 RX Trigger

0x03 : SERCOM0_TX

SERCOM0 TX Trigger

0x04 : SERCOM1_RX

SERCOM1 RX Trigger

0x05 : SERCOM1_TX

SERCOM1 TX Trigger

0x06 : SERCOM2_RX

SERCOM2 RX Trigger

0x07 : SERCOM2_TX

SERCOM2 TX Trigger

0x08 : SERCOM3_RX

SERCOM3 RX Trigger

0x09 : SERCOM3_TX

SERCOM3 TX Trigger

0x0A : SERCOM4_RX

SERCOM4 RX Trigger

0x0B : SERCOM4_TX

SERCOM4 TX Trigger

0x0C : SERCOM5_RX

SERCOM5 RX Trigger

0x0D : SERCOM5_TX

SERCOM5 TX Trigger

0x10 : TCC0_OVF

TCC0 Overflow Trigger

0x11 : TCC0_MC0

TCC0 Match/Compare 0 Trigger

0x12 : TCC0_MC1

TCC0 Match/Compare 1 Trigger

0x13 : TCC0_MC2

TCC0 Match/Compare 2 Trigger

0x14 : TCC0_MC3

TCC0 Match/Compare 3 Trigger

0x15 : TCC1_OVF

TCC1 Overflow Trigger

0x16 : TCC1_MC0

TCC1 Match/Compare 0 Trigger

0x17 : TCC1_MC1

TCC1 Match/Compare 1 Trigger

0x18 : TCC2_OVF

TCC2 Overflow Trigger

0x19 : TCC2_MC0

TCC2 Match/Compare 0 Trigger

0x1A : TCC2_MC1

TCC2 Match/Compare 1 Trigger

0x1B : TC0_OVF

TC0 Overflow Trigger

0x1C : TC0_MC0

TC0 Match/Compare 0 Trigger

0x1D : TC0_MC1

TC0 Match/Compare 1 Trigger

0x1E : TC1_OVF

TC1 Overflow Trigger

0x1F : TC1_MC0

TC1 Match/Compare 0 Trigger

0x20 : TC1_MC1

TC1 Match/Compare 1 Trigger

0x21 : TC2_OVF

TC2 Overflow Trigger

0x22 : TC2_MC0

TC2 Match/Compare 0 Trigger

0x23 : TC2_MC1

TC2 Match/Compare 1 Trigger

0x24 : TC3_OVF

TC3 Overflow Trigger

0x25 : TC3_MC0

TC3 Match/Compare 0 Trigger

0x26 : TC3_MC1

TC3 Match/Compare 1 Trigger

0x27 : TC4_OVF

TC4 Overflow Trigger

0x28 : TC4_MC0

TC4 Match/Compare 0 Trigger

0x29 : TC4_MC1

TC4 Match/Compare 1 Trigger

0x2A : ADC0_RESRDY

ADC0 Result Ready Trigger

0x2B : ADC1_RESRDY

ADC1 Result Ready Trigger

0x2C : SDADC_RESRDY

SDADC Result Ready Trigger

0x2D : DAC_EMPTY

DAC Empty Trigger

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 22 - 23 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BEAT

One trigger required for each beat transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

CMD : Software Command
bits : 24 - 25 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHINTENCLR

Channel Interrupt Enable Clear
address_offset : 0x4C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET

Channel Interrupt Enable Set
address_offset : 0x4D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG

Channel Interrupt Flag Status and Clear
address_offset : 0x4E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS

Channel Status
address_offset : 0x4F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)


CRCCHKSUM

CRC Checksum
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRCCHKSUM CRCCHKSUM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRCCHKSUM

CRCCHKSUM : CRC Checksum
bits : 0 - 31 (32 bit)


CRCSTATUS

CRC Status
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRCSTATUS CRCSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CRCBUSY CRCZERO

CRCBUSY : CRC Module Busy
bits : 0 - 0 (1 bit)

CRCZERO : CRC Zero
bits : 1 - 1 (1 bit)


DBGCTRL

Debug Control
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGCTRL DBGCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DBGRUN

DBGRUN : Debug Run
bits : 0 - 0 (1 bit)


QOSCTRL

QOS Control
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QOSCTRL QOSCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WRBQOS FQOS DQOS

WRBQOS : Write-Back Quality of Service
bits : 0 - 1 (2 bit)

Enumeration: WRBQOSSelect

0x0 : DISABLE

Background (no sensitive operation)

0x1 : LOW

Sensitive Bandwidth

0x2 : MEDIUM

Sensitive Latency

0x3 : HIGH

Critical Latency

End of enumeration elements list.

FQOS : Fetch Quality of Service
bits : 2 - 3 (2 bit)

Enumeration: FQOSSelect

0x0 : DISABLE

Background (no sensitive operation)

0x1 : LOW

Sensitive Bandwidth

0x2 : MEDIUM

Sensitive Latency

0x3 : HIGH

Critical Latency

End of enumeration elements list.

DQOS : Data Transfer Quality of Service
bits : 4 - 5 (2 bit)

Enumeration: DQOSSelect

0x0 : DISABLE

Background (no sensitive operation)

0x1 : LOW

Sensitive Bandwidth

0x2 : MEDIUM

Sensitive Latency

0x3 : HIGH

Critical Latency

End of enumeration elements list.



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