\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
MTB Position
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRAP : Pointer Value Wraps
bits : 2 - 2 (1 bit)
POINTER : Trace Packet Location Pointer
bits : 3 - 31 (29 bit)
MTB Master
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK : Maximum Value of the Trace Buffer in SRAM
bits : 0 - 4 (5 bit)
TSTARTEN : Trace Start Input Enable
bits : 5 - 5 (1 bit)
TSTOPEN : Trace Stop Input Enable
bits : 6 - 6 (1 bit)
SFRWPRIV : Special Function Register Write Privilege
bits : 7 - 7 (1 bit)
RAMPRIV : SRAM Privilege
bits : 8 - 8 (1 bit)
HALTREQ : Halt Request
bits : 9 - 9 (1 bit)
EN : Main Trace Enable
bits : 31 - 31 (1 bit)
MTB Flow
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTOSTOP : Auto Stop Tracing
bits : 0 - 0 (1 bit)
AUTOHALT : Auto Halt Request
bits : 1 - 1 (1 bit)
WATERMARK : Watermark value
bits : 3 - 31 (29 bit)
MTB Base
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MTB Integration Mode Control
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MTB Claim Set
address_offset : 0xFA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MTB Claim Clear
address_offset : 0xFA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MTB Lock Access
address_offset : 0xFB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MTB Lock Status
address_offset : 0xFB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MTB Authentication Status
address_offset : 0xFB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MTB Device Architecture
address_offset : 0xFBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MTB Device Configuration
address_offset : 0xFC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MTB Device Type
address_offset : 0xFCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral Identification 4
address_offset : 0xFD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral Identification 5
address_offset : 0xFD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral Identification 6
address_offset : 0xFD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral Identification 7
address_offset : 0xFDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral Identification 0
address_offset : 0xFE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral Identification 1
address_offset : 0xFE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral Identification 2
address_offset : 0xFE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral Identification 3
address_offset : 0xFEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Component Identification 0
address_offset : 0xFF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Component Identification 1
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Component Identification 2
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Component Identification 3
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
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