Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x19C byte (0x0)
mem_usage : registers
protection :
Control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
Interrupt Enable Clear
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR0 : Channel 0 Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
OVR1 : Channel 1 Overrun Interrupt Enable
bits : 1 - 1 (1 bit)
OVR2 : Channel 2 Overrun Interrupt Enable
bits : 2 - 2 (1 bit)
OVR3 : Channel 3 Overrun Interrupt Enable
bits : 3 - 3 (1 bit)
OVR4 : Channel 4 Overrun Interrupt Enable
bits : 4 - 4 (1 bit)
OVR5 : Channel 5 Overrun Interrupt Enable
bits : 5 - 5 (1 bit)
OVR6 : Channel 6 Overrun Interrupt Enable
bits : 6 - 6 (1 bit)
OVR7 : Channel 7 Overrun Interrupt Enable
bits : 7 - 7 (1 bit)
OVR8 : Channel 8 Overrun Interrupt Enable
bits : 8 - 8 (1 bit)
OVR9 : Channel 9 Overrun Interrupt Enable
bits : 9 - 9 (1 bit)
OVR10 : Channel 10 Overrun Interrupt Enable
bits : 10 - 10 (1 bit)
OVR11 : Channel 11 Overrun Interrupt Enable
bits : 11 - 11 (1 bit)
EVD0 : Channel 0 Event Detection Interrupt Enable
bits : 16 - 16 (1 bit)
EVD1 : Channel 1 Event Detection Interrupt Enable
bits : 17 - 17 (1 bit)
EVD2 : Channel 2 Event Detection Interrupt Enable
bits : 18 - 18 (1 bit)
EVD3 : Channel 3 Event Detection Interrupt Enable
bits : 19 - 19 (1 bit)
EVD4 : Channel 4 Event Detection Interrupt Enable
bits : 20 - 20 (1 bit)
EVD5 : Channel 5 Event Detection Interrupt Enable
bits : 21 - 21 (1 bit)
EVD6 : Channel 6 Event Detection Interrupt Enable
bits : 22 - 22 (1 bit)
EVD7 : Channel 7 Event Detection Interrupt Enable
bits : 23 - 23 (1 bit)
EVD8 : Channel 8 Event Detection Interrupt Enable
bits : 24 - 24 (1 bit)
EVD9 : Channel 9 Event Detection Interrupt Enable
bits : 25 - 25 (1 bit)
EVD10 : Channel 10 Event Detection Interrupt Enable
bits : 26 - 26 (1 bit)
EVD11 : Channel 11 Event Detection Interrupt Enable
bits : 27 - 27 (1 bit)
User Multiplexer n
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
Interrupt Enable Set
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR0 : Channel 0 Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
OVR1 : Channel 1 Overrun Interrupt Enable
bits : 1 - 1 (1 bit)
OVR2 : Channel 2 Overrun Interrupt Enable
bits : 2 - 2 (1 bit)
OVR3 : Channel 3 Overrun Interrupt Enable
bits : 3 - 3 (1 bit)
OVR4 : Channel 4 Overrun Interrupt Enable
bits : 4 - 4 (1 bit)
OVR5 : Channel 5 Overrun Interrupt Enable
bits : 5 - 5 (1 bit)
OVR6 : Channel 6 Overrun Interrupt Enable
bits : 6 - 6 (1 bit)
OVR7 : Channel 7 Overrun Interrupt Enable
bits : 7 - 7 (1 bit)
OVR8 : Channel 8 Overrun Interrupt Enable
bits : 8 - 8 (1 bit)
OVR9 : Channel 9 Overrun Interrupt Enable
bits : 9 - 9 (1 bit)
OVR10 : Channel 10 Overrun Interrupt Enable
bits : 10 - 10 (1 bit)
OVR11 : Channel 11 Overrun Interrupt Enable
bits : 11 - 11 (1 bit)
EVD0 : Channel 0 Event Detection Interrupt Enable
bits : 16 - 16 (1 bit)
EVD1 : Channel 1 Event Detection Interrupt Enable
bits : 17 - 17 (1 bit)
EVD2 : Channel 2 Event Detection Interrupt Enable
bits : 18 - 18 (1 bit)
EVD3 : Channel 3 Event Detection Interrupt Enable
bits : 19 - 19 (1 bit)
EVD4 : Channel 4 Event Detection Interrupt Enable
bits : 20 - 20 (1 bit)
EVD5 : Channel 5 Event Detection Interrupt Enable
bits : 21 - 21 (1 bit)
EVD6 : Channel 6 Event Detection Interrupt Enable
bits : 22 - 22 (1 bit)
EVD7 : Channel 7 Event Detection Interrupt Enable
bits : 23 - 23 (1 bit)
EVD8 : Channel 8 Event Detection Interrupt Enable
bits : 24 - 24 (1 bit)
EVD9 : Channel 9 Event Detection Interrupt Enable
bits : 25 - 25 (1 bit)
EVD10 : Channel 10 Event Detection Interrupt Enable
bits : 26 - 26 (1 bit)
EVD11 : Channel 11 Event Detection Interrupt Enable
bits : 27 - 27 (1 bit)
Interrupt Flag Status and Clear
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR0 : Channel 0 Overrun
bits : 0 - 0 (1 bit)
OVR1 : Channel 1 Overrun
bits : 1 - 1 (1 bit)
OVR2 : Channel 2 Overrun
bits : 2 - 2 (1 bit)
OVR3 : Channel 3 Overrun
bits : 3 - 3 (1 bit)
OVR4 : Channel 4 Overrun
bits : 4 - 4 (1 bit)
OVR5 : Channel 5 Overrun
bits : 5 - 5 (1 bit)
OVR6 : Channel 6 Overrun
bits : 6 - 6 (1 bit)
OVR7 : Channel 7 Overrun
bits : 7 - 7 (1 bit)
OVR8 : Channel 8 Overrun
bits : 8 - 8 (1 bit)
OVR9 : Channel 9 Overrun
bits : 9 - 9 (1 bit)
OVR10 : Channel 10 Overrun
bits : 10 - 10 (1 bit)
OVR11 : Channel 11 Overrun
bits : 11 - 11 (1 bit)
EVD0 : Channel 0 Event Detection
bits : 16 - 16 (1 bit)
EVD1 : Channel 1 Event Detection
bits : 17 - 17 (1 bit)
EVD2 : Channel 2 Event Detection
bits : 18 - 18 (1 bit)
EVD3 : Channel 3 Event Detection
bits : 19 - 19 (1 bit)
EVD4 : Channel 4 Event Detection
bits : 20 - 20 (1 bit)
EVD5 : Channel 5 Event Detection
bits : 21 - 21 (1 bit)
EVD6 : Channel 6 Event Detection
bits : 22 - 22 (1 bit)
EVD7 : Channel 7 Event Detection
bits : 23 - 23 (1 bit)
EVD8 : Channel 8 Event Detection
bits : 24 - 24 (1 bit)
EVD9 : Channel 9 Event Detection
bits : 25 - 25 (1 bit)
EVD10 : Channel 10 Event Detection
bits : 26 - 26 (1 bit)
EVD11 : Channel 11 Event Detection
bits : 27 - 27 (1 bit)
Software Event
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHANNEL0 : Channel 0 Software Selection
bits : 0 - 0 (1 bit)
CHANNEL1 : Channel 1 Software Selection
bits : 1 - 1 (1 bit)
CHANNEL2 : Channel 2 Software Selection
bits : 2 - 2 (1 bit)
CHANNEL3 : Channel 3 Software Selection
bits : 3 - 3 (1 bit)
CHANNEL4 : Channel 4 Software Selection
bits : 4 - 4 (1 bit)
CHANNEL5 : Channel 5 Software Selection
bits : 5 - 5 (1 bit)
CHANNEL6 : Channel 6 Software Selection
bits : 6 - 6 (1 bit)
CHANNEL7 : Channel 7 Software Selection
bits : 7 - 7 (1 bit)
CHANNEL8 : Channel 8 Software Selection
bits : 8 - 8 (1 bit)
CHANNEL9 : Channel 9 Software Selection
bits : 9 - 9 (1 bit)
CHANNEL10 : Channel 10 Software Selection
bits : 10 - 10 (1 bit)
CHANNEL11 : Channel 11 Software Selection
bits : 11 - 11 (1 bit)
Channel n
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
Channel n
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
Channel n
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
Channel n
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
Channel n
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
Channel n
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
Channel n
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
Channel n
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
Channel n
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
Channel n
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
Channel n
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
Channel n
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
User Multiplexer n
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
Channel Status
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
USRRDY0 : Channel 0 User Ready
bits : 0 - 0 (1 bit)
USRRDY1 : Channel 1 User Ready
bits : 1 - 1 (1 bit)
USRRDY2 : Channel 2 User Ready
bits : 2 - 2 (1 bit)
USRRDY3 : Channel 3 User Ready
bits : 3 - 3 (1 bit)
USRRDY4 : Channel 4 User Ready
bits : 4 - 4 (1 bit)
USRRDY5 : Channel 5 User Ready
bits : 5 - 5 (1 bit)
USRRDY6 : Channel 6 User Ready
bits : 6 - 6 (1 bit)
USRRDY7 : Channel 7 User Ready
bits : 7 - 7 (1 bit)
USRRDY8 : Channel 8 User Ready
bits : 8 - 8 (1 bit)
USRRDY9 : Channel 9 User Ready
bits : 9 - 9 (1 bit)
USRRDY10 : Channel 10 User Ready
bits : 10 - 10 (1 bit)
USRRDY11 : Channel 11 User Ready
bits : 11 - 11 (1 bit)
CHBUSY0 : Channel 0 Busy
bits : 16 - 16 (1 bit)
CHBUSY1 : Channel 1 Busy
bits : 17 - 17 (1 bit)
CHBUSY2 : Channel 2 Busy
bits : 18 - 18 (1 bit)
CHBUSY3 : Channel 3 Busy
bits : 19 - 19 (1 bit)
CHBUSY4 : Channel 4 Busy
bits : 20 - 20 (1 bit)
CHBUSY5 : Channel 5 Busy
bits : 21 - 21 (1 bit)
CHBUSY6 : Channel 6 Busy
bits : 22 - 22 (1 bit)
CHBUSY7 : Channel 7 Busy
bits : 23 - 23 (1 bit)
CHBUSY8 : Channel 8 Busy
bits : 24 - 24 (1 bit)
CHBUSY9 : Channel 9 Busy
bits : 25 - 25 (1 bit)
CHBUSY10 : Channel 10 Busy
bits : 26 - 26 (1 bit)
CHBUSY11 : Channel 11 Busy
bits : 27 - 27 (1 bit)
User Multiplexer n
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
User Multiplexer n
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 4 (5 bit)
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