\n

RSTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x3 byte (0x0)
mem_usage : registers
protection : not protected

Registers

RCAUSE

BKUPEXIT


RCAUSE

Reset Cause
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RCAUSE RCAUSE read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 POR BODCORE BODVDD NVM EXT WDT SYST BACKUP

POR : Power On Reset
bits : 0 - 0 (1 bit)

BODCORE : Brown Out CORE Detector Reset
bits : 1 - 1 (1 bit)

BODVDD : Brown Out VDD Detector Reset
bits : 2 - 2 (1 bit)

NVM : NVM Reset
bits : 3 - 3 (1 bit)

EXT : External Reset
bits : 4 - 4 (1 bit)

WDT : Watchdog Reset
bits : 5 - 5 (1 bit)

SYST : System Reset Request
bits : 6 - 6 (1 bit)

BACKUP : Backup Reset
bits : 7 - 7 (1 bit)


BKUPEXIT

Backup Exit Source
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BKUPEXIT BKUPEXIT read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RTC BBPS HIB

RTC : Real Timer Counter Interrupt
bits : 1 - 1 (1 bit)

BBPS : Battery Backup Power Switch
bits : 2 - 2 (1 bit)

HIB : Hibernate
bits : 7 - 7 (1 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.