\n

GCLK

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

Registers

CTRL

STATUS

CLKCTRL

GENCTRL

GENDIV


CTRL

Control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SWRST

SWRST : Software Reset
bits : 0 - 0 (1 bit)


STATUS

Status
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SYNCBUSY

SYNCBUSY : Synchronization Busy Status
bits : 7 - 7 (1 bit)
access : read-only


CLKCTRL

Generic Clock Control
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKCTRL CLKCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID GEN CLKEN WRTLOCK

ID : Generic Clock Selection ID
bits : 0 - 5 (6 bit)

Enumeration: IDSelect

0x0 : DFLL48

DFLL48

0x1 : FDPLL

FDPLL

0x2 : FDPLL32K

FDPLL32K

0x3 : WDT

WDT

0x4 : RTC

RTC

0x5 : EIC

EIC

0x7 : EVSYS_0

EVSYS_0

0x8 : EVSYS_1

EVSYS_1

0x9 : EVSYS_2

EVSYS_2

0xa : EVSYS_3

EVSYS_3

0xb : EVSYS_4

EVSYS_4

0xc : EVSYS_5

EVSYS_5

0xd : SERCOMX_SLOW

SERCOMX_SLOW

0xe : SERCOM0_CORE

SERCOM0_CORE

0xf : SERCOM1_CORE

SERCOM1_CORE

0x10 : SERCOM2_CORE

SERCOM2_CORE

0x11 : TCC0

TCC0

0x12 : TC1_TC2

TC1_TC2

0x13 : ADC

ADC

0x14 : AC_DIG

AC_DIG

0x15 : AC_ANA

AC_ANA

0x16 : DAC

DAC

End of enumeration elements list.

GEN : Generic Clock Generator
bits : 8 - 11 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

End of enumeration elements list.

CLKEN : Clock Enable
bits : 14 - 14 (1 bit)

WRTLOCK : Write Lock
bits : 15 - 15 (1 bit)


GENCTRL

Generic Clock Generator Control
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GENCTRL GENCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID SRC GENEN IDC OOV OE DIVSEL RUNSTDBY

ID : Generic Clock Generator Selection
bits : 0 - 3 (4 bit)

SRC : Source Select
bits : 8 - 12 (5 bit)

Enumeration: SRCSelect

0x0 : XOSC

XOSC oscillator output

0x1 : GCLKIN

Generator input pad

0x2 : GCLKGEN1

Generic clock generator 1 output

0x3 : OSCULP32K

OSCULP32K oscillator output

0x4 : OSC32K

OSC32K oscillator output

0x5 : XOSC32K

XOSC32K oscillator output

0x6 : OSC8M

OSC8M oscillator output

0x7 : DFLL48M

DFLL48M output

0x8 : DPLL96M

DPLL96M output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 16 - 16 (1 bit)

IDC : Improve Duty Cycle
bits : 17 - 17 (1 bit)

OOV : Output Off Value
bits : 18 - 18 (1 bit)

OE : Output Enable
bits : 19 - 19 (1 bit)

DIVSEL : Divide Selection
bits : 20 - 20 (1 bit)

RUNSTDBY : Run in Standby
bits : 21 - 21 (1 bit)


GENDIV

Generic Clock Generator Division
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GENDIV GENDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID DIV

ID : Generic Clock Generator Selection
bits : 0 - 3 (4 bit)

DIV : Division Factor
bits : 8 - 23 (16 bit)



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