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SYSCTRL

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection :

Registers

INTENCLR

XOSC

XOSC32K

OSC32K

OSCULP32K

OSC8M

DFLLCTRL

DFLLVAL

DFLLMUL

DFLLSYNC

BOD33

VREG

INTENSET

VREF

INTFLAG

PCLKSR


INTENCLR

Interrupt Enable Clear
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XOSCRDY XOSC32KRDY OSC32KRDY OSC8MRDY DFLLRDY DFLLOOB DFLLLCKF DFLLLCKC DFLLRCS BOD33RDY BOD33DET B33SRDY

XOSCRDY : XOSC Ready
bits : 0 - 0 (1 bit)

XOSC32KRDY : XOSC32K Ready
bits : 1 - 1 (1 bit)

OSC32KRDY : OSC32K Ready
bits : 2 - 2 (1 bit)

OSC8MRDY : OSC8M Ready
bits : 3 - 3 (1 bit)

DFLLRDY : DFLL Ready
bits : 4 - 4 (1 bit)

DFLLOOB : DFLL Out Of Bounds
bits : 5 - 5 (1 bit)

DFLLLCKF : DFLL Lock Fine
bits : 6 - 6 (1 bit)

DFLLLCKC : DFLL Lock Coarse
bits : 7 - 7 (1 bit)

DFLLRCS : DFLL Reference Clock Stopped
bits : 8 - 8 (1 bit)

BOD33RDY : BOD33 Ready
bits : 9 - 9 (1 bit)

BOD33DET : BOD33 Detection
bits : 10 - 10 (1 bit)

B33SRDY : BOD33 Synchronization Ready
bits : 11 - 11 (1 bit)


XOSC

XOSC Control
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XOSC XOSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE XTALEN RUNSTDBY ONDEMAND GAIN AMPGC STARTUP

ENABLE : Enable
bits : 1 - 1 (1 bit)

XTALEN : Crystal Oscillator Enable
bits : 2 - 2 (1 bit)

RUNSTDBY : Run during Standby
bits : 6 - 6 (1 bit)

ONDEMAND : Enable on Demand
bits : 7 - 7 (1 bit)

GAIN : Gain Value
bits : 8 - 10 (3 bit)

AMPGC : Automatic Amplitude Gain Control
bits : 11 - 11 (1 bit)

STARTUP : Start-Up Time
bits : 12 - 15 (4 bit)


XOSC32K

XOSC32K Control
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XOSC32K XOSC32K read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE XTALEN EN32K EN1K AAMPEN RUNSTDBY ONDEMAND STARTUP WRTLOCK

ENABLE : Enable
bits : 1 - 1 (1 bit)

XTALEN : Crystal Oscillator Enable
bits : 2 - 2 (1 bit)

EN32K : 32kHz Output Enable
bits : 3 - 3 (1 bit)

EN1K : 1kHz Output Enable
bits : 4 - 4 (1 bit)

AAMPEN : Automatic Amplitude Control Enable
bits : 5 - 5 (1 bit)

RUNSTDBY : Run during Standby
bits : 6 - 6 (1 bit)

ONDEMAND : Enable on Demand
bits : 7 - 7 (1 bit)

STARTUP : Start-Up Time
bits : 8 - 10 (3 bit)

WRTLOCK : Write Lock
bits : 12 - 12 (1 bit)


OSC32K

OSC32K Control
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSC32K OSC32K read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE EN32K EN1K RUNSTDBY ONDEMAND STARTUP WRTLOCK CALIB

ENABLE : Enable
bits : 1 - 1 (1 bit)

EN32K : 32kHz Output Enable
bits : 2 - 2 (1 bit)

EN1K : 1kHz Output Enable
bits : 3 - 3 (1 bit)

RUNSTDBY : Run during Standby
bits : 6 - 6 (1 bit)

ONDEMAND : Enable on Demand
bits : 7 - 7 (1 bit)

STARTUP : Start-Up Time
bits : 8 - 10 (3 bit)

WRTLOCK : Write Lock
bits : 12 - 12 (1 bit)

CALIB : Calibration Value
bits : 16 - 22 (7 bit)


OSCULP32K

OSCULP32K Control
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSCULP32K OSCULP32K read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CALIB WRTLOCK

CALIB : Calibration Value
bits : 0 - 4 (5 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


OSC8M

OSC8M Control A
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSC8M OSC8M read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE RUNSTDBY ONDEMAND PRESC CALIB FRANGE

ENABLE : Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Run during Standby
bits : 6 - 6 (1 bit)

ONDEMAND : Enable on Demand
bits : 7 - 7 (1 bit)

PRESC : Prescaler Select
bits : 8 - 9 (2 bit)

CALIB : Calibration Value
bits : 16 - 27 (12 bit)

FRANGE : Frequency Range
bits : 30 - 31 (2 bit)


DFLLCTRL

DFLL Config
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFLLCTRL DFLLCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE MODE STABLE LLAW RUNSTDBY ONDEMAND CCDIS QLDIS

ENABLE : Enable
bits : 1 - 1 (1 bit)

MODE : Mode Selection
bits : 2 - 2 (1 bit)

STABLE : Stable Frequency
bits : 3 - 3 (1 bit)

LLAW : Lose Lock After Wake
bits : 4 - 4 (1 bit)

RUNSTDBY : Run during Standby
bits : 6 - 6 (1 bit)

ONDEMAND : Enable on Demand
bits : 7 - 7 (1 bit)

CCDIS : Chill Cycle Disable
bits : 8 - 8 (1 bit)

QLDIS : Quick Lock Disable
bits : 9 - 9 (1 bit)


DFLLVAL

DFLL Calibration Value
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFLLVAL DFLLVAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FINE COARSE DIFF

FINE : Fine Calibration Value
bits : 0 - 9 (10 bit)

COARSE : Coarse Calibration Value
bits : 10 - 15 (6 bit)

DIFF : Multiplication Ratio Difference
bits : 16 - 31 (16 bit)
access : read-only


DFLLMUL

DFLL Multiplier
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFLLMUL DFLLMUL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MUL FSTEP CSTEP

MUL : Multiplication Value
bits : 0 - 15 (16 bit)

FSTEP : Maximum Fine Step Size
bits : 16 - 25 (10 bit)

CSTEP : Maximum Coarse Step Size
bits : 26 - 31 (6 bit)


DFLLSYNC

DFLL Synchronization
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFLLSYNC DFLLSYNC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 READREQ

READREQ : Read Request Synchronization
bits : 7 - 7 (1 bit)
access : write-only


BOD33

3.3V Brown-Out Detector (BOD33) Control
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOD33 BOD33 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE HYST ACTION RUNSTDBY MODE CEN PSEL LEVEL

ENABLE : Enable
bits : 1 - 1 (1 bit)

HYST : Hysteresis Enable
bits : 2 - 2 (1 bit)

ACTION : Action when Threshold Crossed
bits : 3 - 4 (2 bit)

RUNSTDBY : Run during Standby
bits : 6 - 6 (1 bit)

MODE : Operation Modes
bits : 8 - 8 (1 bit)

CEN : Clock Enable
bits : 9 - 9 (1 bit)

PSEL : Prescaler Select
bits : 12 - 15 (4 bit)

LEVEL : Threshold Level
bits : 16 - 21 (6 bit)


VREG

VREG Control
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREG VREG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUNSTDBY FORCELDO

RUNSTDBY : Run during Standby
bits : 6 - 6 (1 bit)

FORCELDO : Force LDO Voltage Regulator
bits : 13 - 13 (1 bit)


INTENSET

Interrupt Enable Set
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XOSCRDY XOSC32KRDY OSC32KRDY OSC8MRDY DFLLRDY DFLLOOB DFLLLCKF DFLLLCKC DFLLRCS BOD33RDY BOD33DET B33SRDY

XOSCRDY : XOSC Ready
bits : 0 - 0 (1 bit)

XOSC32KRDY : XOSC32K Ready
bits : 1 - 1 (1 bit)

OSC32KRDY : OSC32K Ready
bits : 2 - 2 (1 bit)

OSC8MRDY : OSC8M Ready
bits : 3 - 3 (1 bit)

DFLLRDY : DFLL Ready
bits : 4 - 4 (1 bit)

DFLLOOB : DFLL Out Of Bounds
bits : 5 - 5 (1 bit)

DFLLLCKF : DFLL Lock Fine
bits : 6 - 6 (1 bit)

DFLLLCKC : DFLL Lock Coarse
bits : 7 - 7 (1 bit)

DFLLRCS : DFLL Reference Clock Stopped
bits : 8 - 8 (1 bit)

BOD33RDY : BOD33 Ready
bits : 9 - 9 (1 bit)

BOD33DET : BOD33 Detection
bits : 10 - 10 (1 bit)

B33SRDY : BOD33 Synchronization Ready
bits : 11 - 11 (1 bit)


VREF

VREF Control A
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREF VREF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSEN BGOUTEN CALIB

TSEN : Temperature Sensor Output Enable
bits : 1 - 1 (1 bit)

BGOUTEN : Bandgap Output Enable
bits : 2 - 2 (1 bit)

CALIB : Voltage Reference Calibration Value
bits : 16 - 26 (11 bit)


INTFLAG

Interrupt Flag Status and Clear
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAG INTFLAG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XOSCRDY XOSC32KRDY OSC32KRDY OSC8MRDY DFLLRDY DFLLOOB DFLLLCKF DFLLLCKC DFLLRCS BOD33RDY BOD33DET B33SRDY

XOSCRDY : XOSC Ready
bits : 0 - 0 (1 bit)

XOSC32KRDY : XOSC32K Ready
bits : 1 - 1 (1 bit)

OSC32KRDY : OSC32K Ready
bits : 2 - 2 (1 bit)

OSC8MRDY : OSC8M Ready
bits : 3 - 3 (1 bit)

DFLLRDY : DFLL Ready
bits : 4 - 4 (1 bit)

DFLLOOB : DFLL Out Of Bounds
bits : 5 - 5 (1 bit)

DFLLLCKF : DFLL Lock Fine
bits : 6 - 6 (1 bit)

DFLLLCKC : DFLL Lock Coarse
bits : 7 - 7 (1 bit)

DFLLRCS : DFLL Reference Clock Stopped
bits : 8 - 8 (1 bit)

BOD33RDY : BOD33 Ready
bits : 9 - 9 (1 bit)

BOD33DET : BOD33 Detection
bits : 10 - 10 (1 bit)

B33SRDY : BOD33 Synchronization Ready
bits : 11 - 11 (1 bit)


PCLKSR

Power and Clocks Status
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PCLKSR PCLKSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XOSCRDY XOSC32KRDY OSC32KRDY OSC8MRDY DFLLRDY DFLLOOB DFLLLCKF DFLLLCKC DFLLRCS BOD33RDY BOD33DET B33SRDY

XOSCRDY : XOSC Ready
bits : 0 - 0 (1 bit)
access : read-only

XOSC32KRDY : XOSC32K Ready
bits : 1 - 1 (1 bit)
access : read-only

OSC32KRDY : OSC32K Ready
bits : 2 - 2 (1 bit)
access : read-only

OSC8MRDY : OSC8M Ready
bits : 3 - 3 (1 bit)
access : read-only

DFLLRDY : DFLL Ready
bits : 4 - 4 (1 bit)
access : read-only

DFLLOOB : DFLL Out Of Bounds
bits : 5 - 5 (1 bit)
access : read-only

DFLLLCKF : DFLL Lock Fine
bits : 6 - 6 (1 bit)
access : read-only

DFLLLCKC : DFLL Lock Coarse
bits : 7 - 7 (1 bit)
access : read-only

DFLLRCS : DFLL Reference Clock Stopped
bits : 8 - 8 (1 bit)
access : read-only

BOD33RDY : BOD33 Ready
bits : 9 - 9 (1 bit)
access : read-only

BOD33DET : BOD33 Detection
bits : 10 - 10 (1 bit)
access : read-only

B33SRDY : BOD33 Synchronization Ready
bits : 11 - 11 (1 bit)
access : read-only



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