\n

DAC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

Registers

CTRLA

CTRLB

EVCTRL

INTENCLR

INTENSET

INTFLAG

STATUS

DATA

DATABUF


CTRLA

Control A
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLA CTRLA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY

SWRST : Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Run in Standby
bits : 2 - 2 (1 bit)


CTRLB

Control B
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLB CTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EOEN IOEN LEFTADJ VPD REFSEL

EOEN : External Output Enable
bits : 0 - 0 (1 bit)

IOEN : Internal Output Enable
bits : 1 - 1 (1 bit)

LEFTADJ : Left Adjusted Data
bits : 2 - 2 (1 bit)

VPD : Voltage Pump Disable
bits : 3 - 3 (1 bit)

REFSEL : Reference Selection
bits : 6 - 7 (2 bit)

Enumeration: REFSELSelect

0x0 : INT1V

Internal 1.0V reference

0x1 : AVCC

AVCC

0x2 : VREFP

External reference

End of enumeration elements list.


EVCTRL

Event Control
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVCTRL EVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 STARTEI EMPTYEO

STARTEI : Start Conversion Event Input
bits : 0 - 0 (1 bit)

EMPTYEO : Data Buffer Empty Event Output
bits : 1 - 1 (1 bit)


INTENCLR

Interrupt Enable Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 UNDERRUN EMPTY SYNCRDY

UNDERRUN : Underrun Interrupt Enable
bits : 0 - 0 (1 bit)

EMPTY : Data Buffer Empty Interrupt Enable
bits : 1 - 1 (1 bit)

SYNCRDY : Synchronization Ready Interrupt Enable
bits : 2 - 2 (1 bit)


INTENSET

Interrupt Enable Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 UNDERRUN EMPTY SYNCRDY

UNDERRUN : Underrun Interrupt Enable
bits : 0 - 0 (1 bit)

EMPTY : Data Buffer Empty Interrupt Enable
bits : 1 - 1 (1 bit)

SYNCRDY : Synchronization Ready Interrupt Enable
bits : 2 - 2 (1 bit)


INTFLAG

Interrupt Flag Status and Clear
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAG INTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 UNDERRUN EMPTY SYNCRDY

UNDERRUN : Underrun
bits : 0 - 0 (1 bit)

EMPTY : Data Buffer Empty
bits : 1 - 1 (1 bit)

SYNCRDY : Synchronization Ready
bits : 2 - 2 (1 bit)


STATUS

Status
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SYNCBUSY

SYNCBUSY : Synchronization Busy Status
bits : 7 - 7 (1 bit)
access : read-only


DATA

Data
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data to be converted
bits : 0 - 15 (16 bit)


DATABUF

Data Buffer
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATABUF DATABUF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATABUF

DATABUF : Data Buffer
bits : 0 - 15 (16 bit)



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