\n
address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected
Control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
CRC : 32-bit Cyclic Redundancy Code
bits : 2 - 2 (1 bit)
MBIST : Memory built-in self-test
bits : 3 - 3 (1 bit)
CE : Chip-Erase
bits : 4 - 4 (1 bit)
ARR : Auxiliary Row Read
bits : 6 - 6 (1 bit)
SMSA : Start Memory Stream Access
bits : 7 - 7 (1 bit)
Status A
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DONE : Done
bits : 0 - 0 (1 bit)
CRSTEXT : CPU Reset Phase Extension
bits : 1 - 1 (1 bit)
BERR : Bus Error
bits : 2 - 2 (1 bit)
FAIL : Failure
bits : 3 - 3 (1 bit)
PERR : Protection Error
bits : 4 - 4 (1 bit)
Debug Communication Channel n
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data
bits : 0 - 31 (32 bit)
CoreSight ROM Table Entry 0
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPRES : Entry Present
bits : 0 - 0 (1 bit)
FMT : Format
bits : 1 - 1 (1 bit)
ADDOFF : Address Offset
bits : 12 - 31 (20 bit)
CoreSight ROM Table Entry 1
address_offset : 0x1004 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CoreSight ROM Table End
address_offset : 0x1008 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
END : End Marker
bits : 0 - 31 (32 bit)
Debug Communication Channel n
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data
bits : 0 - 31 (32 bit)
Device Identification
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DEVSEL : Device Select
bits : 0 - 7 (8 bit)
REVISION : Revision Number
bits : 8 - 11 (4 bit)
DIE : Die Number
bits : 12 - 15 (4 bit)
SERIES : Series
bits : 16 - 21 (6 bit)
Enumeration: SERIESSelect
0 : 0
Cortex-M0+ processor, basic feature set
1 : 1
Cortex-M0+ processor, USB
End of enumeration elements list.
FAMILY : Family
bits : 23 - 27 (5 bit)
Enumeration: FAMILYSelect
0 : 0
General purpose microcontroller
1 : 1
PicoPower
End of enumeration elements list.
PROCESSOR : Processor
bits : 28 - 31 (4 bit)
Enumeration: PROCESSORSelect
0x1 : CM0P
Cortex-M0+
0x2 : CM23
Cortex-M23
0x3 : CM3
Cortex-M3
0x5 : CM4
Cortex-M4
0x6 : CM4F
Cortex-M4 with FPU
0x7 : CM33
Cortex-M33
End of enumeration elements list.
Configuration
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LQOS : Latency Quality Of Service
bits : 0 - 1 (2 bit)
DCCDMALEVEL : DMA Trigger Level
bits : 2 - 3 (2 bit)
Enumeration: DCCDMALEVELSelect
0 : EMPTY
Trigger rises when DCC is empty
1 : FULL
Trigger rises when DCC is full
End of enumeration elements list.
ETBRAMEN : Trace Control
bits : 4 - 4 (1 bit)
Device Configuration
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCFG : Device Configuration
bits : 0 - 31 (32 bit)
CoreSight ROM Table Memory Type
address_offset : 0x1FCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SMEMP : System Memory Present
bits : 0 - 0 (1 bit)
Peripheral Identification 4
address_offset : 0x1FD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JEPCC : JEP-106 Continuation Code
bits : 0 - 3 (4 bit)
FKBC : 4KB count
bits : 4 - 7 (4 bit)
Peripheral Identification 5
address_offset : 0x1FD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral Identification 6
address_offset : 0x1FD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral Identification 7
address_offset : 0x1FDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral Identification 0
address_offset : 0x1FE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PARTNBL : Part Number Low
bits : 0 - 7 (8 bit)
Peripheral Identification 1
address_offset : 0x1FE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PARTNBH : Part Number High
bits : 0 - 3 (4 bit)
JEPIDCL : Low part of the JEP-106 Identity Code
bits : 4 - 7 (4 bit)
Peripheral Identification 2
address_offset : 0x1FE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JEPIDCH : JEP-106 Identity Code High
bits : 0 - 2 (3 bit)
JEPU : JEP-106 Identity Code is used
bits : 3 - 3 (1 bit)
REVISION : Revision Number
bits : 4 - 7 (4 bit)
Peripheral Identification 3
address_offset : 0x1FEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CUSMOD : ARM CUSMOD
bits : 0 - 3 (4 bit)
REVAND : Revision Number
bits : 4 - 7 (4 bit)
Component Identification 0
address_offset : 0x1FF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PREAMBLEB0 : Preamble Byte 0
bits : 0 - 7 (8 bit)
Component Identification 1
address_offset : 0x1FF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PREAMBLE : Preamble
bits : 0 - 3 (4 bit)
CCLASS : Component Class
bits : 4 - 7 (4 bit)
Component Identification 2
address_offset : 0x1FF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PREAMBLEB2 : Preamble Byte 2
bits : 0 - 7 (8 bit)
Component Identification 3
address_offset : 0x1FFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PREAMBLEB3 : Preamble Byte 3
bits : 0 - 7 (8 bit)
Status B
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PROT : Protected
bits : 0 - 0 (1 bit)
DBGPRES : Debugger Present
bits : 1 - 1 (1 bit)
DCCD0 : Debug Communication Channel 0 Dirty
bits : 2 - 2 (1 bit)
DCCD1 : Debug Communication Channel 1 Dirty
bits : 3 - 3 (1 bit)
HPE : Hot-Plugging Enable
bits : 4 - 4 (1 bit)
CELCK : Chip Erase Locked
bits : 5 - 5 (1 bit)
TDCCD0 : Test Debug Communication Channel 0 Dirty
bits : 6 - 6 (1 bit)
TDCCD1 : Test Debug Communication Channel 1 Dirty
bits : 7 - 7 (1 bit)
Debug Communication Channel n
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data
bits : 0 - 31 (32 bit)
Device Configuration
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCFG : Device Configuration
bits : 0 - 31 (32 bit)
Debug Communication Channel n
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data
bits : 0 - 31 (32 bit)
Address
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AMOD : Access Mode
bits : 0 - 1 (2 bit)
ADDR : Address
bits : 2 - 31 (30 bit)
MBIST Control
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : MBIST Software Reset
bits : 0 - 0 (1 bit)
ENABLE : MBIST Enable
bits : 1 - 1 (1 bit)
MBIST Configuration
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALGO : MBIST Algorithm
bits : 0 - 4 (5 bit)
Enumeration: ALGOSelect
0x0 : MEMCLEAR
Memory Clear (1n)
0x1 : VERIFY
Memory Verify (1n)
0x2 : CLEARVER
Memory Clear and Verify (2n)
0x3 : ADDR_DEC
Address Decoder (2n)
0x4 : MARCH_LR
March LR (14n)
0x5 : MARCH_SR
March SR (14n)
0x6 : MARCH_SS
March SS (22n)
0x8 : CRC_UP
CRC increasing address (1n)
0x9 : CRC_DOWN
CRC decreasing address (1n)
End of enumeration elements list.
DEFRDMARGIN : Force Default Read Margin
bits : 6 - 6 (1 bit)
DBG : Enable Debug Mode
bits : 7 - 7 (1 bit)
MBIST Background Word
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : MBIST Background Word
bits : 0 - 31 (32 bit)
MBIST Global Status
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLDONE : MBIST Completed
bits : 0 - 0 (1 bit)
FAILED : MBIST Failed
bits : 1 - 1 (1 bit)
ERRINFO : MBIST Error Info Present
bits : 2 - 2 (1 bit)
CONFIGURED : MBIST Configuration Sent
bits : 3 - 3 (1 bit)
MBIST Fail Data
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Error Data Read
bits : 0 - 31 (32 bit)
MBIST Expected Data
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Expected Data
bits : 0 - 31 (32 bit)
MBIST Fail Address
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : Error Address
bits : 0 - 13 (14 bit)
MBIST Fail Context
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBSTEP : Algorithm Sub-step
bits : 0 - 4 (5 bit)
Enumeration: SUBSTEPSelect
0x1 : R0_1
0x3 : R1_1
0x5 : R0_2
0x7 : R1_2
0x9 : R0_3
0xb : R1_3
End of enumeration elements list.
STEP : Algorithm Step
bits : 5 - 9 (5 bit)
Enumeration: STEPSelect
0x2 : DOWN_R0W1
0x3 : UP_R1W0R0W1
0x4 : UP_R1W0
0x5 : UP_R0W1R1W0
0x6 : UP_R0
0x7 : UP_R0R0W0R0W1
0x8 : UP_R1R1W1R1W0
0x9 : DOWN_R0R0W0R0W1
0xa : DOWN_R1R1W1R1W0
0xc : UP_R0R0
0xe : DOWN_R1W0R0W1
0xf : DOWN_R1R1
End of enumeration elements list.
PORT : DPRAM Port Index
bits : 10 - 10 (1 bit)
MBIST Memory Enable 0
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE0 : Memory 0 MBIST Enable
bits : 0 - 0 (1 bit)
ENABLE1 : Memory 1 MBIST Enable
bits : 1 - 1 (1 bit)
ENABLE2 : Memory 2 MBIST Enable
bits : 2 - 2 (1 bit)
ENABLE3 : Memory 3 MBIST Enable
bits : 3 - 3 (1 bit)
ENABLE4 : Memory 4 MBIST Enable
bits : 4 - 4 (1 bit)
ENABLE5 : Memory 5 MBIST Enable
bits : 5 - 5 (1 bit)
ENABLE6 : Memory 6 MBIST Enable
bits : 6 - 6 (1 bit)
ENABLE7 : Memory 7 MBIST Enable
bits : 7 - 7 (1 bit)
ENABLE8 : Memory 8 MBIST Enable
bits : 8 - 8 (1 bit)
ENABLE9 : Memory 9 MBIST Enable
bits : 9 - 9 (1 bit)
ENABLE10 : Memory 10 MBIST Enable
bits : 10 - 10 (1 bit)
ENABLE11 : Memory 11 MBIST Enable
bits : 11 - 11 (1 bit)
ENABLE12 : Memory 12 MBIST Enable
bits : 12 - 12 (1 bit)
ENABLE13 : Memory 13 MBIST Enable
bits : 13 - 13 (1 bit)
ENABLE14 : Memory 14 MBIST Enable
bits : 14 - 14 (1 bit)
ENABLE15 : Memory 15 MBIST Enable
bits : 15 - 15 (1 bit)
ENABLE16 : Memory 16 MBIST Enable
bits : 16 - 16 (1 bit)
ENABLE17 : Memory 17 MBIST Enable
bits : 17 - 17 (1 bit)
ENABLE18 : Memory 18 MBIST Enable
bits : 18 - 18 (1 bit)
ENABLE19 : Memory 19 MBIST Enable
bits : 19 - 19 (1 bit)
ENABLE20 : Memory 20 MBIST Enable
bits : 20 - 20 (1 bit)
ENABLE21 : Memory 21 MBIST Enable
bits : 21 - 21 (1 bit)
ENABLE22 : Memory 22 MBIST Enable
bits : 22 - 22 (1 bit)
ENABLE23 : Memory 23 MBIST Enable
bits : 23 - 23 (1 bit)
ENABLE24 : Memory 24 MBIST Enable
bits : 24 - 24 (1 bit)
ENABLE25 : Memory 25 MBIST Enable
bits : 25 - 25 (1 bit)
ENABLE26 : Memory 26 MBIST Enable
bits : 26 - 26 (1 bit)
ENABLE27 : Memory 27 MBIST Enable
bits : 27 - 27 (1 bit)
ENABLE28 : Memory 28 MBIST Enable
bits : 28 - 28 (1 bit)
MBIST Memory Busy 0
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSY0 : Memory 0 BIST Busy
bits : 0 - 0 (1 bit)
BUSY1 : Memory 1 BIST Busy
bits : 1 - 1 (1 bit)
BUSY2 : Memory 2 BIST Busy
bits : 2 - 2 (1 bit)
BUSY3 : Memory 3 BIST Busy
bits : 3 - 3 (1 bit)
BUSY4 : Memory 4 BIST Busy
bits : 4 - 4 (1 bit)
BUSY5 : Memory 5 BIST Busy
bits : 5 - 5 (1 bit)
BUSY6 : Memory 6 BIST Busy
bits : 6 - 6 (1 bit)
BUSY7 : Memory 7 BIST Busy
bits : 7 - 7 (1 bit)
BUSY8 : Memory 8 BIST Busy
bits : 8 - 8 (1 bit)
BUSY9 : Memory 9 BIST Busy
bits : 9 - 9 (1 bit)
BUSY10 : Memory 10 BIST Busy
bits : 10 - 10 (1 bit)
BUSY11 : Memory 11 BIST Busy
bits : 11 - 11 (1 bit)
BUSY12 : Memory 12 BIST Busy
bits : 12 - 12 (1 bit)
BUSY13 : Memory 13 BIST Busy
bits : 13 - 13 (1 bit)
BUSY14 : Memory 14 BIST Busy
bits : 14 - 14 (1 bit)
BUSY15 : Memory 15 BIST Busy
bits : 15 - 15 (1 bit)
BUSY16 : Memory 16 BIST Busy
bits : 16 - 16 (1 bit)
BUSY17 : Memory 17 BIST Busy
bits : 17 - 17 (1 bit)
BUSY18 : Memory 18 BIST Busy
bits : 18 - 18 (1 bit)
BUSY19 : Memory 19 BIST Busy
bits : 19 - 19 (1 bit)
BUSY20 : Memory 20 BIST Busy
bits : 20 - 20 (1 bit)
BUSY21 : Memory 21 BIST Busy
bits : 21 - 21 (1 bit)
BUSY22 : Memory 22 BIST Busy
bits : 22 - 22 (1 bit)
BUSY23 : Memory 23 BIST Busy
bits : 23 - 23 (1 bit)
BUSY24 : Memory 24 BIST Busy
bits : 24 - 24 (1 bit)
BUSY25 : Memory 25 BIST Busy
bits : 25 - 25 (1 bit)
BUSY26 : Memory 26 BIST Busy
bits : 26 - 26 (1 bit)
BUSY27 : Memory 27 BIST Busy
bits : 27 - 27 (1 bit)
BUSY28 : Memory 28 BIST Busy
bits : 28 - 28 (1 bit)
MBIST Memory Status 0
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATUS0 : Memory 0 MBIST Status
bits : 0 - 0 (1 bit)
STATUS1 : Memory 1 MBIST Status
bits : 1 - 1 (1 bit)
STATUS2 : Memory 2 MBIST Status
bits : 2 - 2 (1 bit)
STATUS3 : Memory 3 MBIST Status
bits : 3 - 3 (1 bit)
STATUS4 : Memory 4 MBIST Status
bits : 4 - 4 (1 bit)
STATUS5 : Memory 5 MBIST Status
bits : 5 - 5 (1 bit)
STATUS6 : Memory 6 MBIST Status
bits : 6 - 6 (1 bit)
STATUS7 : Memory 7 MBIST Status
bits : 7 - 7 (1 bit)
STATUS8 : Memory 8 MBIST Status
bits : 8 - 8 (1 bit)
STATUS9 : Memory 9 MBIST Status
bits : 9 - 9 (1 bit)
STATUS10 : Memory 10 MBIST Status
bits : 10 - 10 (1 bit)
STATUS11 : Memory 11 MBIST Status
bits : 11 - 11 (1 bit)
STATUS12 : Memory 12 MBIST Status
bits : 12 - 12 (1 bit)
STATUS13 : Memory 13 MBIST Status
bits : 13 - 13 (1 bit)
STATUS14 : Memory 14 MBIST Status
bits : 14 - 14 (1 bit)
STATUS15 : Memory 15 MBIST Status
bits : 15 - 15 (1 bit)
STATUS16 : Memory 16 MBIST Status
bits : 16 - 16 (1 bit)
STATUS17 : Memory 17 MBIST Status
bits : 17 - 17 (1 bit)
STATUS18 : Memory 18 MBIST Status
bits : 18 - 18 (1 bit)
STATUS19 : Memory 19 MBIST Status
bits : 19 - 19 (1 bit)
STATUS20 : Memory 20 MBIST Status
bits : 20 - 20 (1 bit)
STATUS21 : Memory 21 MBIST Status
bits : 21 - 21 (1 bit)
STATUS22 : Memory 22 MBIST Status
bits : 22 - 22 (1 bit)
STATUS23 : Memory 23 MBIST Status
bits : 23 - 23 (1 bit)
STATUS24 : Memory 24 MBIST Status
bits : 24 - 24 (1 bit)
STATUS25 : Memory 25 MBIST Status
bits : 25 - 25 (1 bit)
STATUS26 : Memory 26 MBIST Status
bits : 26 - 26 (1 bit)
STATUS27 : Memory 27 MBIST Status
bits : 27 - 27 (1 bit)
STATUS28 : Memory 28 MBIST Status
bits : 28 - 28 (1 bit)
Length
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LENGTH : Length
bits : 2 - 31 (30 bit)
Data
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data
bits : 0 - 31 (32 bit)
Device Configuration
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCFG : Device Configuration
bits : 0 - 31 (32 bit)
Device Configuration
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCFG : Device Configuration
bits : 0 - 31 (32 bit)
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