\n

DSU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

STATUSA

DCC0

ENTRY0

ENTRY1

END

DCC1

DID

CFG

DCFG[0]

MEMTYPE

PID4

PID5

PID6

PID7

PID0

PID1

PID2

PID3

CID0

CID1

CID2

CID3

STATUSB

DCC[0]

DCFG[1]

DCC[1]

ADDR

MBCTRL

MBCONFIG

MBWORD

MBGSTAT

MBDFAIL

MBDEXP

MBAFAIL

MBCONTEXT

MBENABLE0

MBBUSY0

MBSTATUS0

LENGTH

DATA

DCFG0

DCFG1


CTRL

Control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SWRST CRC MBIST CE ARR SMSA

SWRST : Software Reset
bits : 0 - 0 (1 bit)

CRC : 32-bit Cyclic Redundancy Code
bits : 2 - 2 (1 bit)

MBIST : Memory built-in self-test
bits : 3 - 3 (1 bit)

CE : Chip-Erase
bits : 4 - 4 (1 bit)

ARR : Auxiliary Row Read
bits : 6 - 6 (1 bit)

SMSA : Start Memory Stream Access
bits : 7 - 7 (1 bit)


STATUSA

Status A
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUSA STATUSA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DONE CRSTEXT BERR FAIL PERR

DONE : Done
bits : 0 - 0 (1 bit)

CRSTEXT : CPU Reset Phase Extension
bits : 1 - 1 (1 bit)

BERR : Bus Error
bits : 2 - 2 (1 bit)

FAIL : Failure
bits : 3 - 3 (1 bit)

PERR : Protection Error
bits : 4 - 4 (1 bit)


DCC0

Debug Communication Channel n
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCC0 DCC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data
bits : 0 - 31 (32 bit)


ENTRY0

CoreSight ROM Table Entry 0
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENTRY0 ENTRY0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPRES FMT ADDOFF

EPRES : Entry Present
bits : 0 - 0 (1 bit)

FMT : Format
bits : 1 - 1 (1 bit)

ADDOFF : Address Offset
bits : 12 - 31 (20 bit)


ENTRY1

CoreSight ROM Table Entry 1
address_offset : 0x1004 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENTRY1 ENTRY1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

END

CoreSight ROM Table End
address_offset : 0x1008 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

END END read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 END

END : End Marker
bits : 0 - 31 (32 bit)


DCC1

Debug Communication Channel n
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCC1 DCC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data
bits : 0 - 31 (32 bit)


DID

Device Identification
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DID DID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEVSEL REVISION DIE SERIES FAMILY PROCESSOR

DEVSEL : Device Select
bits : 0 - 7 (8 bit)

REVISION : Revision Number
bits : 8 - 11 (4 bit)

DIE : Die Number
bits : 12 - 15 (4 bit)

SERIES : Series
bits : 16 - 21 (6 bit)

Enumeration: SERIESSelect

0 : 0

Cortex-M0+ processor, basic feature set

1 : 1

Cortex-M0+ processor, USB

End of enumeration elements list.

FAMILY : Family
bits : 23 - 27 (5 bit)

Enumeration: FAMILYSelect

0 : 0

General purpose microcontroller

1 : 1

PicoPower

End of enumeration elements list.

PROCESSOR : Processor
bits : 28 - 31 (4 bit)

Enumeration: PROCESSORSelect

0x1 : CM0P

Cortex-M0+

0x2 : CM23

Cortex-M23

0x3 : CM3

Cortex-M3

0x5 : CM4

Cortex-M4

0x6 : CM4F

Cortex-M4 with FPU

0x7 : CM33

Cortex-M33

End of enumeration elements list.


CFG

Configuration
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LQOS DCCDMALEVEL ETBRAMEN

LQOS : Latency Quality Of Service
bits : 0 - 1 (2 bit)

DCCDMALEVEL : DMA Trigger Level
bits : 2 - 3 (2 bit)

Enumeration: DCCDMALEVELSelect

0 : EMPTY

Trigger rises when DCC is empty

1 : FULL

Trigger rises when DCC is full

End of enumeration elements list.

ETBRAMEN : Trace Control
bits : 4 - 4 (1 bit)


DCFG[0]

Device Configuration
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCFG[0] DCFG[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCFG

DCFG : Device Configuration
bits : 0 - 31 (32 bit)


MEMTYPE

CoreSight ROM Table Memory Type
address_offset : 0x1FCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MEMTYPE MEMTYPE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMEMP

SMEMP : System Memory Present
bits : 0 - 0 (1 bit)


PID4

Peripheral Identification 4
address_offset : 0x1FD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID4 PID4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEPCC FKBC

JEPCC : JEP-106 Continuation Code
bits : 0 - 3 (4 bit)

FKBC : 4KB count
bits : 4 - 7 (4 bit)


PID5

Peripheral Identification 5
address_offset : 0x1FD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID5 PID5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PID6

Peripheral Identification 6
address_offset : 0x1FD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID6 PID6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PID7

Peripheral Identification 7
address_offset : 0x1FDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID7 PID7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PID0

Peripheral Identification 0
address_offset : 0x1FE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID0 PID0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARTNBL

PARTNBL : Part Number Low
bits : 0 - 7 (8 bit)


PID1

Peripheral Identification 1
address_offset : 0x1FE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID1 PID1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARTNBH JEPIDCL

PARTNBH : Part Number High
bits : 0 - 3 (4 bit)

JEPIDCL : Low part of the JEP-106 Identity Code
bits : 4 - 7 (4 bit)


PID2

Peripheral Identification 2
address_offset : 0x1FE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID2 PID2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEPIDCH JEPU REVISION

JEPIDCH : JEP-106 Identity Code High
bits : 0 - 2 (3 bit)

JEPU : JEP-106 Identity Code is used
bits : 3 - 3 (1 bit)

REVISION : Revision Number
bits : 4 - 7 (4 bit)


PID3

Peripheral Identification 3
address_offset : 0x1FEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID3 PID3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CUSMOD REVAND

CUSMOD : ARM CUSMOD
bits : 0 - 3 (4 bit)

REVAND : Revision Number
bits : 4 - 7 (4 bit)


CID0

Component Identification 0
address_offset : 0x1FF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CID0 CID0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMBLEB0

PREAMBLEB0 : Preamble Byte 0
bits : 0 - 7 (8 bit)


CID1

Component Identification 1
address_offset : 0x1FF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CID1 CID1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMBLE CCLASS

PREAMBLE : Preamble
bits : 0 - 3 (4 bit)

CCLASS : Component Class
bits : 4 - 7 (4 bit)


CID2

Component Identification 2
address_offset : 0x1FF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CID2 CID2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMBLEB2

PREAMBLEB2 : Preamble Byte 2
bits : 0 - 7 (8 bit)


CID3

Component Identification 3
address_offset : 0x1FFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CID3 CID3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMBLEB3

PREAMBLEB3 : Preamble Byte 3
bits : 0 - 7 (8 bit)


STATUSB

Status B
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUSB STATUSB read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PROT DBGPRES DCCD0 DCCD1 HPE CELCK TDCCD0 TDCCD1

PROT : Protected
bits : 0 - 0 (1 bit)

DBGPRES : Debugger Present
bits : 1 - 1 (1 bit)

DCCD0 : Debug Communication Channel 0 Dirty
bits : 2 - 2 (1 bit)

DCCD1 : Debug Communication Channel 1 Dirty
bits : 3 - 3 (1 bit)

HPE : Hot-Plugging Enable
bits : 4 - 4 (1 bit)

CELCK : Chip Erase Locked
bits : 5 - 5 (1 bit)

TDCCD0 : Test Debug Communication Channel 0 Dirty
bits : 6 - 6 (1 bit)

TDCCD1 : Test Debug Communication Channel 1 Dirty
bits : 7 - 7 (1 bit)


DCC[0]

Debug Communication Channel n
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCC[0] DCC[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data
bits : 0 - 31 (32 bit)


DCFG[1]

Device Configuration
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCFG[1] DCFG[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCFG

DCFG : Device Configuration
bits : 0 - 31 (32 bit)


DCC[1]

Debug Communication Channel n
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCC[1] DCC[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data
bits : 0 - 31 (32 bit)


ADDR

Address
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMOD ADDR

AMOD : Access Mode
bits : 0 - 1 (2 bit)

ADDR : Address
bits : 2 - 31 (30 bit)


MBCTRL

MBIST Control
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MBCTRL MBCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE

SWRST : MBIST Software Reset
bits : 0 - 0 (1 bit)

ENABLE : MBIST Enable
bits : 1 - 1 (1 bit)


MBCONFIG

MBIST Configuration
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MBCONFIG MBCONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALGO DEFRDMARGIN DBG

ALGO : MBIST Algorithm
bits : 0 - 4 (5 bit)

Enumeration: ALGOSelect

0x0 : MEMCLEAR

Memory Clear (1n)

0x1 : VERIFY

Memory Verify (1n)

0x2 : CLEARVER

Memory Clear and Verify (2n)

0x3 : ADDR_DEC

Address Decoder (2n)

0x4 : MARCH_LR

March LR (14n)

0x5 : MARCH_SR

March SR (14n)

0x6 : MARCH_SS

March SS (22n)

0x8 : CRC_UP

CRC increasing address (1n)

0x9 : CRC_DOWN

CRC decreasing address (1n)

End of enumeration elements list.

DEFRDMARGIN : Force Default Read Margin
bits : 6 - 6 (1 bit)

DBG : Enable Debug Mode
bits : 7 - 7 (1 bit)


MBWORD

MBIST Background Word
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MBWORD MBWORD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : MBIST Background Word
bits : 0 - 31 (32 bit)


MBGSTAT

MBIST Global Status
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MBGSTAT MBGSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALLDONE FAILED ERRINFO CONFIGURED

ALLDONE : MBIST Completed
bits : 0 - 0 (1 bit)

FAILED : MBIST Failed
bits : 1 - 1 (1 bit)

ERRINFO : MBIST Error Info Present
bits : 2 - 2 (1 bit)

CONFIGURED : MBIST Configuration Sent
bits : 3 - 3 (1 bit)


MBDFAIL

MBIST Fail Data
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MBDFAIL MBDFAIL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Error Data Read
bits : 0 - 31 (32 bit)


MBDEXP

MBIST Expected Data
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MBDEXP MBDEXP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Expected Data
bits : 0 - 31 (32 bit)


MBAFAIL

MBIST Fail Address
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MBAFAIL MBAFAIL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Error Address
bits : 0 - 13 (14 bit)


MBCONTEXT

MBIST Fail Context
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MBCONTEXT MBCONTEXT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBSTEP STEP PORT

SUBSTEP : Algorithm Sub-step
bits : 0 - 4 (5 bit)

Enumeration: SUBSTEPSelect

0x1 : R0_1


0x3 : R1_1


0x5 : R0_2


0x7 : R1_2


0x9 : R0_3


0xb : R1_3


End of enumeration elements list.

STEP : Algorithm Step
bits : 5 - 9 (5 bit)

Enumeration: STEPSelect

0x2 : DOWN_R0W1


0x3 : UP_R1W0R0W1


0x4 : UP_R1W0


0x5 : UP_R0W1R1W0


0x6 : UP_R0


0x7 : UP_R0R0W0R0W1


0x8 : UP_R1R1W1R1W0


0x9 : DOWN_R0R0W0R0W1


0xa : DOWN_R1R1W1R1W0


0xc : UP_R0R0


0xe : DOWN_R1W0R0W1


0xf : DOWN_R1R1


End of enumeration elements list.

PORT : DPRAM Port Index
bits : 10 - 10 (1 bit)


MBENABLE0

MBIST Memory Enable 0
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MBENABLE0 MBENABLE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE0 ENABLE1 ENABLE2 ENABLE3 ENABLE4 ENABLE5 ENABLE6 ENABLE7 ENABLE8 ENABLE9 ENABLE10 ENABLE11 ENABLE12 ENABLE13 ENABLE14 ENABLE15 ENABLE16 ENABLE17 ENABLE18 ENABLE19 ENABLE20 ENABLE21 ENABLE22 ENABLE23 ENABLE24 ENABLE25 ENABLE26 ENABLE27 ENABLE28

ENABLE0 : Memory 0 MBIST Enable
bits : 0 - 0 (1 bit)

ENABLE1 : Memory 1 MBIST Enable
bits : 1 - 1 (1 bit)

ENABLE2 : Memory 2 MBIST Enable
bits : 2 - 2 (1 bit)

ENABLE3 : Memory 3 MBIST Enable
bits : 3 - 3 (1 bit)

ENABLE4 : Memory 4 MBIST Enable
bits : 4 - 4 (1 bit)

ENABLE5 : Memory 5 MBIST Enable
bits : 5 - 5 (1 bit)

ENABLE6 : Memory 6 MBIST Enable
bits : 6 - 6 (1 bit)

ENABLE7 : Memory 7 MBIST Enable
bits : 7 - 7 (1 bit)

ENABLE8 : Memory 8 MBIST Enable
bits : 8 - 8 (1 bit)

ENABLE9 : Memory 9 MBIST Enable
bits : 9 - 9 (1 bit)

ENABLE10 : Memory 10 MBIST Enable
bits : 10 - 10 (1 bit)

ENABLE11 : Memory 11 MBIST Enable
bits : 11 - 11 (1 bit)

ENABLE12 : Memory 12 MBIST Enable
bits : 12 - 12 (1 bit)

ENABLE13 : Memory 13 MBIST Enable
bits : 13 - 13 (1 bit)

ENABLE14 : Memory 14 MBIST Enable
bits : 14 - 14 (1 bit)

ENABLE15 : Memory 15 MBIST Enable
bits : 15 - 15 (1 bit)

ENABLE16 : Memory 16 MBIST Enable
bits : 16 - 16 (1 bit)

ENABLE17 : Memory 17 MBIST Enable
bits : 17 - 17 (1 bit)

ENABLE18 : Memory 18 MBIST Enable
bits : 18 - 18 (1 bit)

ENABLE19 : Memory 19 MBIST Enable
bits : 19 - 19 (1 bit)

ENABLE20 : Memory 20 MBIST Enable
bits : 20 - 20 (1 bit)

ENABLE21 : Memory 21 MBIST Enable
bits : 21 - 21 (1 bit)

ENABLE22 : Memory 22 MBIST Enable
bits : 22 - 22 (1 bit)

ENABLE23 : Memory 23 MBIST Enable
bits : 23 - 23 (1 bit)

ENABLE24 : Memory 24 MBIST Enable
bits : 24 - 24 (1 bit)

ENABLE25 : Memory 25 MBIST Enable
bits : 25 - 25 (1 bit)

ENABLE26 : Memory 26 MBIST Enable
bits : 26 - 26 (1 bit)

ENABLE27 : Memory 27 MBIST Enable
bits : 27 - 27 (1 bit)

ENABLE28 : Memory 28 MBIST Enable
bits : 28 - 28 (1 bit)


MBBUSY0

MBIST Memory Busy 0
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MBBUSY0 MBBUSY0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSY0 BUSY1 BUSY2 BUSY3 BUSY4 BUSY5 BUSY6 BUSY7 BUSY8 BUSY9 BUSY10 BUSY11 BUSY12 BUSY13 BUSY14 BUSY15 BUSY16 BUSY17 BUSY18 BUSY19 BUSY20 BUSY21 BUSY22 BUSY23 BUSY24 BUSY25 BUSY26 BUSY27 BUSY28

BUSY0 : Memory 0 BIST Busy
bits : 0 - 0 (1 bit)

BUSY1 : Memory 1 BIST Busy
bits : 1 - 1 (1 bit)

BUSY2 : Memory 2 BIST Busy
bits : 2 - 2 (1 bit)

BUSY3 : Memory 3 BIST Busy
bits : 3 - 3 (1 bit)

BUSY4 : Memory 4 BIST Busy
bits : 4 - 4 (1 bit)

BUSY5 : Memory 5 BIST Busy
bits : 5 - 5 (1 bit)

BUSY6 : Memory 6 BIST Busy
bits : 6 - 6 (1 bit)

BUSY7 : Memory 7 BIST Busy
bits : 7 - 7 (1 bit)

BUSY8 : Memory 8 BIST Busy
bits : 8 - 8 (1 bit)

BUSY9 : Memory 9 BIST Busy
bits : 9 - 9 (1 bit)

BUSY10 : Memory 10 BIST Busy
bits : 10 - 10 (1 bit)

BUSY11 : Memory 11 BIST Busy
bits : 11 - 11 (1 bit)

BUSY12 : Memory 12 BIST Busy
bits : 12 - 12 (1 bit)

BUSY13 : Memory 13 BIST Busy
bits : 13 - 13 (1 bit)

BUSY14 : Memory 14 BIST Busy
bits : 14 - 14 (1 bit)

BUSY15 : Memory 15 BIST Busy
bits : 15 - 15 (1 bit)

BUSY16 : Memory 16 BIST Busy
bits : 16 - 16 (1 bit)

BUSY17 : Memory 17 BIST Busy
bits : 17 - 17 (1 bit)

BUSY18 : Memory 18 BIST Busy
bits : 18 - 18 (1 bit)

BUSY19 : Memory 19 BIST Busy
bits : 19 - 19 (1 bit)

BUSY20 : Memory 20 BIST Busy
bits : 20 - 20 (1 bit)

BUSY21 : Memory 21 BIST Busy
bits : 21 - 21 (1 bit)

BUSY22 : Memory 22 BIST Busy
bits : 22 - 22 (1 bit)

BUSY23 : Memory 23 BIST Busy
bits : 23 - 23 (1 bit)

BUSY24 : Memory 24 BIST Busy
bits : 24 - 24 (1 bit)

BUSY25 : Memory 25 BIST Busy
bits : 25 - 25 (1 bit)

BUSY26 : Memory 26 BIST Busy
bits : 26 - 26 (1 bit)

BUSY27 : Memory 27 BIST Busy
bits : 27 - 27 (1 bit)

BUSY28 : Memory 28 BIST Busy
bits : 28 - 28 (1 bit)


MBSTATUS0

MBIST Memory Status 0
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MBSTATUS0 MBSTATUS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATUS0 STATUS1 STATUS2 STATUS3 STATUS4 STATUS5 STATUS6 STATUS7 STATUS8 STATUS9 STATUS10 STATUS11 STATUS12 STATUS13 STATUS14 STATUS15 STATUS16 STATUS17 STATUS18 STATUS19 STATUS20 STATUS21 STATUS22 STATUS23 STATUS24 STATUS25 STATUS26 STATUS27 STATUS28

STATUS0 : Memory 0 MBIST Status
bits : 0 - 0 (1 bit)

STATUS1 : Memory 1 MBIST Status
bits : 1 - 1 (1 bit)

STATUS2 : Memory 2 MBIST Status
bits : 2 - 2 (1 bit)

STATUS3 : Memory 3 MBIST Status
bits : 3 - 3 (1 bit)

STATUS4 : Memory 4 MBIST Status
bits : 4 - 4 (1 bit)

STATUS5 : Memory 5 MBIST Status
bits : 5 - 5 (1 bit)

STATUS6 : Memory 6 MBIST Status
bits : 6 - 6 (1 bit)

STATUS7 : Memory 7 MBIST Status
bits : 7 - 7 (1 bit)

STATUS8 : Memory 8 MBIST Status
bits : 8 - 8 (1 bit)

STATUS9 : Memory 9 MBIST Status
bits : 9 - 9 (1 bit)

STATUS10 : Memory 10 MBIST Status
bits : 10 - 10 (1 bit)

STATUS11 : Memory 11 MBIST Status
bits : 11 - 11 (1 bit)

STATUS12 : Memory 12 MBIST Status
bits : 12 - 12 (1 bit)

STATUS13 : Memory 13 MBIST Status
bits : 13 - 13 (1 bit)

STATUS14 : Memory 14 MBIST Status
bits : 14 - 14 (1 bit)

STATUS15 : Memory 15 MBIST Status
bits : 15 - 15 (1 bit)

STATUS16 : Memory 16 MBIST Status
bits : 16 - 16 (1 bit)

STATUS17 : Memory 17 MBIST Status
bits : 17 - 17 (1 bit)

STATUS18 : Memory 18 MBIST Status
bits : 18 - 18 (1 bit)

STATUS19 : Memory 19 MBIST Status
bits : 19 - 19 (1 bit)

STATUS20 : Memory 20 MBIST Status
bits : 20 - 20 (1 bit)

STATUS21 : Memory 21 MBIST Status
bits : 21 - 21 (1 bit)

STATUS22 : Memory 22 MBIST Status
bits : 22 - 22 (1 bit)

STATUS23 : Memory 23 MBIST Status
bits : 23 - 23 (1 bit)

STATUS24 : Memory 24 MBIST Status
bits : 24 - 24 (1 bit)

STATUS25 : Memory 25 MBIST Status
bits : 25 - 25 (1 bit)

STATUS26 : Memory 26 MBIST Status
bits : 26 - 26 (1 bit)

STATUS27 : Memory 27 MBIST Status
bits : 27 - 27 (1 bit)

STATUS28 : Memory 28 MBIST Status
bits : 28 - 28 (1 bit)


LENGTH

Length
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LENGTH LENGTH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH

LENGTH : Length
bits : 2 - 31 (30 bit)


DATA

Data
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data
bits : 0 - 31 (32 bit)


DCFG0

Device Configuration
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCFG0 DCFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCFG

DCFG : Device Configuration
bits : 0 - 31 (32 bit)


DCFG1

Device Configuration
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCFG1 DCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCFG

DCFG : Device Configuration
bits : 0 - 31 (32 bit)



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