\n
address_offset : 0x0 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection :
Control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : write-only
GCLKREQ : Generic Clock Requests
bits : 4 - 4 (1 bit)
Interrupt Enable Clear
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR0 : Channel 0 Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
OVR1 : Channel 1 Overrun Interrupt Enable
bits : 1 - 1 (1 bit)
OVR2 : Channel 2 Overrun Interrupt Enable
bits : 2 - 2 (1 bit)
OVR3 : Channel 3 Overrun Interrupt Enable
bits : 3 - 3 (1 bit)
OVR4 : Channel 4 Overrun Interrupt Enable
bits : 4 - 4 (1 bit)
OVR5 : Channel 5 Overrun Interrupt Enable
bits : 5 - 5 (1 bit)
OVR6 : Channel 6 Overrun Interrupt Enable
bits : 6 - 6 (1 bit)
OVR7 : Channel 7 Overrun Interrupt Enable
bits : 7 - 7 (1 bit)
EVD0 : Channel 0 Event Detection Interrupt Enable
bits : 8 - 8 (1 bit)
EVD1 : Channel 1 Event Detection Interrupt Enable
bits : 9 - 9 (1 bit)
EVD2 : Channel 2 Event Detection Interrupt Enable
bits : 10 - 10 (1 bit)
EVD3 : Channel 3 Event Detection Interrupt Enable
bits : 11 - 11 (1 bit)
EVD4 : Channel 4 Event Detection Interrupt Enable
bits : 12 - 12 (1 bit)
EVD5 : Channel 5 Event Detection Interrupt Enable
bits : 13 - 13 (1 bit)
EVD6 : Channel 6 Event Detection Interrupt Enable
bits : 14 - 14 (1 bit)
EVD7 : Channel 7 Event Detection Interrupt Enable
bits : 15 - 15 (1 bit)
Interrupt Enable Set
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR0 : Channel 0 Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
OVR1 : Channel 1 Overrun Interrupt Enable
bits : 1 - 1 (1 bit)
OVR2 : Channel 2 Overrun Interrupt Enable
bits : 2 - 2 (1 bit)
OVR3 : Channel 3 Overrun Interrupt Enable
bits : 3 - 3 (1 bit)
OVR4 : Channel 4 Overrun Interrupt Enable
bits : 4 - 4 (1 bit)
OVR5 : Channel 5 Overrun Interrupt Enable
bits : 5 - 5 (1 bit)
OVR6 : Channel 6 Overrun Interrupt Enable
bits : 6 - 6 (1 bit)
OVR7 : Channel 7 Overrun Interrupt Enable
bits : 7 - 7 (1 bit)
EVD0 : Channel 0 Event Detection Interrupt Enable
bits : 8 - 8 (1 bit)
EVD1 : Channel 1 Event Detection Interrupt Enable
bits : 9 - 9 (1 bit)
EVD2 : Channel 2 Event Detection Interrupt Enable
bits : 10 - 10 (1 bit)
EVD3 : Channel 3 Event Detection Interrupt Enable
bits : 11 - 11 (1 bit)
EVD4 : Channel 4 Event Detection Interrupt Enable
bits : 12 - 12 (1 bit)
EVD5 : Channel 5 Event Detection Interrupt Enable
bits : 13 - 13 (1 bit)
EVD6 : Channel 6 Event Detection Interrupt Enable
bits : 14 - 14 (1 bit)
EVD7 : Channel 7 Event Detection Interrupt Enable
bits : 15 - 15 (1 bit)
Interrupt Flag Status and Clear
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR0 : Channel 0 Overrun
bits : 0 - 0 (1 bit)
OVR1 : Channel 1 Overrun
bits : 1 - 1 (1 bit)
OVR2 : Channel 2 Overrun
bits : 2 - 2 (1 bit)
OVR3 : Channel 3 Overrun
bits : 3 - 3 (1 bit)
OVR4 : Channel 4 Overrun
bits : 4 - 4 (1 bit)
OVR5 : Channel 5 Overrun
bits : 5 - 5 (1 bit)
OVR6 : Channel 6 Overrun
bits : 6 - 6 (1 bit)
OVR7 : Channel 7 Overrun
bits : 7 - 7 (1 bit)
EVD0 : Channel 0 Event Detection
bits : 8 - 8 (1 bit)
EVD1 : Channel 1 Event Detection
bits : 9 - 9 (1 bit)
EVD2 : Channel 2 Event Detection
bits : 10 - 10 (1 bit)
EVD3 : Channel 3 Event Detection
bits : 11 - 11 (1 bit)
EVD4 : Channel 4 Event Detection
bits : 12 - 12 (1 bit)
EVD5 : Channel 5 Event Detection
bits : 13 - 13 (1 bit)
EVD6 : Channel 6 Event Detection
bits : 14 - 14 (1 bit)
EVD7 : Channel 7 Event Detection
bits : 15 - 15 (1 bit)
Channel
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Selection
bits : 0 - 2 (3 bit)
SWEVT : Software Event
bits : 8 - 8 (1 bit)
EVGEN : Event Generator Selection
bits : 16 - 21 (6 bit)
PATH : Path Selection
bits : 24 - 25 (2 bit)
Enumeration: PATHSelect
0x0 : SYNCHRONOUS
Synchronous path
0x1 : RESYNCHRONIZED
Resynchronized path
0x2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 26 - 27 (2 bit)
Enumeration: EDGSELSelect
0x0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
0x1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
0x2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
0x3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
User Multiplexer
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USER : User Multiplexer Selection
bits : 0 - 3 (4 bit)
CHANNEL : Channel Event Selection
bits : 8 - 11 (4 bit)
Enumeration: CHANNELSelect
0x0 : 0
No Channel Output Selected
End of enumeration elements list.
Channel Status
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
USRRDY0 : Channel 0 User Ready
bits : 0 - 0 (1 bit)
access : read-only
USRRDY1 : Channel 1 User Ready
bits : 1 - 1 (1 bit)
access : read-only
USRRDY2 : Channel 2 User Ready
bits : 2 - 2 (1 bit)
access : read-only
USRRDY3 : Channel 3 User Ready
bits : 3 - 3 (1 bit)
access : read-only
USRRDY4 : Channel 4 User Ready
bits : 4 - 4 (1 bit)
access : read-only
USRRDY5 : Channel 5 User Ready
bits : 5 - 5 (1 bit)
access : read-only
USRRDY6 : Channel 6 User Ready
bits : 6 - 6 (1 bit)
access : read-only
USRRDY7 : Channel 7 User Ready
bits : 7 - 7 (1 bit)
access : read-only
CHBUSY0 : Channel 0 Busy
bits : 8 - 8 (1 bit)
access : read-only
CHBUSY1 : Channel 1 Busy
bits : 9 - 9 (1 bit)
access : read-only
CHBUSY2 : Channel 2 Busy
bits : 10 - 10 (1 bit)
access : read-only
CHBUSY3 : Channel 3 Busy
bits : 11 - 11 (1 bit)
access : read-only
CHBUSY4 : Channel 4 Busy
bits : 12 - 12 (1 bit)
access : read-only
CHBUSY5 : Channel 5 Busy
bits : 13 - 13 (1 bit)
access : read-only
CHBUSY6 : Channel 6 Busy
bits : 14 - 14 (1 bit)
access : read-only
CHBUSY7 : Channel 7 Busy
bits : 15 - 15 (1 bit)
access : read-only
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