\n

TC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection :

Registers

CTRLA

COUNT

PER

CC0

CC1

READREQ

CTRLBCLR

CTRLBSET

CTRLC

DBGCTRL

EVCTRL

INTENCLR

INTENSET

INTFLAG

STATUS


CTRLA

Control A
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLA CTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE MODE WAVEGEN PRESCALER RUNSTDBY PRESCSYNC

SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : write-only

ENABLE : Enable
bits : 1 - 1 (1 bit)

MODE : TC Mode
bits : 2 - 3 (2 bit)

Enumeration: MODESelect

0x0 : COUNT16

Counter in 16-bit mode

0x1 : COUNT8

Counter in 8-bit mode

0x2 : COUNT32

Counter in 32-bit mode

End of enumeration elements list.

WAVEGEN : Waveform Generation Operation
bits : 5 - 6 (2 bit)

Enumeration: WAVEGENSelect

0x0 : NFRQ


0x1 : MFRQ


0x2 : NPWM


0x3 : MPWM


End of enumeration elements list.

PRESCALER : Prescaler
bits : 8 - 10 (3 bit)

Enumeration: PRESCALERSelect

0x0 : DIV1

GCLK_TC

0x1 : DIV2

GCLK_TC/2

0x2 : DIV4

GCLK_TC/4

0x3 : DIV8

GCLK_TC/8

0x4 : DIV16

GCLK_TC/16

0x5 : DIV64

GCLK_TC/64

0x6 : DIV256

GCLK_TC/256

0x7 : DIV1024

GCLK_TC/1024

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 11 - 11 (1 bit)

PRESCSYNC : Prescaler and Counter Synchronization
bits : 12 - 13 (2 bit)

Enumeration: PRESCSYNCSelect

0x0 : GCLK

Reload or reset Counter on next GCLK

0x1 : PRESC

Reload or reset Counter on next prescaler clock

0x2 : RESYNC

Reload or reset Counter on next GCLK. Reset prescaler counter

End of enumeration elements list.


COUNT

COUNT16 Counter Value
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COUNT COUNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Counter Value
bits : 0 - 31 (32 bit)


PER

COUNT8 Period Value
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PER PER read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PER

PER : Period Value
bits : 0 - 7 (8 bit)


CC0

COUNT16 Compare/Capture
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC0 CC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Compare/Capture Value
bits : 0 - 31 (32 bit)


CC1

COUNT16 Compare/Capture
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC1 CC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Compare/Capture Value
bits : 0 - 31 (32 bit)


READREQ

Read Request
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

READREQ READREQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR RCONT RREQ

ADDR : Address
bits : 0 - 4 (5 bit)

RCONT : Read Continuously
bits : 14 - 14 (1 bit)

RREQ : Read Request
bits : 15 - 15 (1 bit)


CTRLBCLR

Control B Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLBCLR CTRLBCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DIR ONESHOT CMD

DIR : Counter Direction
bits : 0 - 0 (1 bit)

ONESHOT : One-Shot
bits : 2 - 2 (1 bit)

CMD : Command
bits : 6 - 7 (2 bit)

Enumeration: CMDSelect

0x0 : NONE

No action

0x1 : RETRIGGER

Force start, restart or retrigger

0x2 : STOP

Force stop

End of enumeration elements list.


CTRLBSET

Control B Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLBSET CTRLBSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DIR ONESHOT CMD

DIR : Counter Direction
bits : 0 - 0 (1 bit)

ONESHOT : One-shot
bits : 2 - 2 (1 bit)

CMD : Command
bits : 6 - 7 (2 bit)

Enumeration: CMDSelect

0x0 : NONE

No action

0x1 : RETRIGGER

Force start, restart or retrigger

0x2 : STOP

Force stop

End of enumeration elements list.


CTRLC

Control C
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLC CTRLC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INVEN0 INVEN1 CPTEN0 CPTEN1

INVEN0 : Output Waveform 0 Invert Enable
bits : 0 - 0 (1 bit)

INVEN1 : Output Waveform 1 Invert Enable
bits : 1 - 1 (1 bit)

CPTEN0 : Capture Channel 0 Enable
bits : 4 - 4 (1 bit)

CPTEN1 : Capture Channel 1 Enable
bits : 5 - 5 (1 bit)


DBGCTRL

Debug Control
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGCTRL DBGCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DBGRUN

DBGRUN : Debug Run Mode
bits : 0 - 0 (1 bit)


EVCTRL

Event Control
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVCTRL EVCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVACT TCINV TCEI OVFEO MCEO0 MCEO1

EVACT : Event Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : OFF

Event action disabled

0x1 : RETRIGGER

Start, restart or retrigger TC on event

0x2 : COUNT

Count on event

0x3 : START

Start TC on event

0x5 : PPW

Period captured into CC0 Pulse Width in CC1

0x6 : PWP

Period captured into CC1 Pulse Width on CC0

End of enumeration elements list.

TCINV : TC Inverted Event Input
bits : 4 - 4 (1 bit)

TCEI : TC Event Input
bits : 5 - 5 (1 bit)

OVFEO : Overflow/Underflow Event Output Enable
bits : 8 - 8 (1 bit)

MCEO0 : Match or Capture Channel 0 Event Output Enable
bits : 12 - 12 (1 bit)

MCEO1 : Match or Capture Channel 1 Event Output Enable
bits : 13 - 13 (1 bit)


INTENCLR

Interrupt Enable Clear
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVF ERR SYNCRDY MC0 MC1

OVF : Overflow Interrupt Enable
bits : 0 - 0 (1 bit)

ERR : Error Interrupt Enable
bits : 1 - 1 (1 bit)

SYNCRDY : Synchronization Ready Interrupt Enable
bits : 3 - 3 (1 bit)

MC0 : Match or Capture Channel 0 Interrupt Enable
bits : 4 - 4 (1 bit)

MC1 : Match or Capture Channel 1 Interrupt Enable
bits : 5 - 5 (1 bit)


INTENSET

Interrupt Enable Set
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVF ERR SYNCRDY MC0 MC1

OVF : Overflow Interrupt Enable
bits : 0 - 0 (1 bit)

ERR : Error Interrupt Enable
bits : 1 - 1 (1 bit)

SYNCRDY : Synchronization Ready Interrupt Enable
bits : 3 - 3 (1 bit)

MC0 : Match or Capture Channel 0 Interrupt Enable
bits : 4 - 4 (1 bit)

MC1 : Match or Capture Channel 1 Interrupt Enable
bits : 5 - 5 (1 bit)


INTFLAG

Interrupt Flag Status and Clear
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAG INTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVF ERR SYNCRDY MC0 MC1

OVF : Overflow
bits : 0 - 0 (1 bit)

ERR : Error
bits : 1 - 1 (1 bit)

SYNCRDY : Synchronization Ready
bits : 3 - 3 (1 bit)

MC0 : Match or Capture Channel 0
bits : 4 - 4 (1 bit)

MC1 : Match or Capture Channel 1
bits : 5 - 5 (1 bit)


STATUS

Status
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 STOP SLAVE SYNCBUSY

STOP : Stop
bits : 3 - 3 (1 bit)
access : read-only

SLAVE : Slave
bits : 4 - 4 (1 bit)
access : read-only

SYNCBUSY : Synchronization Busy
bits : 7 - 7 (1 bit)
access : read-only



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.