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RTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection :

Registers

CTRL

COUNT

CLOCK

PER

COMP0

ALARM1

COMP1

MASK1

READREQ

EVCTRL

INTENCLR

INTENSET

INTFLAG

STATUS

DBGCTRL

FREQCORR


CTRL

MODE2 Control
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE MODE CLKREP MATCHCLR PRESCALER

SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : write-only

ENABLE : Enable
bits : 1 - 1 (1 bit)

MODE : Operating Mode
bits : 2 - 3 (2 bit)

Enumeration: MODESelect

0x0 : COUNT32

Mode 0: 32-bit Counter

0x1 : COUNT16

Mode 1: 16-bit Counter

0x2 : CLOCK

Mode 2: Clock/Calendar

End of enumeration elements list.

CLKREP : Clock Representation
bits : 6 - 6 (1 bit)

MATCHCLR : Clear on Match
bits : 7 - 7 (1 bit)

PRESCALER : Prescaler
bits : 8 - 11 (4 bit)

Enumeration: PRESCALERSelect

0x0 : DIV1

CLK_RTC_CNT = GCLK_RTC/1

0x1 : DIV2

CLK_RTC_CNT = GCLK_RTC/2

0x2 : DIV4

CLK_RTC_CNT = GCLK_RTC/4

0x3 : DIV8

CLK_RTC_CNT = GCLK_RTC/8

0x4 : DIV16

CLK_RTC_CNT = GCLK_RTC/16

0x5 : DIV32

CLK_RTC_CNT = GCLK_RTC/32

0x6 : DIV64

CLK_RTC_CNT = GCLK_RTC/64

0x7 : DIV128

CLK_RTC_CNT = GCLK_RTC/128

0x8 : DIV256

CLK_RTC_CNT = GCLK_RTC/256

0x9 : DIV512

CLK_RTC_CNT = GCLK_RTC/512

0xa : DIV1024

CLK_RTC_CNT = GCLK_RTC/1024

End of enumeration elements list.


COUNT

MODE1 Counter Value
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COUNT COUNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Counter Value
bits : 0 - 15 (16 bit)


CLOCK

MODE2 Clock Value
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLOCK CLOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SECOND MINUTE HOUR DAY MONTH YEAR

SECOND : Second
bits : 0 - 5 (6 bit)

MINUTE : Minute
bits : 6 - 11 (6 bit)

HOUR : Hour
bits : 12 - 16 (5 bit)

Enumeration: HOURSelect

0x0 : AM

AM when CLKREP in 12-hour

0x10 : PM

Afternoon Hour

End of enumeration elements list.

DAY : Day
bits : 17 - 21 (5 bit)

MONTH : Month
bits : 22 - 25 (4 bit)

YEAR : Year
bits : 26 - 31 (6 bit)


PER

MODE1 Counter Period
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PER PER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PER

PER : Counter Period
bits : 0 - 15 (16 bit)


COMP0

MODE1 Compare n Value
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP0 COMP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP

COMP : Compare Value
bits : 0 - 15 (16 bit)


ALARM1

MODE2 Alarm n Value
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALARM1 ALARM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SECOND MINUTE HOUR DAY MONTH YEAR

SECOND : Second
bits : 0 - 5 (6 bit)

MINUTE : Minute
bits : 6 - 11 (6 bit)

HOUR : Hour
bits : 12 - 16 (5 bit)

Enumeration: HOURSelect

0x0 : AM

Morning hour

0x10 : PM

Afternoon hour

End of enumeration elements list.

DAY : Day
bits : 17 - 21 (5 bit)

MONTH : Month
bits : 22 - 25 (4 bit)

YEAR : Year
bits : 26 - 31 (6 bit)


COMP1

MODE1 Compare n Value
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP1 COMP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP

COMP : Compare Value
bits : 0 - 15 (16 bit)


MASK1

MODE2 Alarm n Mask
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MASK1 MASK1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEL

SEL : Alarm Mask Selection
bits : 0 - 2 (3 bit)

Enumeration: SELSelect

0x0 : OFF

Alarm Disabled

0x1 : SS

Match seconds only

0x2 : MMSS

Match seconds and minutes only

0x3 : HHMMSS

Match seconds, minutes, and hours only

0x4 : DDHHMMSS

Match seconds, minutes, hours, and days only

0x5 : MMDDHHMMSS

Match seconds, minutes, hours, days, and months only

0x6 : YYMMDDHHMMSS

Match seconds, minutes, hours, days, months, and years

End of enumeration elements list.


READREQ

Read Request
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

READREQ READREQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR RCONT RREQ

ADDR : Address
bits : 0 - 5 (6 bit)
access : read-only

RCONT : Read Continuously
bits : 14 - 14 (1 bit)

RREQ : Read Request
bits : 15 - 15 (1 bit)
access : write-only


EVCTRL

MODE2 Event Control
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVCTRL EVCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PEREO0 PEREO1 PEREO2 PEREO3 PEREO4 PEREO5 PEREO6 PEREO7 CMPEO0 ALARMEO0 CMPEO1 OVFEO

PEREO0 : Periodic Interval 0 Event Output Enable
bits : 0 - 0 (1 bit)

PEREO1 : Periodic Interval 1 Event Output Enable
bits : 1 - 1 (1 bit)

PEREO2 : Periodic Interval 2 Event Output Enable
bits : 2 - 2 (1 bit)

PEREO3 : Periodic Interval 3 Event Output Enable
bits : 3 - 3 (1 bit)

PEREO4 : Periodic Interval 4 Event Output Enable
bits : 4 - 4 (1 bit)

PEREO5 : Periodic Interval 5 Event Output Enable
bits : 5 - 5 (1 bit)

PEREO6 : Periodic Interval 6 Event Output Enable
bits : 6 - 6 (1 bit)

PEREO7 : Periodic Interval 7 Event Output Enable
bits : 7 - 7 (1 bit)

CMPEO0 : Compare 0 Event Output Enable
bits : 8 - 8 (1 bit)

ALARMEO0 : Alarm 0 Event Output Enable
bits : 8 - 8 (1 bit)

CMPEO1 : Compare 1 Event Output Enable
bits : 9 - 9 (1 bit)

OVFEO : Overflow Event Output Enable
bits : 15 - 15 (1 bit)


INTENCLR

MODE2 Interrupt Enable Clear
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMP0 ALARM0 CMP1 SYNCRDY OVF

CMP0 : Compare 0 Interrupt Enable
bits : 0 - 0 (1 bit)

ALARM0 : Alarm 0 Interrupt Enable
bits : 0 - 0 (1 bit)

CMP1 : Compare 1 Interrupt Enable
bits : 1 - 1 (1 bit)

SYNCRDY : Synchronization Ready Interrupt Enable
bits : 6 - 6 (1 bit)

OVF : Overflow Interrupt Enable
bits : 7 - 7 (1 bit)


INTENSET

MODE2 Interrupt Enable Set
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMP0 ALARM0 CMP1 SYNCRDY OVF

CMP0 : Compare 0 Interrupt Enable
bits : 0 - 0 (1 bit)

ALARM0 : Alarm 0 Interrupt Enable
bits : 0 - 0 (1 bit)

CMP1 : Compare 1 Interrupt Enable
bits : 1 - 1 (1 bit)

SYNCRDY : Synchronization Ready Interrupt Enable
bits : 6 - 6 (1 bit)

OVF : Overflow Interrupt Enable
bits : 7 - 7 (1 bit)


INTFLAG

MODE2 Interrupt Flag Status and Clear
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAG INTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMP0 ALARM0 CMP1 SYNCRDY OVF

CMP0 : Compare 0
bits : 0 - 0 (1 bit)

ALARM0 : Alarm 0
bits : 0 - 0 (1 bit)

CMP1 : Compare 1
bits : 1 - 1 (1 bit)

SYNCRDY : Synchronization Ready
bits : 6 - 6 (1 bit)

OVF : Overflow
bits : 7 - 7 (1 bit)


STATUS

Status
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SYNCBUSY

SYNCBUSY : Synchronization Busy
bits : 7 - 7 (1 bit)
access : read-only


DBGCTRL

Debug Control
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGCTRL DBGCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DBGRUN

DBGRUN : Run During Debug
bits : 0 - 0 (1 bit)


FREQCORR

Frequency Correction
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FREQCORR FREQCORR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 VALUE SIGN

VALUE : Correction Value
bits : 0 - 6 (7 bit)

SIGN : Correction Sign
bits : 7 - 7 (1 bit)



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