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FPB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

FP_CTRL

FP_COMP2

FP_COMP_BREAKPOINT_MODE2

FP_COMP3

FP_COMP_BREAKPOINT_MODE3

FP_REMAP

FP_COMP0

FP_COMP_BREAKPOINT_MODE0

FP_COMP1

FP_COMP_BREAKPOINT_MODE1

FP_LAR

FP_LSR

FP_DEVARCH

FP_DEVTYPE

FP_PIDR4

FP_PIDR5

FP_PIDR6

FP_PIDR7

FP_PIDR0

FP_PIDR1

FP_PIDR2

FP_PIDR3

FP_CIDR0

FP_CIDR1

FP_CIDR2

FP_CIDR3


FP_CTRL

Flash Patch Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FP_CTRL FP_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE KEY NUM_CODE NUM_LIT NUM_CODE_1 REV

ENABLE : Flash Patch global enable
bits : 0 - 0 (1 bit)

KEY : FP_CTRL write-enable key
bits : 1 - 1 (1 bit)

NUM_CODE : Number of implemented code comparators bits [3:0]
bits : 4 - 7 (4 bit)

NUM_LIT : Number of literal comparators
bits : 8 - 11 (4 bit)

NUM_CODE_1 : Number of implemented code comparators bits [6:4]
bits : 12 - 14 (3 bit)

REV : Revision
bits : 28 - 31 (4 bit)


FP_COMP2

Flash Patch Comparator Register n
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FP_COMP2 FP_COMP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BE FPADDR FE

BE : Breakpoint enable
bits : 0 - 0 (1 bit)

FPADDR : Flash Patch address
bits : 2 - 28 (27 bit)

FE : Flash Patch enable
bits : 31 - 31 (1 bit)


FP_COMP_BREAKPOINT_MODE2

Flash Patch Comparator Register n
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FP_COMP[%s]
reset_Mask : 0x0

FP_COMP_BREAKPOINT_MODE2 FP_COMP_BREAKPOINT_MODE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BE BPADDR

BE : Breakpoint enable
bits : 0 - 0 (1 bit)

BPADDR : Breakpoint address
bits : 1 - 31 (31 bit)


FP_COMP3

Flash Patch Comparator Register n
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FP_COMP3 FP_COMP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BE FPADDR FE

BE : Breakpoint enable
bits : 0 - 0 (1 bit)

FPADDR : Flash Patch address
bits : 2 - 28 (27 bit)

FE : Flash Patch enable
bits : 31 - 31 (1 bit)


FP_COMP_BREAKPOINT_MODE3

Flash Patch Comparator Register n
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FP_COMP[%s]
reset_Mask : 0x0

FP_COMP_BREAKPOINT_MODE3 FP_COMP_BREAKPOINT_MODE3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BE BPADDR

BE : Breakpoint enable
bits : 0 - 0 (1 bit)

BPADDR : Breakpoint address
bits : 1 - 31 (31 bit)


FP_REMAP

Flash Patch Remap Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FP_REMAP FP_REMAP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REMAP RMPSPT

REMAP : Remap address
bits : 5 - 28 (24 bit)

RMPSPT : Remap supported
bits : 29 - 29 (1 bit)


FP_COMP0

Flash Patch Comparator Register n
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FP_COMP0 FP_COMP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BE FPADDR FE

BE : Breakpoint enable
bits : 0 - 0 (1 bit)

FPADDR : Flash Patch address
bits : 2 - 28 (27 bit)

FE : Flash Patch enable
bits : 31 - 31 (1 bit)


FP_COMP_BREAKPOINT_MODE0

Flash Patch Comparator Register n
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FP_COMP[%s]
reset_Mask : 0x0

FP_COMP_BREAKPOINT_MODE0 FP_COMP_BREAKPOINT_MODE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BE BPADDR

BE : Breakpoint enable
bits : 0 - 0 (1 bit)

BPADDR : Breakpoint address
bits : 1 - 31 (31 bit)


FP_COMP1

Flash Patch Comparator Register n
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FP_COMP1 FP_COMP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BE FPADDR FE

BE : Breakpoint enable
bits : 0 - 0 (1 bit)

FPADDR : Flash Patch address
bits : 2 - 28 (27 bit)

FE : Flash Patch enable
bits : 31 - 31 (1 bit)


FP_COMP_BREAKPOINT_MODE1

Flash Patch Comparator Register n
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FP_COMP[%s]
reset_Mask : 0x0

FP_COMP_BREAKPOINT_MODE1 FP_COMP_BREAKPOINT_MODE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BE BPADDR

BE : Breakpoint enable
bits : 0 - 0 (1 bit)

BPADDR : Breakpoint address
bits : 1 - 31 (31 bit)


FP_LAR

FPB Software Lock Access Register
address_offset : 0xFB0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

FP_LAR FP_LAR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : Lock access control
bits : 0 - 31 (32 bit)

Enumeration: KEYSelect

0xC5ACCE55 : UNLOCK

Unlock key value

End of enumeration elements list.


FP_LSR

FPB Software Lock Status Register
address_offset : 0xFB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FP_LSR FP_LSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLI SLK nTT

SLI : Software Lock implemented
bits : 0 - 0 (1 bit)

SLK : Software Lock status
bits : 1 - 1 (1 bit)

nTT : Not thirty-two bit
bits : 2 - 2 (1 bit)


FP_DEVARCH

FPB Device Architecture Register
address_offset : 0xFBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FP_DEVARCH FP_DEVARCH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARCHPART ARCHVER REVISION PRESENT ARCHITECT

ARCHPART : Architecture Part
bits : 0 - 11 (12 bit)

ARCHVER : Architecture Version
bits : 12 - 15 (4 bit)

REVISION : Revision
bits : 16 - 19 (4 bit)

PRESENT : DEVARCH Present
bits : 20 - 20 (1 bit)

ARCHITECT : Architect
bits : 21 - 31 (11 bit)


FP_DEVTYPE

FPB Device Type Register
address_offset : 0xFCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FP_DEVTYPE FP_DEVTYPE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAJOR SUB

MAJOR : Major type
bits : 0 - 3 (4 bit)

SUB : Sub-type
bits : 4 - 7 (4 bit)


FP_PIDR4

FP Peripheral Identification Register 4
address_offset : 0xFD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FP_PIDR4 FP_PIDR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DES_2 SIZE

DES_2 : JEP106 continuation code
bits : 0 - 3 (4 bit)

SIZE : 4KB count
bits : 4 - 7 (4 bit)


FP_PIDR5

FP Peripheral Identification Register 5
address_offset : 0xFD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FP_PIDR5 FP_PIDR5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FP_PIDR6

FP Peripheral Identification Register 6
address_offset : 0xFD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FP_PIDR6 FP_PIDR6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FP_PIDR7

FP Peripheral Identification Register 7
address_offset : 0xFDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FP_PIDR7 FP_PIDR7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FP_PIDR0

FP Peripheral Identification Register 0
address_offset : 0xFE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FP_PIDR0 FP_PIDR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PART_0

PART_0 : Part number bits[7:0]
bits : 0 - 7 (8 bit)


FP_PIDR1

FP Peripheral Identification Register 1
address_offset : 0xFE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FP_PIDR1 FP_PIDR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PART_1 DES_0

PART_1 : Part number bits[11:8]
bits : 0 - 3 (4 bit)

DES_0 : JEP106 identification code bits [3:0]
bits : 4 - 7 (4 bit)


FP_PIDR2

FP Peripheral Identification Register 2
address_offset : 0xFE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FP_PIDR2 FP_PIDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DES_1 JEDEC REVISION

DES_1 : JEP106 identification code bits[6:4]
bits : 0 - 2 (3 bit)

JEDEC : JEDEC assignee value is used
bits : 3 - 3 (1 bit)

REVISION : Component revision
bits : 4 - 7 (4 bit)


FP_PIDR3

FP Peripheral Identification Register 3
address_offset : 0xFEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FP_PIDR3 FP_PIDR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMOD REVAND

CMOD : Customer Modified
bits : 0 - 3 (4 bit)

REVAND : RevAnd
bits : 4 - 7 (4 bit)


FP_CIDR0

FP Component Identification Register 0
address_offset : 0xFF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FP_CIDR0 FP_CIDR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRMBL_0

PRMBL_0 : CoreSight component identification preamble
bits : 0 - 7 (8 bit)


FP_CIDR1

FP Component Identification Register 1
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FP_CIDR1 FP_CIDR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRMBL_1 CLASS

PRMBL_1 : CoreSight component identification preamble
bits : 0 - 3 (4 bit)

CLASS : CoreSight component class
bits : 4 - 7 (4 bit)


FP_CIDR2

FP Component Identification Register 2
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FP_CIDR2 FP_CIDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRMBL_2

PRMBL_2 : CoreSight component identification preamble
bits : 0 - 7 (8 bit)


FP_CIDR3

FP Component Identification Register 3
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FP_CIDR3 FP_CIDR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRMBL_3

PRMBL_3 : CoreSight component identification preamble
bits : 0 - 7 (8 bit)



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