\n
address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :
Debug Halting Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C_DEBUGEN : Enable Halting debug
bits : 0 - 0 (1 bit)
C_HALT : Halt processor
bits : 1 - 1 (1 bit)
C_STEP : Enable single step
bits : 2 - 2 (1 bit)
C_MASKINTS : Mask PendSV, SysTick and external configurable interrupts
bits : 3 - 3 (1 bit)
S_SNAPSTALL : Snap stall control
bits : 5 - 5 (1 bit)
S_REGRDY : Register ready status
bits : 16 - 16 (1 bit)
S_HALT : Halted status
bits : 17 - 17 (1 bit)
S_SLEEP : Sleeping status
bits : 18 - 18 (1 bit)
S_LOCKUP : Lockup status
bits : 19 - 19 (1 bit)
S_SDE : Secure debug enabled
bits : 20 - 20 (1 bit)
S_RETIRE_ST : Retire sticky status
bits : 24 - 24 (1 bit)
S_RESET_ST : Reset sticky status
bits : 25 - 25 (1 bit)
S_RESTART_ST : Restart sticky status
bits : 26 - 26 (1 bit)
Debug Security Control and Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SBRSELEN : Secure Banked register select enable
bits : 0 - 0 (1 bit)
SBRSEL : Secure Banked register select
bits : 1 - 1 (1 bit)
CDS : Current domain Secure
bits : 16 - 16 (1 bit)
CDSKEY : CDS field write-enable key
bits : 17 - 17 (1 bit)
Debug Core Register Select Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
REGSEL : Register selector
bits : 0 - 6 (7 bit)
REGWnR : Register write/not-read access
bits : 16 - 16 (1 bit)
Debug Exception and Monitor Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VC_CORERESET : Core reset Halting debug vector catch enable
bits : 0 - 0 (1 bit)
VC_MMERR : MemManage exception Halting debug vector catch enable
bits : 4 - 4 (1 bit)
VC_NOCPERR : UsageFault exception coprocessor access Halting debug vector catch enable
bits : 5 - 5 (1 bit)
VC_CHKERR : UsageFault exception checking error Halting debug vector catch enable
bits : 6 - 6 (1 bit)
VC_STATERR : UsageFault exception state information error Halting debug vector catch enable
bits : 7 - 7 (1 bit)
VC_BUSERR : BusFault exception Halting debug vector catch enable
bits : 8 - 8 (1 bit)
VC_INTERR : Excception entry and return faults Halting debug vector catch enable
bits : 9 - 9 (1 bit)
VC_HARDERR : HardFault exception Halting debug vector catch enable
bits : 10 - 10 (1 bit)
VC_SFERR : SecureFault exception Halting debug vector catch enable
bits : 11 - 11 (1 bit)
MON_EN : DebugMonitor enable
bits : 16 - 16 (1 bit)
MON_PEND : DebugMonitor pending state
bits : 17 - 17 (1 bit)
MON_STEP : Enable DebugMonitor stepping
bits : 18 - 18 (1 bit)
MON_REQ : DebugMonitor semaphore bit
bits : 19 - 19 (1 bit)
SDME : Secure DebugMonitor enable
bits : 20 - 20 (1 bit)
TRCENA : Global DWT and ITM features enable
bits : 24 - 24 (1 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.