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CoreDebug

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :

Registers

DHCSR

DSCSR

DCRSR

DEMCR


DHCSR

Debug Halting Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHCSR DHCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C_DEBUGEN C_HALT C_STEP C_MASKINTS S_SNAPSTALL S_REGRDY S_HALT S_SLEEP S_LOCKUP S_SDE S_RETIRE_ST S_RESET_ST S_RESTART_ST

C_DEBUGEN : Enable Halting debug
bits : 0 - 0 (1 bit)

C_HALT : Halt processor
bits : 1 - 1 (1 bit)

C_STEP : Enable single step
bits : 2 - 2 (1 bit)

C_MASKINTS : Mask PendSV, SysTick and external configurable interrupts
bits : 3 - 3 (1 bit)

S_SNAPSTALL : Snap stall control
bits : 5 - 5 (1 bit)

S_REGRDY : Register ready status
bits : 16 - 16 (1 bit)

S_HALT : Halted status
bits : 17 - 17 (1 bit)

S_SLEEP : Sleeping status
bits : 18 - 18 (1 bit)

S_LOCKUP : Lockup status
bits : 19 - 19 (1 bit)

S_SDE : Secure debug enabled
bits : 20 - 20 (1 bit)

S_RETIRE_ST : Retire sticky status
bits : 24 - 24 (1 bit)

S_RESET_ST : Reset sticky status
bits : 25 - 25 (1 bit)

S_RESTART_ST : Restart sticky status
bits : 26 - 26 (1 bit)


DSCSR

Debug Security Control and Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSCSR DSCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBRSELEN SBRSEL CDS CDSKEY

SBRSELEN : Secure Banked register select enable
bits : 0 - 0 (1 bit)

SBRSEL : Secure Banked register select
bits : 1 - 1 (1 bit)

CDS : Current domain Secure
bits : 16 - 16 (1 bit)

CDSKEY : CDS field write-enable key
bits : 17 - 17 (1 bit)


DCRSR

Debug Core Register Select Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DCRSR DCRSR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGSEL REGWnR

REGSEL : Register selector
bits : 0 - 6 (7 bit)

REGWnR : Register write/not-read access
bits : 16 - 16 (1 bit)


DEMCR

Debug Exception and Monitor Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEMCR DEMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VC_CORERESET VC_MMERR VC_NOCPERR VC_CHKERR VC_STATERR VC_BUSERR VC_INTERR VC_HARDERR VC_SFERR MON_EN MON_PEND MON_STEP MON_REQ SDME TRCENA

VC_CORERESET : Core reset Halting debug vector catch enable
bits : 0 - 0 (1 bit)

VC_MMERR : MemManage exception Halting debug vector catch enable
bits : 4 - 4 (1 bit)

VC_NOCPERR : UsageFault exception coprocessor access Halting debug vector catch enable
bits : 5 - 5 (1 bit)

VC_CHKERR : UsageFault exception checking error Halting debug vector catch enable
bits : 6 - 6 (1 bit)

VC_STATERR : UsageFault exception state information error Halting debug vector catch enable
bits : 7 - 7 (1 bit)

VC_BUSERR : BusFault exception Halting debug vector catch enable
bits : 8 - 8 (1 bit)

VC_INTERR : Excception entry and return faults Halting debug vector catch enable
bits : 9 - 9 (1 bit)

VC_HARDERR : HardFault exception Halting debug vector catch enable
bits : 10 - 10 (1 bit)

VC_SFERR : SecureFault exception Halting debug vector catch enable
bits : 11 - 11 (1 bit)

MON_EN : DebugMonitor enable
bits : 16 - 16 (1 bit)

MON_PEND : DebugMonitor pending state
bits : 17 - 17 (1 bit)

MON_STEP : Enable DebugMonitor stepping
bits : 18 - 18 (1 bit)

MON_REQ : DebugMonitor semaphore bit
bits : 19 - 19 (1 bit)

SDME : Secure DebugMonitor enable
bits : 20 - 20 (1 bit)

TRCENA : Global DWT and ITM features enable
bits : 24 - 24 (1 bit)



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